Input Bus. Description

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1 isplsi 2032E In-System Programmable SuperFAST High Density PLD Features SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic 00% Functionally and JEDEC Upward Compatible with isplsi 2032 Devices HIGH PERFORMANCE E 2 CMOS TECHNOLOGY fmax 225 MHz Maximum Operating Frequency tpd 3.5 ns Propagation Delay TTL Compatible Inputs and Outputs 5V Programmable Logic Core ispjtag In-System Programmable via IEEE 49. (JTAG) Test Access Port User-Selectable 3.3V or 5V I/O (48-Pin Package Only) Supports Mixed Voltage Systems PCI Compatible Outputs (48-Pin Package Only) Open-Drain Output Option Electrically Erasable and Reprogrammable Non-Volatile Unused Product Term Shutdown Saves Power isplsi OFFERS THE FOLLOWING ADDED FEATURES Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality Reprogram Soldered Devices for Faster Prototyping OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Can Combine Glue Logic and Structured Designs Enhanced Pin Locking Capability Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control to Minimize Switching Noise Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity ispdesignexpert LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Superior Quality of Results Tightly Integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispanalyzer PC and UNIX Platforms Functional Block Diagram Input Bus Output Routing Pool (ORP) A0 A A2 A3 Description GLB Global Routing Pool (GRP) Logic Array D Q D Q D Q D Q A7 A6 A5 A4 Output Routing Pool (ORP) Input Bus 039Bisp/2000 The isplsi 2032E is a High Density Programmable Logic Device. The device contains 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The isplsi 2032E features 5V in-system programmability and in-system diagnostic capabilities. The isplsi 2032E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the isplsi 2032E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A.. A7 (see Figure ). There are a total of eight GLBs in the isplsi 2032E device. Each GLB is made up of four macrocells. Each GLB has 8 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. The device also has 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually Copyright 999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 9724, U.S.A. June 999 Tel. (503) ; -800-LATTICE; FAX (503) ; e_03

2 Functional Block Diagram Figure. isplsi 2032E Functional Block Diagram GOE 0 I/O 0 I/O I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 0 I/O I/O 2 I/O 3 I/O 4 I/O 5 TDI/IN 0 TDO/IN Input Bus Output Routing Pool (ORP) A0 A A2 A3 Global Routing Pool (GRP) A7 A6 A5 A4 Output Routing Pool (ORP) Input Bus I/O 3 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 2 I/O 20 I/O 9 I/O 8 I/O 7 I/O 6 TMS BSCAN CLK 0 CLK CLK 2 Notes: *Y and RESET are multiplexed on the same pin Y0 Y* TCK/Y2 039/2032E programmed to be a combinatorial input, output or bidirectional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 ma or sink 8 ma. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. By connecting the IO pins to a common 5V or 3.3V power supply, I/O output levels can be matched to 5V or 3.3V compatible voltages. When connected to a 5V supply, the I/O pins provide PCI-compatible output drive (48-pin device only). Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (see Figure ). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the ORP. Each isplsi 2032E device contains one Megablock. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the isplsi 2032E device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the isplsi 2032E are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispdesignexpert software tools. 2

3 Absolute Maximum Ratings Supply Voltage V cc to +7.0V Input Voltage Applied to V CC +.0V Off-State Output Voltage Applied to V CC +.0V Storage Temperature to 50 C Case Temp. with Power Applied to 25 C Max. Junction Temp. (T J ) with Power Applied C. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition SYMBOL PARAMETER Supply Voltage: Logic Core, Input Buffers IO 5V Supply Voltage: Output Drivers 3.3V VIL Input Low Voltage VIH Input High Voltage. 3.3V I/O operation not available for 44-pin packages. T A 0 C to +70 C MIN. MAX. UNITS V V V V 2.0 V cc + V Table /2032E Capacitance (T A 25 C, f.0 MHz) C C C SYMBOL PARAMETER TYP UNITS TEST CONDITIONS 2 Dedicated Input Capacitance 6 pf I/O Capacitance 7 pf V 5.0V, V 2.0V CC V 5.0V, V 2.0V Clock Capacitance 0 pf V 5.0V, V 2.0V 3 CC Y CC IN I/O Table /2032E Erase/Reprogram Specification PARAMETER MINIMUM MAXIMUM UNITS Erase/Reprogram Cycles 0,000 Cycles Table /2032E 3

4 Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 0% to 90% to 3.0V.5 ns Figure 2. Test Load + 5V Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level..5v.5v See Figure 2 Table /2032E Device Output R R2 CL* Test Point Output Load Conditions (see Figure 2) TEST CONDITION R R2 CL A 470Ω 390Ω 35pF *CL includes Test Fixture and Probe Capacitance. 023A B C Active High Active Low Active High to Z at V OH-0.5V Active Low to Z at V OL+0.5V 390Ω 35pF 470Ω 390Ω 35pF 390Ω 5pF 470Ω 390Ω 5pF Table A DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL VOL VOH IIL IIH PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current CONDITION MIN. TYP. 3 MAX. UNITS I OL 8 ma I OH -4 ma 0V V IN V IL (Max.) V V µa (V CCIO - 0.2)V V IN V CCIO 0 µa V CCIO V IN 5.25V 0 µa IIL-PU I/O Active Pull-Up Current, non-pci 0V V IN 2.0V µa I/O Active Pull-Up Current, PCI 5 0V V IN 2.0V µa IOS Output Short Circuit Current, non-pci V CCIO 5V, V OUT 0.5V -200 ma Output Short Circuit Current, PCI 5 V CCIO 5.0V or 3.3V, V OUT 0.5V -240 ma ICC 2,4,6 Operating Power Supply Current V IL 0.0V, V IH 3.0V -225/ ma f TOGGLE MHz Others 65 ma Table /2032E. One output at a time for a maximum duration of one second (V OUT 0.5V). Characterized, but not 00% tested. 2. Meaured using two 6-bit counters. 3. Typical values are at V CC 5V and T A 25 C. 4. Unused inputs held at 0.0V. 5. Available in 48-pin package only. 6. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I CC. 4

5 External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST # 2 DESCRIPTION COND. MIN. MAX. MIN. MAX. MIN. MAX. UNITS tpd A Data Prop. Delay, 4PT Bypass, ORP Bypass ns tpd2 A 2 Data Prop. Delay ns fmax A 3 Clk Frequency with Int. Feedback MHz fmax (Ext.) 4 Clk Frequency with Ext. Feedback ( tsu2 + tco) MHz fmax (Tog.) 5 Clk Frequency, Max. Toggle MHz tsu 6 GLB Reg. Setup Time before Clk, 4 PT Bypass ns tco A 7 GLB Reg. Clk to Output Delay, ORP Bypass ns th 8 GLB Reg. Hold Time after Clk, 4 PT Bypass ns tsu2 9 GLB Reg. Setup Time before Clk ns tco2 0 GLB Reg. Clk to Output Delay ns th2 GLB Reg. Hold Time after Clk ns tr A 2 Ext. Reset Pin to Output Delay, ORP Bypass ns trw 3 Ext. Reset Pulse Duration ns tptoeen B 4 Input to Output Enable ns tptoedis C 5 Input to Output Disable ns tgoeen B 6 Global OE Output Enable ns tgoedis C 7 Global OE Output Disable ns twh 8 Ext. Synch. Clk Pulse Duration, High ns twl 9 Ext. Synch. Clk Pulse Duration, Low ns. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 6-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. USE 2032E-225 FOR NEW DESIGNS Table A/2032E 5

6 External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST # 2 DESCRIPTION COND. MIN. MAX. MIN. MAX. UNITS tpd A Data Propagation Delay, 4PT Bypass, ORP Bypass ns tpd2 A 2 Data Propagation Delay ns fmax A 3 Clock Frequency with Internal Feedback 3 37 MHz fmax (Ext.) 4 Clock Frequency with External Feedback ( tsu2 + tco) MHz fmax (Tog.) 5 Clock Frequency, Max. Toggle MHz tsu 6 GLB Register Setup Time before Clock, 4 PT Bypass ns tco A 7 GLB Register Clock to Output Delay, ORP Bypass ns th 8 GLB Register Hold Time after Clock, 4 PT Bypass ns tsu2 9 GLB Register Setup Time before Clock ns tco2 0 GLB Register Clock to Output Delay ns th2 GLB Register Hold Time after Clock ns tr A 2 External Reset Pin to Output Delay, ORP Bypass ns trw 3 External Reset Pulse Duration ns tptoeen B 4 Input to Output Enable ns tptoedis C 5 Input to Output Disable ns tgoeen B 6 Global OE Output Enable ns tgoedis C 7 Global OE Output Disable ns twh 8 External Synchronous Clock Pulse Duration, High ns twl 9 External Synchronous Clock Pulse Duration, Low ns. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 6-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Table B/2032E 6

7 Internal Timing Parameters Over Recommended Operating Conditions PARAMETER # 2 DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNITS Inputs tio 20 Input Buffer Delay ns tdin 2 Dedicated Input Delay ns GRP tgrp 22 GRP Delay ns GLB t4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) ns t4ptbpr 24 4 Product Term Bypass Path Delay (Registered) ns tptxor 25 Product Term/XOR Path Delay ns t20ptxor Product Term/XOR Path Delay ns txoradj 27 3 XOR Adjacent Path Delay ns tgbp 28 GLB Register Bypass Delay ns tgsu 29 GLB Register Setup Time before Clock ns tgh 30 GLB Register Hold Time after Clock ns tgco 3 GLB Register Clock to Output Delay ns tgro 32 GLB Register Reset to Output Delay ns tptre 33 GLB Product Term Reset to Register Delay ns tptoe 34 GLB Product Term Output Enable to I/O Cell Delay ns tptck 35 GLB Product Term Clock Delay ns ORP torp 36 ORP Delay.0.0. ns torpbp 37 ORP Bypass Delay ns Outputs tob 38 Output Buffer Delay ns tsl 39 Output Slew Limited Delay Adder ns toen 40 I/O Cell OE to Output Enabled ns todis 4 I/O Cell OE to Output Disabled ns tgoe 42 Global Output Enable ns Clocks tgy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns tgy/2 44 Clock Delay, Y or Y2 to Global GLB Clock Line ns Global Reset tgr 45 Global Reset to GLB ns. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. USE 2032E-225 FOR NEW DESIGNS Table A/2032E 7

8 Internal Timing Parameters PARAMETER Inputs # 2 DESCRIPTION -35 MIN. MAX. -0 MIN. MAX. tio 20 Input Buffer Delay..7 ns tdin 2 Dedicated Input Delay ns GRP tgrp 22 GRP Delay.3.7 ns GLB t4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) ns t4ptbpr 24 4 Product Term Bypass Path Delay (Registered) ns tptxor 25 Product Term/XOR Path Delay ns t20ptxor Product Term/XOR Path Delay ns txoradj 27 3 XOR Adjacent Path Delay ns tgbp 28 GLB Register Bypass Delay ns tgsu 29 GLB Register Setup Time before Clock ns tgh 30 GLB Register Hold Time after Clock ns tgco 3 GLB Register Clock to Output Delay ns tgro 32 GLB Register Reset to Output Delay..8 ns tptre 33 GLB Product Term Reset to Register Delay ns tptoe 34 GLB Product Term Output Enable to I/O Cell Delay ns tptck 35 GLB Product Term Clock Delay ns ORP torp 36 ORP Delay.3.5 ns torpbp 37 ORP Bypass Delay ns Outputs tob 38 Output Buffer Delay.2.2 ns tsl 39 Output Slew Limited Delay Adder ns toen 40 I/O Cell OE to Output Enabled ns todis 4 I/O Cell OE to Output Disabled ns tgoe 42 Global Output Enable ns Clocks tgy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns tgy/2 44 Clock Delay, Y or Y2 to Global GLB Clock Line ns Global Reset tgr 45 Global Reset to GLB ns. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. UNITS Table B/2032E 8

9 isplsi 2032E Timing Model I/O Cell GRP GLB ORP I/O Cell Feedback Ded. In I/O Pin (Input) Reset #2 I/O Delay GRP Reg 4 PT Bypass GLB Reg Bypass ORP Bypass #20 #22 #24 #28 #37 #45 20 PT XOR Delays #25, 26, 27 Comb 4 PT Bypass #23 GLB Reg Delay D Q RST #29, 30, 3, 32 ORP Delay #36 #38, #39 I/O Pin (Output) Control PTs #33, 34, 35 RE OE CK #40, 4 Y0,,2 #43, 44 GOE 0 #42 049/2032E Derivations of tsu, th and tco from the Product Term Clock tsu Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) 2.7 ( ) + (0.8) - ( ) th tco Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) ( ) + (.7) - ( ) Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#3) + (#36 + #38) ( ) + (0.7) + (.0 +.0) Note: Calculations are based upon timing specifications for the isplsi 2032E-225L Table /2032E 9

10 Power Consumption Power consumption in the isplsi 2032E device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure 3 shows the relationship between power and operating speed. Figure 3. Typical Device Power Consumption vs fmax 50 isplsi 2032E-225 and ICC (ma) isplsi 2032E-80 and Slower fmax (MHz) Notes: Configuration of two 6-bit counters Typical current at 5V, 25 C I CC can be estimated for the isplsi 2032E using the following equation: For 2032E-225 and -200: ICC (# of PTs *.3) + (# of nets * Max freq * ) For 2032E-80 and Slower: ICC (# of PTs *.02) + (# of nets * Max freq * ) Where: # of PTs Number of Product Terms used in design # of nets Number of Signals used in device Max freq Highest Clock Frequency to the device (in MHz) The I CC estimate is based on typical conditions (V CC 5.0V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of I CC is sensitive to operating conditions and the program in the device, the actual I CC should be verified. 027A/2032E 0

11 Pin Description NAME I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O I/O 2 - I/O 5 I/O 6 - I/O 9 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 3 44-PIN PLCC PIN NUMBERS 5, 9, 25, 29, 37, 4, 3, 7, 6, 20, 26, 30, 38, 42, 4, 8, 7, 2, 27, 3, 39, 43, 5, 9, 8, 22, 28, 32, 40, 44, 6, 0 44-PIN TQFP PIN NUMBERS 9, 3, 9, 23, 3 35, 4,, 0, 4, 20, 24, 32, 36, 42, 2,, 5, 2, 25, 33, 37, 43, 3, 2, 6, 22, 26, 34, 38, 44, 4 48-PIN TQFP PIN NUMBERS 9, 4, 20, 25, 33, 38, 44,, 0, 5, 2, 26, 34, 39, 45, 2,, 6, 22, 27, 35, 40, 46, 3, 3, 7, 23, 28, 37, 4, 47, 4 DESCRIPTION Input/Output Pins These are the general purpose I/O pins used by the logic array. GOE 0 Y0 RESET/Y BSCAN TDI/IN 0 TMS/NC 2 TDO/IN TCK/Y2 IO , 23 2, 34 7, 39 6, 28. Pins have dual function capability. 2. NC pins are not to be connected to any active signals, V CC or , 8, 36, 42 6, 30 24, 48 Global Output Enable input pin. Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. This pin performs two functions: - Dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. - Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Input Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. Input This pin performs two functions. When BSCAN is logic low, it functions as an input pin to load programming data into the device. TDI/IN0 also is used as one of the two control pins for the ISP state machine. When BSCAN is high, it functions as a dedicated input pin. Input When in ISP mode, controls operation of ISP state machine. Output/Input This pin performs two functions. When BSCAN is logic low, it functions as an output pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. Input This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Serial Shift Register. When BSCAN is high, it functions as a dedicated clock input. This clock input is brought into the Clock Distribution Network and can be routed to any GLB and/or I/O cell on the device. Ground () V CC Supply voltage for output drivers, 5V or 3.3V. All IO pins must be connected to the same voltage level. Table /2032E

12 Pin Configuration isplsi 2032E 44-Pin PLCC Pinout Diagram I/O 27 I/O 26 I/O 25 I/O 24 GOE 0 I/O 23 I/O 22 I/O 2 I/O 20 I/O I/O I/O 8 I/O I/O 7 I/O I/O 6 I/O TMS/NC 2 Y0 2 isplsi 2032E RESET/Y BSCAN TDI/IN Top View TCK/Y2 I/O 5 I/O I/O 4 I/O 6 30 I/O 3 I/O I/O I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 TDO/IN I/O 8 I/O 9 I/O 0 I/O 44PLCC/2032E. Pins have dual function capability. 2. NC pins are not to be connected to any active signals, V CC or. isplsi 2032E 44-Pin TQFP Pinout Diagram I/O 27 I/O 26 I/O 25 I/O 24 GOE 0 I/O 23 I/O 22 I/O 2 I/O 20 I/O I/O I/O 8 I/O I/O 7 I/O I/O 6 I/O 3 Y0 BSCAN TDI/IN isplsi 2032E Top View TMS/NC 2 RESET/Y TCK/Y2 I/O 5 I/O I/O 4 I/O 0 24 I/O 3 I/O 2 23 I/O I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 TDO/IN I/O 8 I/O 9 I/O 0 I/O 44TQFP/2032E. Pins have dual function capability. 2. NC pins are not to be connected to any active signals, V CC or. 2

13 Pin Configuration isplsi 2032E 48-Pin TQFP Pinout Diagram IO I/O 27 I/O 26 I/O 25 I/O 24 GOE 0 I/O 23 I/O 22 I/O 2 I/O 20 I/O I/O I/O I/O 8 I/O I/O 7 I/O I/O 6 Y0 BSCAN TDI/IN isplsi 2032E Top View TMS/NC 2 RESET/Y TCK/Y2 I/O I/O 5 I/O 0 27 I/O 4 I/O 2 26 I/O I/O I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 TDO/IN I/O 8 I/O 9 I/O 0 I/O IO 48TQFP/2032E. Pins have dual function capability. 2. NC pins are not to be connected to any active signals, V CC or. 3

14 Part Number Description isplsi 2032E XXX X XXX X Device Family Device Number Speed MHz fmax MHz fmax MHz fmax MHz fmax 0 0 MHz fmax Grade Blank Commercial Package J44 PLCC T44 TQFP T48 TQFP Power L Low 022/2032E isplsi 2032E Ordering Information COMMERCIAL FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE isplsi 2032E-225LJ44 44-Pin PLCC isplsi 2032E-225LT44 44-Pin TQFP isplsi 2032E-225LT48 48-Pin TQFP isplsi 2032E-200LJ44* 44-Pin PLCC isplsi 2032E-200LT44* 44-Pin TQFP isplsi 2032E-200LT48* 48-Pin TQFP isplsi isplsi 2032E-80LJ44 44-Pin PLCC *2032E-225 recommended for new designs. isplsi 2032E-80LT44 isplsi 2032E-80LT48 isplsi 2032E-0LT44 isplsi 2032E-0LT48 44-Pin TQFP 48-Pin TQFP isplsi 2032E-35LJ44 isplsi 2032E-35LT44 44-Pin PLCC 44-Pin TQFP isplsi 2032E-35LT48 48-Pin TQFP isplsi 2032E-0LJ44 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP Table 2-004/2032E 4

Input Bus. Description

Input Bus. Description isplsi 2032E In-System Programmable SuperFAST High Density PLD Features SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global