User s Guide. Mixed Signal DSP Solutions SLLU011

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1 User s Guide July 2000 Mixed Signal DSP Solutions SLLU011

2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated

3 How to Use This Manual Preface Read This First About This Manual The Texas Instruments TLK2201 Serdes evaluation module (EVM) board is used to evaluate the TLK2201 device(vqfp) and associated optical interface (GBIC Module) for point-to-point data transmission applications. The board enables the designer to connect 50-Ω parallel buses to both transmitter and receiver connectors. Using high speed PLL technology, the TLK2201 serializes and transmits data along one differential pair. The receiver part of the device deserializes and presents data on the parallel bus. The highspeed (up to 1.6 Gbps) data lines interface to four 50-Ω controlled-impedance SMA connectors. The designer can either use this copper interface or, with small solder modifications, send the high-speed data to a GBIC-compatible laser module for an optical interface (not provided). How to Use This Manual This document contains the following chapters: Chapter 1 Introduction Chapter 2 Typical Test and Setup Configurations Appendix A Schematics, Board Layouts, and GBIC Configuration Read This First iii

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5 Running Title Attribute Reference Contents 1 Introduction TLK2201 EVM Kit Contents TLK2201 EVM Board Configuration Test and Setup Configurations Typical Test and Setup Configurations PCB Construction and Characteristics A Schematics, Board Layouts, and GBIC Configurations A-1 Figures 2 1 TLK2201 External Serial Loopback Test Configuration TLK2201EVM Serial PRBS Self-Test Configuration TLK2201EVM Serial PRBS BERT Test Configuration TLK2201EVM Layer Construction A 1 TLK2201EVM Transceiver Schematic A-2 A 2 Optical Transceiver Configuration A-3 A 3 Top Layer A-5 A 4 Layers 2 and A-6 A 5 Power Plane Layer A-7 A 6 GBIC and JTAG Layer A-8 A 7 Bottom Layer A-9 Tables 1 1 Default Transceiver-Board Configuration as Shipped Configuration Changes Necessary for DC Coupling of the High-Speed Signals A 1 TLK2201EVM Transceiver Bill of Materials A-4 Contents v

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7 Chapter 1 Introduction The Texas Instruments (TI) TLK2201 Serdes evaluation module (EVM) board is used to evaluate the TLK2201 device (VQFP) and associated optical interface (gigabit interface connector (GBIC) optics module) for point-to-point data transmission applications. The board enables the designer to connect 50-Ω parallel buses to both the transmitter and receiver parallel connectors. Using high speed PLL technology, the TLK2201 serializes data and transmits this data along a differential pair. The receiver part of the device deserializes and presents the data on the parallel bus. For proper use of this device, users must provide dc-balanced encoded data on the parallel bus (that is, 8b/10b). The high-speed (up to 1.6 Gbps) data lines interface to four 50-Ω controlled-impedance SMA connectors. The designer can either use this copper interface directly or use steering resistors to direct the high-speed side to the 75-Ω GBIC-compatible optical interface. The board can be used to evaluate device parameters while acting as a guide for high-speed board layout. The evaluation board can be used as daughterboards that are plugged into new or existing designs. Since the TLK2201 operates over a wide range of frequencies, the designer will need to optimize the design for the frequency of interest. Additionally, the designer may wish to use buried transmission lines and provide additional noise attenuation and EMI suppression to optimize the end product. Topic Page 1.1 TLK2201 EVM Kit Contents TLK2201 EVM Board Configuration Introduction 1-1

8 TLK2201 EVM Kit Contents As the frequency of operation increases, the board designer must take special care to ensure that the highest signal integrity is maintained. To achieve this, the board s impedance is controlled to 50 Ω (75 Ω for the GBIC interface) for both the high-speed differential serial and parallel data connections. In addition, board impedance mismatches are reduced by designing the component pad size to be as close as possible to the width of the connecting transmission lines. Vias are minimized and, when necessary, placed as close as possible to the device drivers. Since the board contains both serial and parallel transmission lines, care was taken to control both impedance and trace-length mismatch (board skew). Overall, the board layout is designed and optimized to support high-speed operation. Thus, understanding impedance control and transmission-line effects is crucial when designing high-speed boards. Some of the advanced features offered by this board include: PCB (printed-circuit board) is designed for high-speed signal integrity. Flexibility the PCB can be configured for copper or optical interfaces. SMA and parallel fixtures are easily connected to test equipment. All input/output signals are accessible for rapid prototyping. Analog and digital power planes can be supplied through separate banana jacks for isolation, or can be combined using ferrite bridging networks. Series termination resistors provide parallel RD outputs. Onboard capacitors provide ac coupling of high-speed signals. 1.1 TLK2201 EVM Kit Contents TLK2201 EVM board (TLK2201 Rev 1.0) TLK2201 EVM kit documentation (this document) 1.2 TLK2201 EVM Board Configuration The TLK2201 EVM board gives the developer various options for operation, many of which are jumper-selectable. Other options can be either soldered into the EVM or connected through input connectors. The TX and RX parallel connectors, P3 and P5 of Figures A 8 and A 10 in Appendix A, provide a connection for both transmitted and received paralleldata busing. The reference clock is supplied through SMA connector J11, and jumper J10 must be installed between pins 1 and 2. A direct clock connection can also be made to J10 between the center and ground pins. The high-speed serial data is transmitted through SMA connectors J1 and J2. The received recovered clock (RBC0 and RBC1) is output through header P5. Received data connects through SMA connectors J3 and J4 on the RX side of the board. Header J9 provides static signals (normally pulled high) to configure the device for different modes of operation. Header J7 is for the optical transceiver s configuration and error checking. Refer to your specific GBIC-module documentation for proper configuration of this header. 1-2

9 TLK2201 EVM Board Configuration The power planes are split three ways to provide power to different parts of the board. This prevents coupling of switching noise between the analog and digital sections of the TLK2201, and provides voltage isolation for the laser section. The laser section of the board requires 5 V (GBIC-dependent) and is energized through the V CC connector. The V DD and V DDA connectors require 2.5 V and are joined together by removable jumpers TP1 and TP3 that are installed in the default configuration. Thus, only the V DD connection is necessary to energize the TLK2201 device in the default configuration. In all sections of the board, the ground planes are common and each ground plane is tied together at every component ground connection. See Appendix A, Schematics, Board Layouts, and BGIC Configurations, for detailed schematic and layout. The board is normally delivered in a default configuration that requires external clock and data inputs. The TLK2201 is shipped with jumpers for default operation. Table 1 1 shows the default configuration for sending data. Table 1 1. Default Transceiver-Board Configuration as Shipped Designator Function Condition J10 REF CLK SEL Jumper installed provides a method of supplying a input clock to the board J9 RBCMODE Jumper not installed (logic 1) for a 1/10 baud-rate clock on RBC0 (a non-ddr mode) J9 ENABLE Jumper not installed (logic 1) this pulls up the enable pin for normal operation J9 SYNC_EN Jumper installed (logic 0) disables the TLK2201 comma-detection circuitry J9 LOOPEN Jumper installed (logic 0) disables the TLK2201 internal loopback mode J9 TEST_EN Jumper installed (logic 0) disables the TLK2201 test mode J9 PRBSEN Jumper installed (logic 0) disables the TLK2201 PRBS internal production test mode J9 MODESEL Jumper installed (logic 0) puts the parallel buses in a 10-bit mode (disables the DDR mode) TP1, TP3 bridge A Joins the V DD and V DDA power planes C14, C15 TX ac-coupling capacitors C22, C23 RX ac-coupling capacitors C18, C19 TX ac-coupling to GBIC C20, 21 RX ac-coupling to GBIC These capacitors (normally installed) are provided to ac-couple the transmitted signal. These capacitors (normally installed) are provided to ac-couple the received signal. These capacitors (normally not installed) are provided to ac-couple the TLK2201 transmitted data to the 75-Ω GBIC interface. These capacitors (normally not installed) are provided to ac-couple the 75-Ω GBIC receiver data to the TLK2201. Introduction 1-3

10 TLK2201 EVM Board Configuration Table 1 2. Configuration Changes Necessary for DC Coupling of the High-Speed Signals Designator Function Condition or Changes Necessary for DC Coupling C14, C15 TX AC coupling capacitors Install zero-ohm resistors C16, C17 RX AC coupling capacitors Install zero-ohm resistors 1-4

11 Chapter 2 Test and Setup Configurations This chapter presents the typical test and setup configurations used to evaluate and test the transceiver. The printed-circuit board construction and characteristics are included in the second section of this chapter. Topic Page 2.1 Typical Test and Setup Configurations PCB Construction and Characteristics Test and Setup Configurations 2-1

12 Typical Test and Setup Configurations 2.1 Typical Test and Setup Configurations The following configurations are used to evaluate and test the TLK2201 transceiver. The first configuration is an external serial loopback of the high-speed signals shown in Figure 2 1. The serial loopback allows the designer to evaluate most of the functions of the transmitter and receiver sections of the TLK2201 device. To test a system, a parallel-bit error-rate tester (BERT) generates a predefined dc-balanced parallel-bit pattern. The pattern is connected to the transmitter through parallel connectors TD0 TD9 (TD0 TD4 for DDR mode). The TLK2201 device serializes and presents the data on the highspeed serial pair. The serial TX data is then looped back to the receiver side and the device deserializes and presents the data on the receive side RD0 RD9 (RD0 RD4 for DDR mode). The data is received by the BERT and compared against the transmitted pattern and monitored for valid data and errors. If any bit errors are received, a bit-error rate is evaluated at the parallel-receive BERT. Figure 2 1. TLK2201 External Serial Loopback Test Configuration Jumper Selection RBCMODE ENABLE HP8133A Pulse Generator SYNC_EN LOOP_EN TEST_EN J9 EXT INPUT Channel 1 O/P PRBS_EN MODESEL Parallel BERT CLK OUT TX Data Out 0-9 Transmitter BERT 10 bits TD 0-9 REF_CLK TX+ TX CLK IN RBC_CLK RX Data In 0-9 Receiver BERT 10 bits RD 0-9 RX+ RX TLK2201EVM Evaluation Board 2-2

13 Typical Test and Setup Configurations If a parallel BERT is not available, the designer can take advantage of the built-in-test mode of the device, see Figure 2 2. If the designer asserts the PRBSEN pin high, a pseudo random bit pattern will be transmitted. This pin also puts the receiver in a mode to detect a valid PRBS pattern. A valid pattern is indicated by the SYNC_PASS pin indicating high. This test only validates the high-speed serial portion of the device and system interconnects. The PRBS pattern is compatible with most serial BERT test equipment. This function allows the operator to isolate and test the transmitter and receiver independently. A typical configuration is shown in Figure 2 3. The dashed lines represent optional connections that can be made for monitoring eye patterns and measuring jitter. Figure 2 2. TLK2201EVM Serial PRBS Self-Test Configuration Jumper Selection RBCMODE ENABLE SYNC_EN LOOP_EN TEST_EN PRBS_EN J9 Channel 1 O/P HP8133A Pulse Generator EXT INPUT TRIGGER OUT Digital Oscilloscope CH1 CH2 HP83480 or Tek Trigger MODESEL REF_CLK Channel 1 PRBS 2^7-1 TX TX+ TDS820 Digital Oscilloscope SYNC_PASS RX+ RD 0-9(4) TLK2201EVM Evaluation Board RX PRBS 2^7-1 Test and Setup Configurations 2-3

14 Typical Test and Setup Configurations Figure 2 3. TLK2201EVM Serial PRBS BERT Test Configuration Jumper Selection RBCMODE ENABLE SYNC_EN HP8133A Pulse Generator EXT INPUT CLK/10 Digital Oscilloscope HP83480 or Tek LOOP_EN TEST_EN J9 Channel 1 O/P TRIGGER OUT CH1 CH2 Trigger PRBS_EN MODESEL REF_CLK Serial BERT HP7004A 3 Gbps Channel 1 PRBS 2^7-1 TX Receiver BERT Data In TX+ Transmitter BERT TDS820 Digital Oscilloscope SYNC_PASS RX+ Data Out RD 0-9(4) RX PRBS 2^7-1 Data Out CLK OUT TLK2201EVM Evaluation Board 2-4

15 PCB Construction and Characteristics 2.2 PCB Construction and Characteristics The PCB characteristics are calculated and based on the layer construction and trace width of the board. Figure 2 4. TLK2201EVM Layer Construction Layer 1 Layer 2 Layer 3 Layer 4 Layer 5 Layer 6 14 Mil 5.5 Mil 21 Mil 9.5 Mil 6 Mil Top 50 Ω Ω 2 Solder 50 Ω Notes: 1) All cores consist of 1 oz Cu. 2) Trace width A) 25 mils (for 50-Ω layer 1) B) 11.8 mils (for 75-Ω layer 4) C) 11.8 mils (for 50-Ω layer 6) 3) Overall board thickness is 62 mils ±5 mil 4) Copper and solder mask adds approximately 10 mils to the overall board thickness 5) Impedance is 50 Ω ±10% 6) Material is G-Tek. Dielectric constant = 3.9 7) For overall thickness: add 1.2 to 1.4 mils for each metal layer in the stack Test and Setup Configurations 2-5

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17 Appendix A Schematics, Board Layouts, and GBIC Configurations This appendix contains the schematics, bill of materials, and board layouts for the TLK2201EVM transceiver board. Schematics, Board Layouts, and GBIC Configurations A-1

18 A-2 Figure A 1.TLK2201EVM Transceiver Schematic C12 C13 C22 4.7u C23 L3 J6 R9 1k D1 C27 C28 R13 0 J8 C32 C29 C31 C30 10k R24 10k R23 10k R21 10k R20 10k R25 10k R22 10k R17 10k R18 10k R19 R14 open 10k R16 TD1 TD3 TD0 TD P3 TD J9 MODESEL TEST_EN LOOP_EN SYNC_EN R36 0 TD7 TD5 TD6 TD4 TD9 PRBSEN R37 open RBCMODE ENABLE A2 C10 C TP1 Split power plane L2 A1 Split power plane C2 C1 A1 J3 A1 GBIC_TXN GBIC_TXP C14 C18 C19 J1 J2 C15 C16 C3 C R11 A1 C43 C40 A1 A1 C41 C42 C39 TRST TMS TP3 C34 C35 C33 C36 L4 C24 C25 10uF C37 C38 32 RBCMODE 27 TDO 18 PLL 16 PRBSEN 17 TEN 43 RD RD3 40 RD4 39 RD5 38 RD RD7 35 RD8 34 RD9 31 RBC0 30 RBC ENABLE 26 LOS SYNCEN REFCLK LOOPEN 15 MODESEL TD9 12 TD8 11 TD TD6 8 TD5 7 TD A 61 TXN 62 TXP TD0 3 TD1 4 TD2 5 6 TD3 64 PLL 44 RD1 51 A 52 RXN 59 A 58 A 57 A 54 RXP 53 A 45 RD TDI 47 SYNC/PASS 49 TCLK 55 TMS 56 TRSTN 50 U1 TLK2201 C45 TD4 TD3 TD2 TD0 TD1 R2 open C4 C5 J5 VCC A1 A1 J4 A1 C17 C21 R1 open TP2 C6 GBIC_RXN GBIC_RXP C9 C8 C7 L1 Split power plane VCC R6 R3 R4 R5 R7 R8 VCC TRST TX_FAULT RX_LOS MOD_DEF(0) MOD_DEF(2) MOD_DEF(1) KEY TX_DISABLE GBIC_RXP TRST GBIC_RXN GBIC CONNECTOR VCC P P5 RD0 SYNC/PASS RD3 RD2 RD1 RD4A RSV RD2 RD0 RD3 RD1 SYNC/PASS GBIC_TXN GBIC_TXP R10 open 49.9 R12 C26 C44 TDO TMS TCLK_RET J7 TMS TDO RSV P2 TDI R15 CLK RSV R28 R27 R29 R26 C46 R35 C51 R38 R45 R33 R34 C48 R32 R30 R31 RD8 RD9 RD4A RD5 RBC0 RD6 RD7 RD8 RD6 RD7 RD9 RBC1 RBC0 LOS RD5 LOS RBC1 C47 TD7 TD8 TD5 TD6 TD9 R44 R43 R40 R51 R39 R41 R42 C49 C50 A2 R46 TDO C52 0 R50 R47 open J J R48 0 R49

19 Figure A 2.Optical Transceiver Configuration Install or redirect steering capacitors for GBIC usage 50-Ω high-speed data lines to SMA 75-Ω GBIC high-speed data lines 50-Ω high-speed data lines to SMA Note: Simultaneous GBIC and SMA operation is not possible. Steering capacitors can either be directed to the GBIC or the SMA connectors but not to both simultaneously. Schematics, Board Layouts, and GBIC Configurations A-3

20 Table A 1.TLK2201EVM Transceiver Bill of Materials 1 1 Digi-Key S ND J7 2X12 Header 0.1x0.1 Centers 2 1 Digi-Key S ND J9 2X14 Header 0.1x0.1 Centers 3 1 Digi-Key S ND P3 2X20 Header 0.1x0.1 Centers 4 1 Digi-Key S ND P5 2X32 Jumper 0.1x0.1 Centers 5 3 Newark 39N867 J5,J6,J8 Banana jack 6 39 Digi-Key PCC1784CT ND C1 C5, C7, C8, C10, C11, C13, C14 C21, C24 C26, C33 C36, C38 C42, C44 C52 Capacitor, SMT V, 10%, µf 7 1 Digi-Key PCC1842CT ND C22 Capacitor, SMT V, 20%, 4.7 µf 8 1 Digi-Key PCC1894CT ND C37 Capacitor, SMT V, 10%, 10 µf 9 4 Digi-Key ND L1 L4 Ferrite bead ma 600 Ω at 100 MHz 10 1 Digi-Key S ND TP2 1x2 Header Header, 1x2, 0.1 center 11 1 AMP P1 GBIC Connector N/A 12 4 Digi-Key P0.0JCT ND R13, R36, R49, R Digi-Key P4.75KLCT ND R3 R8, R39 R44, R51 Resistor, SMT, 0402 Resistor, SMT, Ω 4.7 kω Digi-Key P10.0KLCT ND R16 R25 Resistor, SMT, kω 15 3 Digi-Key P49.9LCT ND R11, R12, R48 Resistor, SMT, 0402, 1% 1/16W 50 V 49.9 Ω 16 6 N/A N/A R1, R2, R10, R37, R14, R Digi-Key PLCT ND R15, R26 R35, R38, R45, R46 Resistor, SMT, % 1/16W 50 V Resistor, SMT, % 1/16W 50 V Open Ω 18 5 Newark J11, J1 J4 SMA end launch 19 4 Newark 92N4922 STANDOFF Standoff thread 20 4 Newark 30F082 Machine screw 4 40 x 3/ TI TLK2201 U1 TI TLK2201 DUT 64 pin VQFP 22 1 Digi-Key P1kLCT ND R9 Resistor, SMT, % 1/16W 50 V 1 kω M 3M UB P2 IDC14M 2x14 header 0.1x0.1 centers 24 1 Digi-Key L62711CT ND D1 SMT LED red Digi-Key PCC101ACVCT ND C6, C9, C12, C23, C27 C32, C43 Capacitor, SMT V, 5%, 100 pf A-4

21 1 2 Figure A 3.Top Layer 1 VCC P6 P14 C6 L1 C9 P2 J4 RXN C5 C7 C8 P5 PIN 1 JTAG P13 TEXAS INSTRUMENTS C3 P5 C4 P1 TP2 R15 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 0 open J7 J9 R38 R45 RXP R8 R7 R6 R5 R4 R3 C21 R46 J C17 C16 C20 C19 C15 C14 C18 PIN 1 J11 J2 TXN J10 C52 TD0 TD1 TD2 TD3 TD4 TD5 TD6 TD7 TD8 TD9 SYNC RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RBC1 RBC0 LOS 1.25Gbps Transceiver Evaluation Board (EVM) TLK2201 Serial Gigabit CMOS 04 OCT 1999 Rev 1.0 RX_LOS MOD_DEF(0) MOD_DEF(1) MOD_DEF(2) TX_DISABLE TX_FAULT RBCMODE ENABLE SYNC_EN LOOP_EN TEST_EN PRBSEN MODESEL R13 0 R14 P3 REFCLK open TP3 C1 C2 TD0 TD1 TD2 TD3 TD4 TD5 TD6 TD7 TD8 TD9 C24 L4 C25 C10 C23 TXP C11 L2 C13 C37 J1 TP1 L3 C12 10uF R9 C22 4.7u 1k D1 Notes: *All Capacitors are.01uf unless otherwise marked *All Resistor are 49.9 ohm unless otherwise marked Schematics, Board Layouts, and GBIC Configurations A-5

22 Figure A 4. Layers 2 and 5 A-6

23 Figure A 5. Power Plane Layer 3 Schematics, Board Layouts, and GBIC Configurations A-7

24 1 2 Figure A 6. GBIC and JTAG Layer 4 VCC P6 P14 C6 L1 C9 P2 J4 RXN C5 C7 C8 P5 PIN 1 JTAG P13 C3 P5 C4 P1 TP2 R15 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 0 open J7 J9 R38 R45 RXP R8 R7 R6 R5 R4 R3 C21 R46 J C17 C16 C20 C19 C15 C14 C18 PIN 1 J11 J2 TXN J10 C52 TD0 TD1 TD2 TD3 TD4 TD5 TD6 TD7 TD8 TD9 SYNC RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RBC1 RBC0 LOS 1.25Gbps Transceiver Evaluation Board (EVM) TLK2201 Serial Gigabit CMOS 04 OCT 1999 Rev 1.0 RX_LOS MOD_DEF(0) MOD_DEF(1) MOD_DEF(2) TX_DISABLE TX_FAULT RBCMODE ENABLE SYNC_EN LOOP_EN TEST_EN PRBSEN MODESEL R13 0 R14 P3 REFCLK open TP3 C1 C2 TD0 TD1 TD2 TD3 TD4 TD5 TD6 TD7 TD8 TD9 C24 L4 C25 C10 C23 TXP C11 L2 C13 C37 J1 TP1 L3 C12 10uF R9 C22 4.7u 1k D1 Notes: *All Capacitors are.01uf unless otherwise marked *All Resistor are 49.9 ohm unless otherwise marked A-8

25 Figure A 7.Bottom Layer 6 C38 C31 C47 C45 C40 R47 R49 [open] R50 [0] [0] C49 C50 C42 C43 R11 C39 R48 C26 C51 R12 R10 [open] C36 C48 C41 C44 C46 C32 C30 open R2 open R1 10k R25 R24 R23 R22 R21 R20 R19 R18 R17 R16 C33 C27 C34 C28 R39 R40 R41 R42 R43 R44 R51 C35 C29 Schematics, Board Layouts, and GBIC Configurations A-9

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Board Layout Adjustments Between the TNETE2201B and TLK2201/TLK1201

Application Report SLLA115 May 2002 Board Layout Adjustments Between the TNETE2201B and TLK2201/TLK1201 Lori Schnier; Falk Alicke, Thomas Neu HPA Wizard Serial Links ABSTRACT This report explains the different