ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS)

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1 ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS) Objective Part A: To become acquainted with Spectre (or HSpice) by simulating an inverter, observing voltage transfer characteristics and measuring its rise and fall times with various capacitive loads. Background Part A: After a circuit is logically designed and verified, we need to make sure the assumed inter-module timing characteristics satisfy their requirements so that our digital circuit will work correctly when fabricated. That is we need to ensure that the analog characteristics of our digital circuit do not interfere with its ideal logical behavior. This is accomplished by modeling the behavior of the transistors in the circuit where such factors as temperature, capacitance, resistance, inductance are taken into account. The transistor level simulator you will be using in ESE 570 is Spectre. For all your Spectre simulations in the exercises described below, please follow the instructions given in the on-line Cadence Manual sections: Schematic Simulation: Creating a Test File for Simulating an Inverter; Spice Simulation: DC Analysis of the The Inverter; Schematic Simulation: Transient Analyses of the Inverter; Parametric Analysis with Spectre. Exercises for Part A: 1. Transient simulation (20/100 pts) Review the on-line Cadence Manual section Schematic Simulation: Transient Analyses of The Inverter. The simulation is to be performed with Wn/Ln = 6u/0.6u a nd Wp/Lp = 15u/0.6u. This can be done by editing the inverter schematic you composed in Lab 1. The manual takes the user through a transient simulation of an inverter for one value of the external component of the load capacitance, namely C ext = 25 ff, and measures only rise time. For this exercise perform a transient simulation of this inverter using a C ext = 0 and 100 ff. Use the simulation to measure both rise and fall times for both capacitance conditions. 2. Inverter DC characteristics (25/100 pts) Perform a DC sweep analysis in Spectre for the inverter constructed in exercise 1 above to find its transfer characteristics for a range Wp/Wn values. For this purpose connect a dc voltage source vdc to the input pin of the inverter test circuit and select DC Analyses for the Analyses option in the Cadence Analog Artist Window. Vary the W of the nmos transistor over the range 1u W 10u and observe the movement of the switching threshold Vth. Use the Cadence Manual section Parametric Analysis with Spectre as a guide to do this simulation and plot the group of curves in the data sweep. For a Wp/Wn ratio of 3/1, find the input voltage when the output voltage is equal to VDD/2 using the measuring tools in the waveform window.

2 2 Objective Part B: To create mask sequences for simple gates and a static D flip-flop, as well as using Spectre to do Post Layout Simulation of the D flip-flop. Background Part B: In VLSI Design powerful automated synthesis tools are used by designers to implement the physical design or layout of their chip, rather than labor intensive transistor by transistor hand-layout. Using such tools increases the designer productivity and shortens the time to market for the chip. However, before the value of such tools can be appreciated, it is instructive to do the layout of few simple circuits by hand. In doing so, one achieves a better understanding of the various timing issues associated with layout floor planning and routing which will provide valuable intuition when designing and implementing more complex chip functions. Design Flow: Layout Once the schematic for a circuit is captured, its behavior verified logically and its analog characteristics have passed all voltage, timing and power specifications the next step in the design flow is layout. This verification is very important no designer wants to waste valuable time laying out circuits that have no chance of working. When laying out a circuit it is helpful to have the the transistor level schematic to help guide your placement and routing of the physical implementation of circuit elements. The layout ought to have a one-to-one correspondence to the schematic. However, the layout will undoubtedly introduce parasitic resistances and capacitances that are not accounted for in the schematic, as has been discussed in class. These parasitics can be measured using tools within Cadence, and they can then be back-annotated in the schematic so that the schematic reflects the actual layout in terms of timing and capacitance properties. Thus after a layout is completed it is necessary to extract from the layout all of the parasitic capacitances using the Layout Versus Schematic (LVS) tool as described in the Layout Versus Schematic (LVS) Verification section of the on-line Cadence Manual. With parasitic capacitances extracted and back-annotated into the schematic (actually the schematic net-list), the designer performs a post-layout Spectre simulation to to validate all of the circuit specifications using a model that best represents the fabricated circuit. There are a few rules of thumb to keep in mind when laying out a circuit, many of which have been mentioned in class: 1. Avoid using polysilicon as a long wire or route. Use it only for local, < 6 mm connections because it has high sheet resistance of 15 to 30 Ohms/square, as well as introducing parasitic capacitance. 2. Use wide metal wires or interconnect for power rails and ground, at minimum W = 4 l. especially if they are long and supplying (sourcing) a lot of current. Keep in mind that typical current density rating for metals is about 0.5 ma/mm.

3 3 3. When changing metal layers, the number of contacts to use should follow from the current rating of the contacts themselves. The current density for each contact should be kept below 0.5 ma/mm. The Virtuoso Layout Editor: The Cadence view or window that contains the layout is called the layout view, as described in the Create Custom Layouts section of the on-line Cadence Manual. Opening the layout view automatically brings up the layout editor called Virtuoso. The long and thin rectangular window that contains all of the layers provided by the technology file is shown in the layer selection window (LSW). Selecting a layer in the LSW will allow one to subsequently draw a layout feature that uses that layer. The background represents the substrate, which in our N-well CMOS process is p material. The mask sequence for an nmos transistor on p bulk is 1) n-diffusion; 2) active; 3) polysilicon, 4) metal1 and 5) contact. The mask sequence for an pmos transistor on p bulk is 1) n-well diffusion, 2) p- diffusion; 3) active; 4) polysilicon, 5) metal1 and 6) contact. For simulation purposes and and standard cell design rules, it is necessary to add the PIN or pn layer, which is used for the for the input/output and vdd!/gnd! pins in the schematic. Power and ground rails should be declared as jumpers. Physical input and output pins should be in metal2 and and power/ground rail pins should be in metal1. It is a good idea to label your pins with the text layer, and make sure to name the labels the same as the pins and put them on top of the labeled wires. Once the the layout is complete run a Design Rule Check (DRC) to verify that no design rules have been violated. The running of the DRC is described in the Design Rule Check section of the on-line Cadence Manual. After the layout has been found to be free of design rule violations, the next set is parasitic extraction. The extraction tool takes the mask sequences and matches them with known sequences for various circuit elements, e.g. whenever the mask sequence 1) n-diffusion; 2) active, 3) polysilicon; 4) metal1; 5) contact is encountered it is recognized as an nmos transistor. Parasitic capacitances are recognized whenever polysilicon or a metal layer runs over field oxide, and a simple estimate of the capacitance is made based on the area of the overlap. Parasitic resistances are not extracted because they are not implemented in our technology file. The extracted view is automatically created whenever a layout is extracted. It contains the circuit element and netlist information for the whole layout. Usually there are no errors in the extracted view unless there are unrecognized mask sequences, which need to be corrected before moving forward. The extracted view is used to compare the layout and schematic for differences that would suggest errors. This verification step is called Layout Versus Schematic (LVS). Note that the LVS is to be done from the extracted view and not the layout view. After the LVS verification is passed, the designer can do the Post-Layout Simulation (PLS) using Spectre from the extracted view. The procedure is identical to that for simulating from the schematic view. See the Post Layout Simulation section of the on-line Cadence Manual.

4 4 Standard Cell Design: Like software libraries that a programmer uses to perform certain well-established or routine functions in a large program, hardware descriptions for VLSI design can be taken from a library of modules or cells that can be called and inserted into a functional description, schematic and layout for a VLSI circuit as often as needed. Such cells are called standard cells because their physical design or layout are done to rigid geometric standards that enable the cells to be automatically placed and routed. One such standard is that standard cells have standard height (vertical distance) and placements for power and ground rails. This enables standard cells to be placed next to each other in rows in order for their power/ground rails to be perfectly aligned. We will design gates as standard cells to take advantage of their reusability. For our standard cells the vertical distance from the top of the vdd! rail to the bottom of the gnd! rail is 100l = 30 mm (see Fig. 1). 100 l = 30 mm Figure 1 Standard Cell

5 5 The topology of a standard cell design is that there are rows of cells alternated with rows of interconnect or routing channels such that in between every pair of standard cell rows there is a routing channel. Interconnecting wires will be routed out of and into cell blocks above and below, and passed through spaces in between. Hence, care must be taken to ensure that these wires do not violate design rules when connecting with adjacent ports. In order to use standard cells in a design it is standard procedure to first characterize each cell to specify its timing information and input/output capacitances. In the exercises in this part you will be asked to layout the Inverter (INV), 2-input NAND gate and 2-input NOR gate. In addition for extra credit, you may elect to layout an asynchronously resettable static D flip flop. To summarize the guidelines for standard cell design are as follows: 1. Standard cells must adhere to rigid dimension specifications; all standard cells are to be the same height and power and ground rails must align. In our case we use 30 mm as our standard height from the top of the vdd! rail to the bottom of the gnd! rail. 2. To effectively use standard cells, they must be fully simulated and characterized. This means capturing the gate switching threshold voltage V th and rise/fall times as a function of load capacitance. 3. It is helpful to design the cell layout so that the input and output pins are not on the same horizontal line, as in the layouts below in Fig. 2, and they are spaced vertically by at least the edge-to-edge minimum width spacing of the metal2 wires. This will enable easy routing of interconnections between different cells while not violating design rules. Figure 2 Layouts of Inverter, 2-input NAND (ND2) gate and 2-input NOR (NR2) gate

6 6 Exercises Part B: 1. Layout of elementary gates (55/100 pts) Create and layout the elementary gates INV, 2-input NAND and 2-input NOR (draw the layouts for your designs done in Cadence Lab 1). Use Wn/Ln = 6u/0.6u and Wp/Lp = 15u/0.6u for all three gates. Follow the online Cadence Tutorial for this purpose. Use the standard cell design guidelines given above. Run DRC and LVS on the layouts. Print out the mask sequences and comparison reports section of the si.log file in your LVS directory. DO NOT print out the entire file. Make sure that you use a different LVS directory for each gate. Review the Post Layout Simulation (PLS) part of the Cadence Tutorial. For the inverter do PLS and determine the V th and the propagation delays rise/fall for the external component of the load capacitances C ext = 0 and 100 ff. For the 2-input NAND and 2-input NOR do the PLS to determine the rise/fall times for all input patterns and present them in table. What are the worst case rise/fall times input patterns? In order to determine rise/fall times you may do either of the following methods: a. Use the cursors on the simulation window to find the appropriate times corresponding to 90% and 10%. or b. Use the special calculator function risetime in the Analog Environment. In order to use the calculator double click an existing output in your Analog Environment (such as OUT). You should then see an outputs manager pop up. In the Outputs Manager (See Fig. 3) Click "New Expression" and name it "risetime" then click open calculator. Select WAVE from the left bank of calculator buttons and click on your OUTPUT wave in the waveform window. Then go to special functions, risetime, and a dialog of options will pop up. Configure the options appropriately for Rise or Fall, and then in the output manager click GET EXPRESSION. The final string that you use should look something like "risetime(vt("net190" "/mnt/castor.../..." ) 0 nil 5 nil nil nil nil 1). For fall time flip the position of 5 and 0."

7 7 Figure 3 Cadence outputs Manager Window 2. D flip flop layout (30/100 pts Extra Credit) Create a mask sequence for the asynchronous resettable, static D flip-flop developed in Cadence Lab 1. Follow the standard cell design guidelines. Perform DRC and LVS on it before simulating the extracted view in Spectre. Perform PLS and make sure it works as desired. That is satisfies the functional behavior verified in your Verilog-XL simulation executed in Lab 1. Using you PLS determine the clock-to-q delay and the reset-to-q delay when clkin frequency = 25 MHz. Print out the mask sequence and simulation result. 3. Static D flip flop setup and hold times (20/100 pts Extra Credit) Describe how you would go about using the PLS to determine the setup and hold times for your static D flip flop. Please note that this cadence Lab Assignment 1 (as well as Cadence Lab Assignment 1) will count 1.5 x the score for each of the seven Text Book Homework Assignments. KRL Updated 24 Mar 15