Embedded System Design

Size: px

Start display at page:

Download "Embedded System Design"

Veronica Flynn
5 years ago
Views:

1 Embedded System Design Lecture 5 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University

2 What We Have Covered So Far Instruction Set Architecture How CPU interacts with I/O controllers Today, we will talk about how CPU interacts with memory in greater details Memory system mechanism (Chapter 3.5 in Wolf s book) Chung EPC6071 2

3 Memory Management Units (MMU) Most OSes require CPU to have MMU If multi-tasking is needed in your embedded system, buy CPU with MMU There are some OSes that do not need MMU Ex) uclinux ( MMUs provide virtualization for memory Entities share a resource, but they are perceived as if each has its own resource Chung EPC6071 3

4 Resource Sharing When more than one process (i.e., program being executed) run Processes fight for resources (CPU, memories, and IO devices) OSes manage processes and resources with authority (i.e., OS is supervisor) Scheduling time management, core allocation Memory management CPU provides hardware to support OS MMU for memory management Chung EPC6071 4

5 Memory Management Processes fight for memory Needs memory protection Memory virtualization Elegant mechanism to share memory Process 1 Virtual address Virtual memory Physical memory Process 2 Virtual address Virtual memory Space for 1 Space for 2 Physical address Space for 3 Process 3 Virtual address Virtual memory Memory mapping /address translation Chung EPC6071 5

6 Memory Management Units Memory management unit (MMU) translates addresses: CPU Logical (virtual) address memory management unit physical address main memory Chung EPC6071 6

7 Address Translation Requires some sort of register/table to allow arbitrary mappings of logical to physical addresses. Two basic schemes: Contiguous Allocation Base and limit registers Non-contiguous Allocation Paging Segmentation Segmentation and paging can be combined (x86). Chung EPC6071 7

8 Base and Limit Registers Memory Process 1 Virtual Mem. 0 Base register Process Process 2 Virtual Mem. 0 Process [Silberschartz et al] Chung EPC6071 8

9 Base and Limit Registers 100 Process [Silberschartz et al] Chung EPC6071 9

10 Activity Process 1 is running and is writing 10 to 0x4 addr. Where is it stored in physical memory? How base register change when process 2 runs? Process 1 s Virtual address space Process 2 s Virtual address space Physical memory 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF PC IR R0 R1 R2 R3 CPU CORE Base register CPU 5 MMU ADDR[0] ADDR[1] ADDR[2] ADDR[3] DATA[7:0] x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF Chung EPC

11 Swapping If we run out of contiguous memory space, [Silberschartz et al] Chung EPC

12 Fragmentation Base-and-limit-register scheme suffers from external fragmentation External Fragmentation total memory space exists to satisfy q request, but it is not contiguous Internal Fragmentation allocated memory may be slightly larger than requested memory Chung EPC

13 Paging Divide memory space into same-size blocks Can handle external & internal fragmentation Use non-contiguous memory allocation for external frag. Make blocks small for internal frag. [Silberschartz et al] Chung EPC

14 Paging Hardware [Silberschartz et al] Chung EPC

15 Activity Use paging and page size is 4 bytes How many frames? How many pages? How many entries in page table? Allocate 8 bytes. How many bits are in offset field? Process 1 s Virtual address space 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF PC IR R0 R1 R2 R3 CPU CORE Page table CPU MMU ADDR[0] ADDR[1] ADDR[2] ADDR[3] DATA[7:0] Physical memory used 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF Chung EPC

16 Caching Address Translations Large translation tables require main memory access. TLB: cache for address translation. Typically small. Chung EPC

17 Paging Hardware w/ TLB [Silberschartz et al] Chung EPC

18 Advantages of Paging Some pages are present in memory and others can be in secondary storage Page level swapping Demand paging Being able to conceptually use more memory than might be physically available Chung EPC

19 Page Fault A trap to the software raised by the hardware when a program accesses a page that is mapped in the virtual address space, but not loaded in physical memory. A page may be swapped out (Swapping) A page may not be loaded at all (Demand paging) When a page fault occurs, Check if the memory reference is a valid reference to a location on secondary memory. If not, the process is terminated (illegal memory access). Otherwise, we have to page in the required page Schedule disk operation to read the desired page into main memory and restart the instruction that was interrupted by the operating system trap Chung EPC

20 Demand Paging When pure demand paging is used, page loading only occurs at the time of the data request, and not before. In particular, when a demand pager is used, a program usually begins execution with none of its pages pre-loaded in RAM. Pages are copied from the executable file into RAM the first time the executing code references them, usually in response to page faults. As a consequence, pages of the executable file containing code not executed during a particular run will never be loaded into memory Chung EPC

21 Page Sharing [Silberschartz et al] Chung EPC

22 ARM Memory Management Memory region types: section: 1 Mbyte block; large page: 64 kbytes; small page: 4 kbytes. Two-level translation scheme. Chung EPC

23 Large Page Table Problem 32bit virtual address space 4K (2^12) page size Each entry in page table is 4bytes (a word) Each process needs 4MB physical memory for its page table alone Chung EPC

24 Two-Level Page-Table Scheme Chung EPC

25 Two-Level Page-Table Scheme Advantages Individual page tables are smaller, and easier to allocate space for Page tables themselves may be paged Efficiently represents scattered virtual memory Chung EPC

26 Segmentation Hardware [Silberschartz et al] Chung EPC

27 Segmentation Hardware [Silberschartz et al] Chung EPC

28 Linux (Virtual) address space int global_data; int global_data2 = 5; int foo() { } int *a; int b[100]; a = malloc(sizeof(int)*100); Chung EPC

Virtual Memory. Daniel Sanchez Computer Science & Artificial Intelligence Lab M.I.T. November 15, MIT Fall 2018 L20-1

Virtual Memory. Daniel Sanchez Computer Science & Artificial Intelligence Lab M.I.T. November 15, MIT Fall 2018 L20-1 Virtual Memory Daniel Sanchez Computer Science & Artificial Intelligence Lab M.I.T. L20-1 Reminder: Operating Systems Goals of OS: Protection and privacy: Processes cannot access each other s data Abstraction: