Embedded System Design

Transcription

1 Embedded System Design Lecture 4 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University

2 CPUs Takes inputs from input devices (sensors, keyboards, ) Process inputs and produce results Send results to output devices (display, actuators, ) Communicate with I/O devices via I/O Device Controllers I/O Device controllers provide abstraction for CPUs Chung EPC6071 2

3 I/O Device Controllers Now and then PXA32x SoC Block Diagram Chung EPC6071 3

4 mechanism I/O Device Controllers Each device controller maintains a set of device registers Command registers (write-only) Status registers (read-only) Data registers (read/write) Typical digital interface to CPU: CPU status reg data reg Chung EPC6071 4

5 I/O Controllers: 8251 UART Universal asynchronous receiver transmitter (UART) : provides serial communication functions are integrated into standard PC interface chip. Allows many communication parameters to be programmed. Chung EPC6071 5

6 Serial Communication Characters are transmitted separately: no char start bit 0 bit 1... bit n-1 stop time Serial Communication Parameters Baud (bit) rate. Number of bits per character. Parity/no parity. Even/odd parity. Length of stop bit (1, 1.5, 2 bits). Chung EPC6071 6

7 8251 CPU interface status (8 bit) CPU 8251 data (8 bit) xmit/ rcv serial port Chung EPC6071 7

8 System Bus Communication system between CPUs and device controllers including memory controllers Connects CPUs and device controllers physically by wires Consists of address lines, control lines, data lines memory System bus address data R/W CPU Chung EPC6071 8

9 Programming I/O Two types of instructions can support I/O: special-purpose I/O instructions (port-mapped IO or isolated I/O); memory-mapped load/store instructions. Let s access registers in I/O devices in the same way as memory Intel x86 provides in, out instructions. Most other CPUs use memory-mapped I/O. I/O instructions do not preclude memory-mapped I/O. Chung EPC6071 9

10 Memory-mapped I/O Memory Map Cortex-M3 Memory Map Chung EPC

11 Memory-mapped I/O Lincoln-60 (Cortex M3 based microcontroller) Memory Map Chung EPC

12 Address Decoding The process of generating chip select (CS) signals from the address bus for each device in the system We set address decoders following a memory map, or the settings of address decoders determine the memory map Designing address decoders is one of important tasks when you design embedded hardware (boards or chips) for your embedded systems Chung EPC

13 Full Address Decoding Chung EPC

14 Partial Address Decoding Chung EPC

15 Generic Bus to I/O Device Interface Device controller Chung EPC

16 An Example controller Chung EPC

17 An Example controller Chung EPC

18 Another Example Chung EPC

19 Implementing Address Decoders Discrete logic High chip-count, lacks flexibility Data decoder Programmable Read Only Memory (PROM) Lookup tables can become very large for more than 8 address lines Programmable Logic Device (PLD) Field Programmable Gate Array (FPGA) X-hyper320TKU [hybus] Chung EPC

20 Activity Finish hardware design and fill out memory map Memory Map CPU D0,,D7 A0 A1 A2 A3 D0,,D7 cs WIFI U0 U1 U2 U3 D0,,D7 cs S0 S1 UART 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF Chung EPC

21 ARM Memory-mapped I/O Define location for device: DEV1 EQU 0x1000 Read/write code: LDR r1,#dev1 ; set up device adrs LDR r0,[r1] ; read DEV1 LDR r0,#8 ; set up value to write STR r0,[r1] ; write value to device Chung EPC

22 Peek and Poke Traditional HLL interfaces: int peek(char *location) { return *location; } void poke(char *location, char newval) { (*location) = newval; } Chung EPC

23 Busy-wait IO (Busy-wait Polling) Simplest way to program device. Use instructions to test when device is ready. current_char = mystring; while (*current_char!= \0 ) { poke(out_char,*current_char); while (peek(out_status)!= 0); current_char++; } Chung EPC

24 Simultaneous Busy/wait I/O while (TRUE) { /* read */ while (peek(in_status) == 0); achar = (char)peek(in_data); /* write */ poke(out_data,achar); poke(out_status,1); while (peek(out_status)!= 0); } Chung EPC

25 Interrupt I/O Busy/wait is very inefficient. CPU can t do other work while testing device. Hard to do simultaneous I/O. Interrupts allow a device to change the flow of control in the CPU. Causes subroutine call to handle device. Chung EPC

26 IR PC mechanism Interrupt Interface CPU intr request intr ack data/address status reg data reg Chung EPC

27 Interrupt Behavior Based on subroutine call mechanism. Interrupt forces next instruction to be a subroutine call to a predetermined location. Return address is saved to resume executing foreground program. Chung EPC

28 Interrupt Physical Interface CPU and device are connected by CPU bus. CPU and device handshake: device asserts interrupt request; CPU asserts interrupt acknowledge when it can handle the interrupt. Chung EPC

29 Example: character I/O handlers void input_handler() { achar = peek(in_data); gotchar = TRUE; poke(in_status,0); } void output_handler() { } Chung EPC

30 Priorities and Vectors Two mechanisms allow us to make interrupts more specific: Priorities determine what interrupt gets CPU first. Vectors determine what code is called for each type of interrupt. Mechanisms are orthogonal: most CPUs provide both. Chung EPC

31 Prioritized Interrupts device 1 device 2 device n interrupt acknowl edge L1 L2.. Ln CPU Chung EPC

32 Interrupt Prioritization Masking: interrupt with priority lower than current priority is not recognized until pending interrupt is complete. Non-maskable interrupt (NMI): highest-priority, never masked. Often used for power-down. Chung EPC

33 Example: Prioritized I/O :interrupts :foreground :A :B :C B C A A,B Chung EPC

34 Interrupt Vectors Allow the interrupting device to specify its handler Interrupt vector table: Interrupt vector table head handler 0 handler 1 handler 2 handler 3 Chung EPC

35 Interrupt Vector Acquisition :CPU :device receive request receive vector receive ack Chung EPC

36 Generic Interrupt Mechanism continue execution ignore N N intr? Y intr priority > current priority? Assume priority selection is handled before this point. Y ack Y bus error Y timeout? N vector? Y call table[vector] Chung EPC

37 Interrupt Sequence CPU acknowledges request. Device sends vector. CPU calls handler. Software processes request. CPU restores state to foreground program. Chung EPC

38 Sources of Interrupt Overhead Handler execution time. Interrupt mechanism overhead. Register save/restore. Pipeline-related penalties. Cache-related penalties. Chung EPC

39 ARM Interrupts ARM7 supports two types of interrupts: Fast interrupt requests (FIQs). Interrupt requests (IRQs). Interrupt table starts at location 0. Chung EPC

40 ARM Interrupt Procedure CPU actions: Save PC. Copy CPSR to SPSR. Force bits in CPSR to record interrupt. Force PC to vector. Handler responsibilities: Restore proper PC. Restore CPSR from SPSR. Clear interrupt disable flags. Chung EPC

41 ARM Interrupt Latency Worst-case latency to respond to interrupt is 27 cycles: Two cycles to synchronize external request. Up to 20 cycles to complete current instruction. Three cycles for data abort. Two cycles to enter interrupt handling state. Chung EPC

42 Software Interrupt Caused either by an exceptional condition in the processor itself, or a special instruction in the instruction set which causes an interrupt when it is executed (ex, SWI in ARM) The former is often called a trap or exception and is used for errors or events occurring during program execution that are exceptional enough that they cannot be handled within the program itself. For example, if the processor's arithmetic logic unit is commanded to divide a number by zero, this impossible demand will cause a divide-by-zero exception Chung EPC

43 I/O in Systems with OS When OS is installed, we cannot perform I/O this way Why? I/O is a resource and need to be shared by processes carefully OS will supervise OS Kernel I/O Device Controller Device Driver. inb(mydev); outb(x, MYDEV);. System calls Process In Linux, for peek(), use inb() for poke(), use outb() Chung EPC

44 System Call A request for service that a program makes of the kernel. The service is generally something that only the kernel has the privilege to do, such as doing I/O. Executed via software interrupts Low level I/O is performed by making system calls. In Linux, all low-level I/O is done by reading and writing file handles System calls in Linux: sys_open: open a file sys_close: close a file sys_read: read from a file sys_write: write to a file sys_lseek: seek and many more Chung EPC

45 System Call Programmers don't call system calls directly Call wrapper functions corresponding to system calls in the GNU C Library #include <unistd.h> #include <sys/syscall.h> #include <errno.h> int rc;... rc = syscall(sys_chmod, "/etc/passwd", 0444); if (rc == -1) fprintf(stderr, "chmod failed, errno = %d\n", errno); #include <sys/types.h> #include <sys/stat.h> #include <errno.h> int rc;... rc = chmod("/etc/passwd", 0444); if (rc == -1) fprintf(stderr, "chmod failed, errno = %d\n", errno); Direct calls Using wrappers Chung EPC

46 System Call Software intrrupt x86 Chung EPC

47 Supervisor Mode SWI instruction put the ARM CPU in supervisor mode OS runs in supervisor mode, and applications run in user mode Supervisor mode has privileges that user modes do not Chung EPC

48 CPUs Cache. a memory that transparently stores data so that future requests for that data can be served faster Cache Hit/miss Locality Multiple levels of caches (L1, L2, L3) Direct-mapped and set-associative Replacement policies (LRU, LFU, ) Scratch pad memory and etc Cache is not covered by this course Memory management unit (next class) Chung EPC

49 Pipelining Several instructions are executed simultaneously at different stages of completion. pipeline bubbles Latency, Throughput Fetch, decode, execute Stalls, etc Pipelining is not covered by this course Chung EPC