PEX 8311 Hardware Design Checklist August 11, 2010; r2.0

Transcription

1 ntroduction PEX 8311 Hardware Design Checklist August 11, 2010; r2.0 This document is intended f systems design engineers incpating the PEX 8311 PC Express-to-Local Bus bridge into a system hardware design. t provides a handy list of basic design checks covering schematic and printed-circuit board (PCB) layout designs. ncluding these checks as part of your design review can help insure that imptant details are not overlooked when your design is committed to hardware, thereby improving your chances f a successful bring-up. n preparation f your design review, we also recommend that you check our website, and download the most current technical specifications, errata, and related documentation. This document supersedes and replaces previously dated versions. 1 Schematic Design Checks This section includes checks on basic elements of the circuit design, including schematic symbol, power supply, clocks, configuration straps, serial EEPRM, JTAG, GP, PC Express, Local Bus and other signals. All power and signal balls on the device are covered. 1.1 Schematic Symbol F designers using RCAD schematic capture tools, an RCAD symbol library is available on the PLX website at This library symbol is pre-checked by PLX engineers, and it is also used in the design of the PEX 8311 RDK. F designers not using the PLX-supplied schematic symbol, we highly recommend double-checking your symbol s signal ball names and numbers f accuracy befe using the symbol in your schematic design. A BSDL file is available in the PEX 8311 web page which has ball names and numbers in text fmat. This can be useful in creating and/ checking your symbol also. 1.2 Power Supply Regulated DC Supply Voltages The PEX 8311 requires the following regulated DC voltages: VDD1.5: 1.5 Volts, +/- 5% - Powers digital ce logic VDD2.5: 2.5 Volts, +/- 10% - Powers digital ce logic VDD3.3: 3.3 Volts, +/- 10% - Powers buffers Power sequencing requirements f the PEX 8311 are described in the PEX 8311 data book. Please review these requirements and make sure they are covered in your design. F most designs, there is no need f special power sequencing hardware, providing all supplies are powered and un-powered within 10 ms of each other. Never power the 3.3V rail without powering the 2.5V supply f any sustained length of time Filtered Analog Supply Voltages From the VDD1.5 supply, the following analog supply voltages are derived: VDD_P: PLL supply voltage, filtered from VDD1.5 PLX Technology, nc., 2010 PLX Technology, nc, 870 W. Maude Avenue, Sunnyvale, CA 94085, Products and Company names are trademarks/registered trademarks of their respective holders.

2 1.2.3 Power, Ground Ball Connections Signal Ball # Signal Type Checked Recommendations PC Express Ce Logic Supply (8 Balls) VDD1.5 C2, C9, C13, D6, L1, L2, M1, W5 Power UNKWN Connect to the +1.5V power supply. Recommended decoupling scheme: 1 Cap 10.0 uf 4 Caps 0.1 uf placed close to PEX Caps 0.001uF placed close to PEX 8311 AVDD G3 Power VDD_R H3 Power VDD_T J4 Power VDD_P J2 Power UNKWN UNKWN UNKWN UNKWN Analog Supply Voltage Connect to VDD1.5. Receiver Supply Voltage Connect to VDD1.5. Transmitter Supply Voltage Connect to VDD1.5. PLL Supply Voltage Filter from VDD1.5 supply. Recommended filter circuit is shown below. Note that the the D.C. resistance of the induct plus the series resist should be ~1.4 ohms total. Local Bus Ce Logic Supply (7 Balls) VDD2.5 C17, H18, J17, T16, U15, V9, Y5 Power UNKWN Connect to the +2.5V power supply. Recommended decoupling scheme: 1 Cap 10.0 uf 4 Caps 0.1 uf placed close to PEX Caps 0.01uF placed close to PEX 8311 Supply Voltage (26 Balls) VDD3.3 D7, D8, D9, E5, E9, E15, E16, E17, F5, F15, F16, F17, G15, G16, H16, J16, K16, N16, P16, R16, T12, T15, U10, U11, U14, V14 Power UNKWN Connect to the +3.3V power supply. Recommended decoupling scheme: 1 Cap 10.0 uf 13 Caps 0.01 uf placed close to PEX Caps 0.1 uf placed close to PEX , PLX Technology, nc. All rights reserved. Page 2 of 23

3 Signal GND Ball # A2, A16, A17, B15, B16, D12, D13, D14, D15, E7, E8, E10, E11, E12, E13, E14, F6, F7, F8, F9, F10, F11, F12, F13, F14, G5, G6, G7, H5, H6, H15, J5, J6, J15, K4, K5, K6, K15, L5, L6, M4, M5, M6, N5, N6, N15, P5, P6, P15, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, T5, T6, T7, T8, T9, T10, T11, T13, T14, U5, U6, U8, U9, U12, U13, V1, V12, V13, W1, W2, W3, W4, Y1, Y2, Y3, Y4 Signal Type Ground AVSS J3 Ground VSS_C F4 Ground VSS_P0 H4 Ground VSS_P1 G4 Ground VSS_R F1 Ground VSS_RE G2 Ground VSS_T K1 Ground Checked UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN Recommendations Ground Connections (86 Balls) Analog Ground Connect to GND Common Ground Connect to GND PLL Ground Connect to GND PLL Ground Connect to GND Receiver Ground Connect to GND Receiver Ground Connect to GND Transmitter Ground Connect to GND 2010, PLX Technology, nc. All rights reserved. Page 3 of 23

4 1.3 Clocks REFCLK REFCLK+/- balls provide the primary clock f the PEX 8311 PC Express interface. REFCLK must be provided at all times during nmal operation. F PC Express adapter cards (PEX 8311 is ENDPNT), REFCLK+/- can be taken directly from the PC Express slot generated locally on-board. When PEX 8311 is configured as RT_CMPLEX, REFCLK+/- must be generated locally on-board REFCLK Clock Source and Line Termination REFCLK Source Signal Type Checked Requirements External REFCLK Clock Transmitter External-CML UNKWN PEX 8311 REFCLK Clock nput Balls Frequency Tolerance: ± 300 ppm, max. 33 Ω series (in-line) and 49 Ω shunt (to GND) required on each differential signal, near the clock source. PCe adapter card designs should connect REFCLK-/+ directly to the PCe edge fingers, as REFCLK is terminated on the system board. Signal Ball # Signal Type REFCLK- REFCLK+ H2 H CLKUT, CLKN, LCLK DFF Signal Ball # Signal Type Checked UNKWN Checked Recommendations 100 MHz PC Express Reference Clock input pair. See Chapter 2 f trace routing recommendations. Recommendations nternal Clock nput CLKN A15 CLKUT A8 LCLK J20 UNKWN UNKWN UNKWN A 66-MHz clock input to the internal PEX 8311 interface. CLKN can be directly driven from CLKUT through an external damping resist (0Ω recommended value) when the RT_CMPLEX# signal is deasserted (Endpoint mode). Avoid connecting the CLKUT ball directly to CLKN; use an external 0 ohms resist to create a test point. An external 66-MHz clock source (oscillat) is required when the RT_CMPLEX# signal is asserted (Root Complex mode). Use internal clock requirement guidelines. When an external source is used, follow the PC r2.2 guidelines. Note also that CLKN is connected to two devices internally, so it counts as two loads. nternal Clock utput A buffered clock output derived from REFCLK. Frequency is programmable, depending on the PECS_DEVNT register CLKUT Frequency field value (1000h[3:0]). Default signal frequency is 66 MHz at 1:2 duty cycle (1/3 High, 2/3 Low). CLKUT has an internal 33 hms series terminat. Local Bus Clock Local Bus clock input. LCLK can be any frequency from 1.0 MHz up to 66.6 MHz. Note: LCLK must be driven at all times during nmal operation. 2010, PLX Technology, nc. All rights reserved. Page 4 of 23

5 1.4 Configuration Straps, Miscellaneous Signals Signal Ball # Signal Type BAR0ENB# E1 3.3 V Checked UNKWN Recommendations PECS_PCBASE0 Register Enable Pull to GRUND to enable enumeration of the PECS_PCBASE0 register, to provide memy-mapped access to PEX 8311 PECS configuration registers and internal RAM. therwise, pull to 3.3V to disable. General-Purpose (4 balls) GP0: Defaults to link status output (drives high when PC Express link is in L0 state). Can be used to drive an LED. This signal is highly useful f debug. f not needed f other functions, it is strongly recommended that this ball at least be connected to a test point to provide scope access. GP[3:0] A1, D3, B1, C1 12 ma 3.3 V UNKWN GP1: Defaults to an input. Pull to VDD3.3 if not used. GP2: Pull to GRUND to set PECS_TLPCFG0[LimitCompletionFlowControlCredit] = 1 (1048h[22] = 1) at reset release. therwise, pull to VDD3.3. See the data book f details on this function. GP3: Recommend pull to GRUND to set PECS_TLPCFG0[DelayLinkTraining] = 1 (1048h[18]=1). This delays the link training f 12 ms following reset release. n practice, this setting has been found to improve compatibility with other PC Express devices. Local Bus Mode (2 Balls) MDE[1:0] straps select the Local Bus operating mode. MDE[1:0] H20, H19 UNKWN MDE1 MDE0 Local Bus Mode L L C Mode H L Reserved L H J Mode H H M Mode (L = Pull to Ground. H = Pull to VDD3.3.) MDE[1:0] straps must be stable at power-on. Power K PWR_K D2 6 ma 3.3V UNKWN Valid only in Endpoint mode. When the available power indicated in the PC Express Set Slot Power Limit message is greater than equal to the power requirement indicated in the PECS_PWER register (101Ch), PWR_K is asserted. RT_CMPLEX# A V UNKWN f not used, this output can be left unconnected. RT_CMPLEX Mode Select Pull to GRUND to configure PEX 8311 as a PC Express root complex. therwise, pull to VDD3.3 to configure PEX 8311 as a PC Express endpoint. 2010, PLX Technology, nc. All rights reserved. Page 5 of 23

6 Signal Ball # Signal Type BD_SEL# B19 PC BTN D10 BUNR F3 Checked UNKWN UNKWN UNKWN Recommendations Board Select Pull to GRUND through 1K ohms f nmal operation. Test Enable Pull tie to GRUND f nmal operation. Test Mode Select Pull tie to GRUND f nmal operation. DDQ Enable DDQEN# V10 PD UNKWN Places the PEX 8311 Local Bus utput buffers into a quiescent state. Asserting DDQEN# to logic Low (0) along with BD_SEL# to logic High (1) fces the PEX 8311 Local Bus s to be tristated and all analog power is disabled. TD C15 PLXT1 A3 PLXT2 A10 SMC V4 TEST N1 TMC E2 TMC1 V3 TMC2 E3 UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN Pull to VDD3.3 through 1K ohms f nmal operation. nternal Test Data (JTAG) Pull to PLX-Defined Test 1 Pull to VDD3.3 through 10K ohms f nmal operation. (Note: if this ball is strapped low, the CLKUT frequency will default to 33 MHz) PLX-Defined Test 2 Pull to GRUND through 1K ohms f nmal operation. Scan Path Mode Control Pull tie to GRUND f nmal operation. Test Mode Select Pull tie to GRUND f nmal operation. Test Mode Control Pull tie to GRUND f nmal operation. DDQ Test Control nput Pull tie to GRUND f nmal operation. Buffer Control Pull tie to GRUND f nmal operation. 1.5 No-Connect Signals Signal N/C Ball # A4, A5, A6, A7, A9, A12, B3, B4, B5, B6, B7, B8, B9, B11, B12, B13, C4, C5, C6, C7, C8, C10, C11, C12, D4, D5, D11, D16, E4, Signal Type Checked UNKWN Recommendations No Connect (59 Balls) Signals designated N/C are true no connects and must not be used to route other functional signals across the board. Must remain floating f standard operation. 2010, PLX Technology, nc. All rights reserved. Page 6 of 23

7 Signal Ball # E6, M2, N2, N3, N4, P1, P2, P3, P4, R1, R2, R3, R4, T1, T2, T3, T4, U1, U2, U3, U4, U7, V2, V5, V6, V7, V8, W6, W7, Y6 Signal Type Checked Recommendations MPRTANT TE: We recommend connecting T4 to PERST# through a schottky diode, BAT54 equivalent, see PEX8311 erratum titled 'External Reset f PCLK clock generat insures reliable PCLK output' 1.6 PC Express Configuration Serial EEPRM nterface The PC Express Configuration Serial EEPRM is used to initialize PECS configuration registers at reset time. This EEPRM is optional f most system designs. t is recommended that designers at least lay in the circuit necessary f the serial EEPRM in case it is needed later f any EEPRM based patches, etc. PEX 8311 suppts SP type serial EEPRMs with 8, 16, 24 bits address fmat. Suppted EEPRMs include Atmel AT25640A, AT25320A, AT25160A, AT25080A equivalents. Also tested were n Semiconduct CAT25010 and CAT25020 serial EEPRMS. PEX 8311 DES T suppt SP serial EEPRMs with 9-bit address fmats. These include Atmel AT25040A and equivalents PC Express Configuration Serial EEPRM (SP) nterface Signals Signal Ball # Signal Type EECLK L4 3 ma 3.3 V EECS# K3 3 ma 3.3 V EERDATA EEWRDATA M3 L3 3.3V 3 ma 3.3 V Checked UNKWN UNKWN UNKWN UNKWN Recommendations Serial EEPRM CLK Connect directly to EEPRM Serial Data Clock (SCK) input pin. Serial EEPRM Chip Select Connect directly to EEPRM Chip Select (CS#) input pin. Serial EEPRM Chip Select Connect directly to EEPRM Serial Data UT (S) output pin. Pull high to 3.3V through 10K ohms. Serial EEPRM Write Data Connect directly to EEPRM Serial Data nput (S) input pin Additional SP EEPRM Signals WP# Pull this signal to 3.3 V through 10K ohms. Can be jumped low to prevent EEPRM write. HLD# Tie this pin to 3.3V. 1.7 Local Configuration Serial EEPRM nterface The Local Configuration Space Serial EEPRM is used to load LCS configuration registers at reset time. F systems that do not have a Local Bus Process capable of writing LCS registers using the CCS# signal, this serial EEPRM is strongly recommended f all designs. F systems using a Local Bus Process to load LCS registers, this serial EEPRM is optional. See Section of the PEX 8311 data book f me details. PEX 8311 suppts a MicroWire type serial EEPRMs with sequential read function. Suppted EEPRMs include Atmel AT93C56/66A equivalents. 2010, PLX Technology, nc. All rights reserved. Page 7 of 23

8 1.7.1 Local Bus Configuration Serial EEPRM (SP) nterface Signals Signal Serial EEPRM Chip Select 12 ma EECS A20 Connect this ball directly to the serial eeprom CS input pin. When BD_SEL# is UNKWN EESK A19 high, ball goes Hi-Z. 12 ma When BD_SEL# is high, ball goes Hi-Z. UNKWN Serial EEPRM Serial Data Clock Connect this ball directly to the serial eeprom CLK input pin. Serial EEPRM Serial Data N/UT EED/D B20 12 ma When LCS_CNRTL[31] =1, ball goes Hi-Z UNKWN Multiplexed EEPRM serial write data output serial read data input. Connect this ball to serial EEPRM Serial Data ut (D) AND Serial Data N (D). F most designs, this pin should also be pulled to There are some cases where this pin can be pulled low also. RT_CMPLEX mode designs with no serial EEPRM should pull this signal low. See the data book f details Additional MicroWire EEPRM Signals RG Pull this signal to 3.3 V through 10K ohms. 1.8 JTAG nterface Considerations f JTAG signals are given below. Please note Erratum #4 which affects JTAG operation. See the PEX 8311 Errata document f details. f JTAG boundary scan is implemented, PEX 8311 should be placed at the front of the chain, such that TD connects to the JTAG controller, and TD connects to the next device in the scan chain. Signal Test Clock TCK A13 UNKWN Pull to GRUND through 1K ohms. Do not leave floating. Test Data nput TD A14 UNKWN f JTAG is not implemented, ok to leave this ball unconnected. TD TMS TRST# C14 A11 B14 12 ma 3.3 V UNKWN UNKWN UNKWN Test Data utput f JTAG is not implemented, ok to leave this ball unconnected. Test Mode Select f JTAG is not implemented, ok to leave this ball unconnected. Test Reset Pull to GRUND through 1K ohms f nmal operation. Drive high to enable JTAG functions. 2010, PLX Technology, nc. All rights reserved. Page 8 of 23

9 1.9 PC Express nterface Signals Signal Ball # Signal Type PERn0 PERp0 PETn0 PETp0 F2 G1 K2 J1 DFF DFF DFF DFF Checked UNKWN UNKWN UNKWN UNKWN Recommendations Receive Minus PC Express Differential Receive signal. See Chapter 2 f trace routing recommendations. Receive Plus PC Express Differential Receive signal. See Chapter 2 f trace routing recommendations. Transmit Minus PC Express Differential Transmit signal. Series 100nF AC coupling capacit required on each transmit line. See Chapter 2 f trace routing recommendations. Transmit Plus PC Express Differential Transmit signal. Series 100nF AC coupling capacit required on each transmit line. See Chapter 2 f trace routing recommendations. PC Express Reset PERST# C3 6 ma 3.3 V UNKWN n Endpoint mode, PERST# is an input. PERST# resets the entire bridge when asserted. F PC Express add-in cards, this ball can be connected directly to the PC Express slot PERST# signal. n Root Complex mode, PERST# is an output. t is asserted when a PC reset is detected. n this mode PERST# can be used to reset a downstream PC Express device. Wake n WAKEN# B2 3.3 V UNKWN n Root Complex mode, WAKEN# is an input, and indicates that the PC Express device requested a wakeup while the Link is in the L2 state. Pull this signal to VDD3.3 through 1-10K ohms. Wake ut WAKEUT# D1 D 6 ma 3.3 V UNKWN n Endpoint mode, WAKEUT# is an output, and asserted when the Link is in the L2 state. PC Express add-in card designs can connect this signal directly to the PC Express slot WAKE# signal. f not used, this pin can be left as no-connect. 2010, PLX Technology, nc. All rights reserved. Page 9 of 23

10 1.10 C-Mode Local Bus Signals This section applies only f designs implementing a C-Mode Local Bus (MDE[1:0] = LL). Signal ADS# BGEND# BLAST# F19 D18 F20 BREQi G18 BREQo BTERM# G17 J19 D D CCS# D17 DACK[1:0]# B18, C20 When [(RT_CMPLEX# is not asserted and PERST# is asserted) (RT_CMPLEX# and balls go Hi-Z. UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN Address Strobe Big Endian Select Drive low to enable endian-swap on Direct Master transactions (Local-to-PC Express). An external pullup is recommended on this signal. Burst Last Bus Request n External pull-down (10K ohms to GRUND) recommended on this signal. t can optionally be driven low when not being asserted. Do not leave floating. Bus Request ut f this signal is used, it should be pulled to GRUND through 10K ohms. f not used, ok to leave unconnected. Burst Terminate Configuration Register Select External pull-up recommended. Pull to VDD3.3 through 10K ohms. Do not leave floating. DMA Channel 1:0 Demand Mode Acknowledge (2 balls) External pull-ups recommended on these balls. Pull each to f not used, these balls can be left unconnected. 2010, PLX Technology, nc. All rights reserved. Page 10 of 23

11 Signal DMPAF / ET# DP[3:0] DREQ[1:0]# LA[31:2] LBE[3:0] C18 M15, M16, L15, L16 B17, C19 Y7, W8, Y8, W9, Y9, W10, Y10, V11, W11, Y11, W12, Y12, W13, Y13, W14, Y14, V15, W15, Y15, U16, V16, W16, Y16, U17, V17, W17, Y17, V18, W18, Y18 Y19, Y20, W20, W19 When LCS_DMAMDE0/1[14]=1 therwise When [(RT_CMPLEX# is not asserted and PERST# is asserted) (RT_CMPLEX# and ball goes Hi-Z. (LA[31:30, 28:2] only) UNKWN UNKWN UNKWN UNKWN UNKWN Multiplexed signal: Direct Master Programmable Almost Full (output) r ET# (nput) See the data book f details on this signal. External pull-up recommended. Pull to VDD3.3 through 10K ohms. Local Data Parity (4 balls) DP[3:0] balls have weak internal pull-ups. f these signals are connected to board circuits, an external pull up (10K ohms to VDD3.3) is recommended on each line. DMA Channel 1:0 Demand Mode Request (2 balls) External pull up recommended on each ball. Pull to VDD3.3 though 10K ohms. Local Address Bus (30 balls) Local address bus signals should be pulled high externally (pull each LAn line to VDD3.3 through 10K ohms). Local Byte Enables (4 balls) External pull-ups required. Pull each LBEn line to 2010, PLX Technology, nc. All rights reserved. Page 11 of 23

12 Signal LD[31:0] LHLD V19, V20, U19, U20, T17, T18, T19, T20, R17, R18, R19, R20, P17, P18, P19, P20, N17, N18, N19, N20, M17, M18, M19, M20, L17, L18, L19, L20, K17, K18, K19, K20 G20 When [(RT_CMPLEX# is not asserted and PERST# is asserted) (RT_CMPLEX# and ball goes Hi-Z. LHLDA G19 LNTi# LNTo# LRESET# LSERR# E20 E19 E18 J18 D When RT_CMPLEX# is asserted otherwise D UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN Local Data Bus (32 balls) F Local bus widths of 8 16 bits, unused balls can be left unconnected. Local Hold Request f connecting LHLD to an external local bus arbiter, pull this signal to GRUND through 10K ohms. f PEX 8311 is the only local bus master in the system, connect this signal directly to LHLDA. Local Hold Acknowledge This signal should be pulled to GRUND through 10K ohms. Can optionally be driven low by external logic. Do not leave floating at any time. Local nterrupt nput This signal should be pulled to VDD3.3 through 10K ohms. Local nterrupt utput This is an open-drain output. f used, pull to VDD3.3 through 1K-10K ohms. f not used, this ball can be left unconnected. Local Bus Reset n RT_CMPLEX mode, connect to main system reset signal (pull high if not always driven). n ENDPNT mode, this signal is used to propagate reset to Local Bus devices (external 10K pull-up recommended) Local System Err nterrupt utput This is an open-drain output. f used, pull to VDD3.3 through 1K-10K ohms. f not used, this ball can be left unconnected. 2010, PLX Technology, nc. All rights reserved. Page 12 of 23

13 Signal LW/R# PMEN# PMEUT# READY# USERi / LLCKi# USERo / LLCKo# WAT# U18 C16 B10 F18 D20 D19 H17 (10K) D D When [(RT_CMPLEX# is not asserted and PERST# is asserted) (RT_CMPLEX# and ball goes Hi-Z. UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN Local Write/Read Power Management Event nput (ENDPNT mode only) This ball has an internal 10K ohm pull up. f not used, ok to leave unconnected. Power Management Event utput (RT_CMPLEX mode only) f used, this signal requires an external pull-up (pull to VDD3.3 through 1K-10K ohms). f not used, ok to leave unconnected. READY Multiplexed input ball. Default functionality is USERi (LCS_CNTRL[18]=1). See Section of the PEX 8311 data book f USERi considerations at reset-time. F most designs, this ball should be pulled to VDD3.3 through 10K ohms. Multiplexed utput ball. Default functionality is USERo (LCS_CNTRL[19]=1). This output can go hi-z during reset. Pull to VDD3.3 if necessary. f not used, this ball can be left unconnected. WAT 2010, PLX Technology, nc. All rights reserved. Page 13 of 23

14 1.11 J-Mode Local Bus Signals This section applies only f designs implementing a J-Mode Local Bus (MDE[1:0] = LH). Signal ADS# ALE BGEND# BLAST# F19 Y8 D18 F20 BREQi G18 BREQo BTERM# G17 J19 D D CCS# D17 DACK[1:0]# DEN# B18, C20 W8 When [(RT_CMPLEX# is not asserted and PERST# is asserted) (RT_CMPLEX# and balls go Hi-Z. UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN Address Strobe Address Latch Enable This signal requires an external pull-down. Pull to GRUND through 4.7K-10K ohms. Big Endian Select Drive low to enable endian-swap on Direct Master transactions (Local-to-PC Express). An external pullup is recommended on this signal. Burst Last Bus Request n External pull-down (10K ohms to GRUND) recommended on this signal. t can optionally be driven low when not being asserted. Do not leave floating. Bus Request ut f this signal is used, it should be pulled to GRUND through 10K ohms. f not used, ok to leave unconnected. Burst Terminate Configuration Register Select External pull-up recommended. Pull to VDD3.3 through 10K ohms. Do not leave floating. DMA Channel 1:0 Demand Mode Acknowledge (2 balls) External pull-ups recommended on these balls. Pull each to f not used, these balls can be left unconnected. Data Enable f used, pull to VDD3.3 through 10K ohms, else ok to leave unconnected. 2010, PLX Technology, nc. All rights reserved. Page 14 of 23

15 Signal DMPAF / ET# DP[3:0] DREQ[1:0]# DT/R# LA[28:2] C18 M15, M16, L15, L16 B17, C19 Y7 W9, Y9, W10, Y10, V11, W11, Y11, W12, Y12, W13, Y13, W14, Y14, V15, W15, Y15, U16, V16, W16, Y16, U17, V17, W17, Y17, V18, W18, Y18 When LCS_DMAMDE0/1[14]=1 therwise When [(RT_CMPLEX# is not asserted and PERST# is asserted) (RT_CMPLEX# and ball goes Hi-Z. UNKWN UNKWN UNKWN UNKWN UNKWN Multiplexed signal: Direct Master Programmable Almost Full (output) r ET# (nput) See the data book f details on this signal. External pull-up recommended. Pull to VDD3.3 through 10K ohms. Local Data Parity (4 balls) DP[3:0] balls have weak internal pull-ups. f these signals are connected to board circuits, an external pull up (10K ohms to VDD3.3) is recommended on each line. DMA Channel 1:0 Demand Mode Request (2 balls) External pull up recommended on each ball. Pull to VDD3.3 though 10K ohms. Data Transmit/Receive f used, pull to VDD3.3 through 10K ohms, else ok to leave unconnected. Local Address Bus (27 Balls) Provides the current DWd address (except LA[31:29]) during any phase of an access. (same as C- mode.) These signals are optional f J-Mode designs, as the local address is typically conveyed on LAD[31:0]. f these signals are used by external logic, pull each line to 3.3V through 10K ohms. 2010, PLX Technology, nc. All rights reserved. Page 15 of 23

16 Signal LAD[31:0] LBE[3:0] LHLD V19, V20, U19, U20, T17, T18, T19, T20, R17, R18, R19, R20, P17, P18, P19, P20, N17, N18, N19, N20, M17, M18, M19, M20, L17, L18, L19, L20, K17, K18, K19, K20 Y19, Y20, W20, W19 G20 When [(RT_CMPLEX# is not asserted and PERST# is asserted) (RT_CMPLEX# and ball goes Hi-Z. LHLDA G19 LNTi# LNTo# LRESET# E20 E19 E18 D When RT_CMPLEX# is asserted otherwise UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN Local Address/Data Bus (32 Balls) Pull each line to Local Byte Enables (4 balls) External pull-ups required. Pull each LBEn line to Local Hold Request f connecting LHLD to an external local bus arbiter, pull this signal to GRUND through 10K ohms. f PEX 8311 is the only local bus master in the system, connect this signal directly to LHLDA. Local Hold Acknowledge This signal should be pulled to GRUND through 10K ohms. Can optionally be driven low by external logic. Do not leave floating at any time. Local nterrupt nput This signal should be pulled to VDD3.3 through 10K ohms. Local nterrupt utput This is an open-drain output. f used, pull to VDD3.3 through 1K-10K ohms. f not used, this ball can be left unconnected. Local Bus Reset n RT_CMPLEX mode, connect to main system reset signal (pull high if not always driven). n ENDPNT mode, this signal is used to propagate reset to Local Bus devices (external 10K pull-up recommended) 2010, PLX Technology, nc. All rights reserved. Page 16 of 23

17 Signal LSERR# LW/R# PMEN# PMEUT# READY# USERi / LLCKi# USERo / LLCKo# WAT# J18 U18 C16 B10 F18 D20 D19 H17 D (10K) D D When [(RT_CMPLEX# is not asserted and PERST# is asserted) (RT_CMPLEX# and ball goes Hi-Z. UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN Local System Err nterrupt utput This is an open-drain output. f used, pull to VDD3.3 through 1K-10K ohms. f not used, this ball can be left unconnected. Local Write/Read Power Management Event nput (ENDPNT mode only) This ball has an internal 10K ohm pull up. f not used, ok to leave unconnected. Power Management Event utput (RT_CMPLEX mode only) f used, this signal requires an external pull-up (pull to VDD3.3 through 1K-10K ohms). f not used, ok to leave unconnected. READY Multiplexed input ball. Default functionality is USERi (LCS_CNTRL[18]=1). See Section of the PEX 8311 data book f USERi considerations at reset-time. F most designs, this ball should be pulled to VDD3.3 through 10K ohms. Multiplexed utput ball. Default functionality is USERo (LCS_CNTRL[19]=1). This output can go hi-z during reset. Pull to VDD3.3 if necessary. f not used, this ball can be left unconnected. WAT 2010, PLX Technology, nc. All rights reserved. Page 17 of 23

18 1.12 M-Mode Local Bus Signals This section applies only f designs implementing a M-Mode Local Bus (MDE[1:0] = HH). Signal BB# BDP# G18 H17 D UNKWN UNKWN Bus Busy External pull-up resist recommended on this signal. Pull to VDD3.3 through 4.7K ohms less to insure fast transition times. Burst Data n-progress External pull-up required. Pull to VDD3.3 through 4.7K-10K ohms. Bus Grant BG# G19 B# BGEND# / WAT# BR# BURST# J19 D18 G20 F20 When (LCS_MARBR[31]=0) else When [(RT_CMPLEX# is not asserted and PERST# is asserted) (RT_CMPLEX# and ball goes Hi-Z. CCS# D17 UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN f an external local bus arbiter is used (multiple local masters), insure that this ball is always driven, else pull high externally to VDD3.3 through 4.7K-10K ohms. f the PEX 8311 is the only local bus master (no external arbiter), this ball can be pulled to GRUND to always grant the local bus to PEX Burst nhibit External pull-up required. Pull to VDD3.3 through 4.7K-10K ohms. Multiplexed ball. Default functionality is BGEND#, Big Endian input (LCS_MARBR[31])=0). External pull-up required. Pull to VDD3.3 through 4.7K-10K ohms. Bus Request This ball is always driven during nmal operation. f PEX 8311 is the only local bus master (BG# tied low), then it is ok to leave this ball unconnected. Burst External pull-up required. Pull to VDD3.3 through 4.7K-10K ohms. Configuration Register Select External pull-up recommended. Pull to VDD3.3 through 10K ohms. Do not leave floating. 2010, PLX Technology, nc. All rights reserved. Page 18 of 23

19 Signal DACK[1:0]# B18, C20 DP[0:3]# M15, M16, L15, L16 DREQ[1:0]# LA[0:31] LD[0:31] LNTi# B17, C19 Y7, W8, Y8, W9, Y9, W10, Y10, V11, W11, Y11, W12, Y12, W13, Y13, W14, Y14, V15, W15, Y15, U16, V16, W16, Y16, U17, V17, W17, Y17, V18, W18, Y18, W20, W19 V19, V20, U19, U20, T17, T18, T19, T20, R17, R18, R19, R20, P17, P18, P19, P20, N17, N18, N19, N20, M17, M18, M19, M20, L17, L18, L19, L20, K17, K18, K19, K20 E20 When [(RT_CMPLEX# is not asserted and PERST# is asserted) (RT_CMPLEX# and balls go Hi-Z. (LA[0:1, 3:31] only) UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN DMA Channel 1:0 Demand Mode Acknowledge (2 balls) External pull-ups recommended on these balls. Pull each to f not used, these balls can be left unconnected. Local Data Parity (4 balls) DP[0:3] balls have weak internal pull-ups. f these signals are connected to board circuits, an external pull up (10K ohms to VDD3.3) is recommended on each line. DMA Channel 1:0 Demand Mode Request (2 balls) External pull up recommended on each ball. Pull to VDD3.3 though 10K ohms. Local Address Bus (32 balls) External pull-ups recommended on each line. Pull to Local Data Bus (32 balls) External pull-ups recommended on each line. Pull to Local nterrupt nput This signal should be pulled to VDD3.3 through 10K ohms. 2010, PLX Technology, nc. All rights reserved. Page 19 of 23

20 Signal LNTo# LRESET# MDREQ# DMPAF ET# PMEN# PMEUT# RD/WR# RETRY# E19 E18 C18 C16 B10 U18 G17 D When RT_CMPLEX# is asserted otherwise When (LCS_DMAMDE0/1[14]=1) else When [(RT_CMPLEX# is not asserted and PERST# is asserted) (RT_CMPLEX# and ball goes Hi-Z. (10K) D D UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN Local nterrupt utput This is an open-drain output. f used, pull to VDD3.3 through 1K-10K ohms. f not used, this ball can be left unconnected. Local Bus Reset n RT_CMPLEX mode, connect to main system reset signal (pull high if not always driven). n ENDPNT mode, this signal is used to propagate reset to Local Bus devices (external 10K pull-up recommended) Multiplexed ball. Default functionality is MDREQ#/DMPAF output (LCS_DMAMDE0/1[14]=0). DMA Data Transfer Request (output) DMPAF (output) End-of-Transfer f Current DMA Channel (input) F most designs, this ball should be pulled to VDD3.3 through 10K ohms. Power Management Event nput (ENDPNT mode only) This ball has an internal 10K ohm pull up. f not used, ok to leave unconnected. Power Management Event utput (RT_CMPLEX mode only) f used, this signal requires an external pull-up (pull to VDD3.3 through 1K-10K ohms). f not used, ok to leave unconnected. Read/Write Retry f used, an external pull-up (10K ohms to VDD3.3) is recommended. f PEX 8311 is the only local master, ok to leave unconnected. 2010, PLX Technology, nc. All rights reserved. Page 20 of 23

21 Signal TA# TEA# # Z[0:1] USERi / LLCKi# USERo / LLCKo# F18 J18 F19 Y19, Y20 D20 D19 D D When [(RT_CMPLEX# is not asserted and PERST# is asserted) (RT_CMPLEX# and ball goes Hi-Z. UNKWN UNKWN UNKWN UNKWN UNKWN UNKWN Transfer Acknowledge Transfer Err Acknowledge Transfer Start (Address Strobe) Transfer Size These signals require external pull-ups. Pull each line to Multiplexed input ball. Default functionality is USERi (LCS_CNTRL[18]=1). See Section of the PEX 8311 data book f USERi considerations at reset-time. F most designs, this ball should be pulled to VDD3.3 through 10K ohms. Multiplexed input ball. Default functionality is USERi (LCS_CNTRL[18]=1). This output can go hi-z during reset. Pull to VDD3.3 if necessary. f not used, this ball can be left unconnected Additional Schematic Design Considerations PERST# The PEX 8311 requires the PERST# signal to be asserted f at least 100ms after the board s power is stable to allow the chip to initialize crectly. nsure that Power n Reset and Power Valid detection circuitry implemented in your design meets this requirement. Refer to the PEX 8311 RDK Hardware Reference Manual f an example schematic Mid-Bus Probe Points f your design contains embedded PC Express links, it can sometimes be useful to add probe pads to your PCB design to allow instrumentation access to PC Express links on the board. f you are planning to include mid-bus probe footprints in your PCB design, be aware that they may induce jitter and/ reduce signal integrity on the PC Express lanes it is connected to. Refer to your instrumentation vend s specifications f specific layout design considerations. 2010, PLX Technology, nc. All rights reserved. Page 21 of 23

22 2 PCB Layout Design Checks Note: The following guidelines were provided f PC Express 2.5 GT/s (Gen 1) transmission lines. Since PC Express links operate at very high speeds, proper PCB routing of each RX and TX pair in each lane is critical f maintaining signal integrity on each PC Express link. The PC-SG provides numerous suggestions about how to crectly design PCB s containing PC Express links. Several imptant guidelines f proper layout of PC Express SerDes signals are listed below. Additional infmation is available from the PC-SG website, 1. Recommended Microstrip Trace mpedance: Differential mpedance 6 layers: 100 ohms +/- 20% 8-10 layers: 85 ohms +/- 20% Single-ended mpedance 6 layers: 60 ohms +/- 15% 8-10 layers: 55 ohms +/- 15% 2. Recommended Stripline Trace mpedance: Differential mpedance 6 layers: 100 ohms +/- 15% 8-10 layers: 85 ohms +/- 15% Single-Ended mpedance 6 layers: 60 ohms +/- 15% 8-10 layers: 55 ohms +/- 15% 3. Maintain 20 mil trace edge to plane edge gap 4. Match signal trace lengths to within 5 mils. Equalize using a snaked trace near the receive end if needed, but avoid "tight bends" 5. Route signals over continuous, un-broken planes. 6. Use GND-GND stitching vias near signal vias when routing between PCB layers 7. Do not route over plane splits voids. Allow no me than 1/2 trace width routed over via antipad 8. Match left/right turn bends where possible. No 90-degree bends "tight" bend structures. 9. The reference clock signal pair should maintain the same reference plane f the entire routed length and should not cross any plane splits (breaks in the reference plane) 10. Reference clock terminating components should be placed as close as possible to their respective driving sources, ideally within 100 mils of the clock/receiver component pin/ball. 11. Match all segment lengths between differential pairs along the entire length of the pair. 12. Maintain constant line impedance along the routing path by keeping the same line width and line separation. 13. Avoid routing differential pairs adjacent to noisy signal lines high speed switching devices such as clock chips. 14. Recommended reference clock differential pair spacing (clock to clock#) mils. 15. Recommended reference clock trace spacing to other traces is 20 mils. 16. Recommended reference clock line width 5 mils. 17. When routing the 100MHz differential clock, do not divide the two halves of the clock pair between layers. 18. Recommended reference clock differential impedance: 85 Ω ± 15% 19. Recommended PC Express reference clock to PC express reference clock length matching to within 25 mils 2010, PLX Technology, nc. All rights reserved. Page 22 of 23

23 20. AC Coupling Capacits: The same package size and value of capacit should be used f each signal in a differential pair. Refer to the PC Express Base Specification f permitted values. 21. AC Coupling Capacits: Locate capacits f coupled traces in a differential pair at the same location along the differential traces. Place them as close to each other as possible. 22. AC Coupling Capacits: The "breakout" into and out of the capacit mounting pads should be symmetrical f both signal lines in a differential pair. n addition, the area under the cap footprint should be voided of metal. 23. Test points and probing structures should not introduce stubs on the differential pairs. 24. Use Low ESR, ceramic caps f lane AC-coupling. 2010, PLX Technology, nc. All rights reserved. Page 23 of 23