Board Design Guidelines for PCI Express Architecture

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Board Design Guidelines for PCI Express Architecture Cliff Lee Staff Engineer Intel Corporation Member, PCI Express Electrical and Card WGs The facts, techniques and applications presented by the

1 Board Design Guidelines for PCI Express Architecture Cliff Lee Staff Engineer Intel Corporation Member, PCI Express Electrical and Card WGs The facts, techniques and applications presented by the following person and company are solely those of the presenter and not in any way endorsed, certified, or necessarily the opinion of PCI-SIG or its members. Copyright 2003, PCI-SIG, All Rights Reserved 1

3 Bus Topologies PCI common clock Meet setup/hold timing Multi-drop parallel I/O AGP source synchronous Match all data to strobe Single strobe, multiple data CONN PCI Express serial differential CONN 133MT/s CONN Point-to-point, match per data pair only Longer route, creative device placement CLK MCH 533MT/s CONN MCH 2.5+GT/s MCH Point-to-point routing is is straightforward Copyright 2003, PCI-SIG, All Rights Reserved 3

4 Serial differential 800 mv RX TX Transmitter & package TX Spec Eye Baseboard AC caps D+ D- PCI Express Connector Interconnect Loss < 13.2 db Jitter < 0.3 UI Add-in card TX RX Receiver & package RX Spec 175 mv AC coupled Lane-to-lane de-skew Polarity inversion On-chip equalization On-chip terminations 0.7 UI UI = Unit Interval 400ps 0.4 UI Copyright 2003, PCI-SIG, All Rights Reserved 4

AGP8X Layout Challenges Data and Strobe must be length matched Serpentine routing is needed for length matching Short Motherboard Trace Lengths

5 AGP8X Layout Challenges Data and Strobe must be length matched Serpentine routing is needed for length matching Short Motherboard Trace Lengths 2 6 max MCH to connector Tight Timing Budget Data-to-strobe timing skew AGP Connector Strobe Data Copyright 2003, PCI-SIG, All Rights Reserved 5

PCI Express makes layout easy Trace length matching between pairs is not required Embedded clock simplifies routing rules GND reference preferred Avoid splits and voids Use GND

6 PCI Express makes layout easy Trace length matching between pairs is not required Embedded clock simplifies routing rules GND reference preferred Avoid splits and voids Use GND stitching vias when changing layers Longer motherboard trace 12 + possible AC Coupling Caps x16 PCI Express Connector No trace serpentines Copyright 2003, PCI-SIG, All Rights Reserved 6

7 Interconnect budget Interconnect Baseboard (connector and/or riser card) Add-in card Near-end crosstalk Impedance mismatch Total Loss 6.6 db 1.4 db 2.7 db 2.5 db 13.2 db Jitter 0.19 UI UI UI 0.3 UI Loss and Jitter are key parameters Impedance is not as critical Maintain differential pair symmetry Design tradeoffs for PCB: component loss vs. trace length Manage loss and symmetry to meet budget Copyright 2003, PCI-SIG, All Rights Reserved 7

9 Stackup design No new PCB technology required Standard 4-layer stackup thick PCB Microstrip ½ oz Cu plated Ok Stripline 1 oz Cu (6+ layers) Better Soldermask L1 Signal Pre-preg L2 VCC Core L3 VSS Pre-preg L4 Signal Soldermask Nominal 4-layer PCB Stackup Trace Spacing Trace Width ε r = 4.1, +/- 0.3 ε r = 4.1, +/ mils 1.9 mils 4.4 mils 1.4 mils 47 mils 1.4 mils 4.4 mils 1.9 mils 1.2 mils Follow simple layout rules & design tradeoffs 62.4 mils Copyright 2003, PCI-SIG, All Rights Reserved 9

10 Trace Geometry & Impedance Use wider trace width Minimize loss Use wider traces for long routes More pair-to-pair spacing Minimize crosstalk Target differential Z o of 100 Ω ±20% Tx h 20 mil Tx Non-interleaved Topology example Microstrip Tx h Rx 20 mil Interleaved Topology example Stripline Copyright 2003, PCI-SIG, All Rights Reserved 10

PCB material dominates loss Stackup FR4 material Copper roughness loss Thinner dielectrics loss Non-homogeneous dielectric Resin Material Glass Material Localized Zo

11 PCB material dominates loss Stackup FR4 material Copper roughness loss Thinner dielectrics loss Non-homogeneous dielectric Resin Material Glass Material Localized Zo variation due to material weave loss Wide differential Impedance variation on µstrip Etching and Plating process loss FR4 cross-section Copyright 2003, PCI-SIG, All Rights Reserved 11

12 Trace length Longer trace length loss 0.25 to 0.35 db inherent loss per inch for FR4 microstrip traces Limit motherboard trace to < 12 inches and add-in card trace to < 3 inches 1.25GHz freq -5.23dB 20-inch line db VNA measurements for trace insertion loss Copyright 2003, PCI-SIG, All Rights Reserved 12

13 Trace Symmetry & Matching Match each differential pair per segment Match overall length 5 mils Symmetric routing for each pair Preferred matching Match near mismatch 45 mils Alternative matching Copyright 2003, PCI-SIG, All Rights Reserved 13

14 Pin field breakout Use side-by-side breakout for package to maintain symmetry Avoid tight bends Side-by-side Best Adjacent w/ small serpentine Ok Adjacent w/ bend Fair Diagonal routing Fair Copyright 2003, PCI-SIG, All Rights Reserved 14

15 Reference plane Full ground plane reference Stitching vias required for layer transition Clearance near plane void Avoid trace over anti-pad Plane Void Long trace routes Gnd stitching via Copyright 2003, PCI-SIG, All Rights Reserved 15

16 Bend Guidelines Avoid tight bends No 90 bends; impact to loss and jitter budgets Keep angles >= 135 (α) Keep minimum air gap A >= 3x the trace width Length of B and C >= 1.5x the width of the trace C B α A Copyright 2003, PCI-SIG, All Rights Reserved 16

17 AC coupling caps Size: 0402 best, 0603 ok No 0805 size or C-packs Symmetric placement Cap Size: 0.1uF best Cap location: Along Tx pairs on Motherboard Along Tx pairs on Add-in card Copyright 2003, PCI-SIG, All Rights Reserved 17

18 Connectors New connector with standard PTH Pinout optimized for differential routing Loss & crosstalk part of baseboard budget Connector sizes: x1, x4, x8, x16 Side B: Tx D- D+ Gnd Gnd Side A: Rx D+ D- Copyright 2003, PCI-SIG, All Rights Reserved 18

19 Card edge fingers Remove ref plane under edge fingers pads For better impedance/loss performance Outer Layer Differential Pair Signal Traces Layer 2 Reference Plane Layer 3 Reference Plane Outer Layer Edge Fingers Copyright 2003, PCI-SIG, All Rights Reserved 19

20 Test points & Vias Minimize Vias usage Up to 0.25 db loss per via Via pad size 25 mil, hole size 14 mil Put test points or LAI pads in series No stubs Provide Gnd pads for single-ended probing LAI pads Probe pads Gnd pads Copyright 2003, PCI-SIG, All Rights Reserved 20

22 Simulations Simulations to maximize board solution space Simulation analysis using HSPICE, etc Dielectric and conductor loss must be modeled Simulate spec parameters Compliance Eye (Loss/Jitter) AC & DC common mode Return Loss (for buffer/package) Models Buffer, package, PCB (trace, via), connector Worst case ref channel Perform simulations to maximize solution space Copyright 2003, PCI-SIG, All Rights Reserved 22

23 Topology & modeling Multi-pair (2 aggressors, 1 victim) coupled models Tx Pkg AC cap Connector Pkg Rx aggressor victim aggressor Baseboard Add-in card Corner case PCB: impedance variations and non-homogenous effects 8b/10b compliance data pattern in Spec Aggressor Victim Aggressor Copyright 2003, PCI-SIG, All Rights Reserved 23

24 Spec vs. Product Simulations Spec simulations for generic board solution Tx to 50Ω load ~175mV Tx Pkg AC Cap Connector 50 Ω 800mV 175mV Baseboard Product simulations for specific package Tx to Rx (die-to-die) pad margins Card Pkg Rx Determine pad margins 800mV? Baseboard Card Copyright 2003, PCI-SIG, All Rights Reserved 24

25 Baseboard vs Card TX Eyes CEM Spec for separate Baseboard vs Card budget Baseboard Tx to 50Ω load Tx Pkg AC Cap Connector 50 Ω 800mV 274mV Baseboard Card Tx to 50Ω load 50 Ω AC Cap Pkg Tx 514mV 800mV Card Copyright 2003, PCI-SIG, All Rights Reserved 25

26 Baseboard vs Card RX Eyes CEM Spec defines Baseboard vs Card input requirements Determine pad eye? Eye for Baseboard Rx Rx Pkg Connector 445mV Baseboard Eye for Card Rx 238mV Pkg Rx Determine pad eye? Card Copyright 2003, PCI-SIG, All Rights Reserved 26

27 Compliance eye mask Must meet compliance Rx pins Min Rx eye 0.4 UI at 0 mv differential Min Vdiff-p-p at Rx 175 mv Add any Tx jitter not included in modeling Rx Eye Tx Jitter Compliance Eye 87.5mV 0mV -87.5mV 0.2UI 0.2UI 0.3UI 0.2UI 0.3UI 0.2UI Copyright 2003, PCI-SIG, All Rights Reserved 27

3 pf RX res = 53 TX res = 53 MB length = 12" (with 250mil BO) Card length = 4" (with 250mil BO) AC cap = 200 nf MB Zo = High ~113 diff Z

28 Data Analysis Example eye diagrams at RX pin Eye mask Jitter 0.5 UI 0.5 UI Median Jitter Example parameters for worst- case eye: RX cap = 1.3 pf TX cap = 1.3 pf RX res = 53 TX res = 53 MB length = 12" (with 250mil BO) Card length = 4" (with 250mil BO) AC cap = 200 nf MB Zo = High ~113 diff Z Card Zo = High ~113 diff Z De-emph emph = 3 db Swing = 800 mv Edge rate = slow Vias = 6 Driving direction = card Tx, MB Rx 30% guard band for AC common mode (for fiber weave effects) 20% guard band otherwise Copyright 2003, PCI-SIG, All Rights Reserved 28

30 Return Loss Simulations Return loss simulations for package using ADS/HSPICE/HFSS models Differential return loss targets from -10 to -15dB at 1.25GHz AC sweep up to 6 GHz Copyright 2003, PCI-SIG, All Rights Reserved 30

31 Ref channel for RX simulations Return Loss spec is not sufficient to guarantee RX operability Use Ref channel model for RX simulations Calibrate T-line with ~13.2dB loss to 175mV at 50Ω load Use Spec TX (800mV swing, -3.5dB deemphasis, 0.3UI TX jitter) Spec TX Pkg 29.6 stripline T-line 175mV Example Ref channel model 50Ω Determine pad eye for RX design Package design under test Copyright 2003, PCI-SIG, All Rights Reserved 31

33 Signal measurement Generate compliance pattern per Spec Probe with real time scope (> 6 GHz analog bandwidth, > 20 G sampling) Scope post-processing software for Compliance Eye diagram analysis Rx Eye Diagram Voltage (Volts) Relative Unit Interval Time (Seconds) x Validate compliance eye diagram using scope Copyright 2003, PCI-SIG, All Rights Reserved 33

Analysis Methodology Average UI recovered from 3500 UI Voltage margin & Jitter analysis across 250 UI Repeat analysis by sweeping in 100 UI increments across entire acquisition AC Common Mode is

34 Analysis Methodology Average UI recovered from 3500 UI Voltage margin & Jitter analysis across 250 UI Repeat analysis by sweeping in 100 UI increments across entire acquisition AC Common Mode is reported for the entire acquisition Voltage (volts) 3,500 UI Clock Recovery Window (CRW) 250 UI Analysis Window Centered with CRW Sweep CRW Across Waveform Time (µsec) Waveform Data Copyright 2003, PCI-SIG, All Rights Reserved 34

Interpretation of Results Scope post-processing software Transition Eye De-emphasized Eye Max jitter Min Eye voltage margin AC Common mode Probe

35 Interpretation of Results Scope post-processing software Transition Eye De-emphasized Eye Max jitter Min Eye voltage margin AC Common mode Probe locations Tx output at 50Ω load Rx pin Example transition bit Eye Example de- emphasized bit Eye Copyright 2003, PCI-SIG, All Rights Reserved 35

36 Summary PCI Express point-to-point layout is straightforward Manage loss and symmetry in PCB to meet interconnect budget Follow basic layout rules and design tradeoffs to implement typical topologies Perform simulations to maximize solution space for complex topologies Validate compliance eye diagrams using real time scope Copyright 2003, PCI-SIG, All Rights Reserved 36

37 Collateral Whitepaper and other technical collateral available from the Intel Developer Network for PCI Express* Architecture Where attendees get additional and updated information Copyright 2003, PCI-SIG, All Rights Reserved 37

Q2 QMS/QFS 16mm Stack Height Final Inch Designs In PCI Express Applications Generation Gbps. Revision Date: February 13, 2009

Q2 QMS/QFS 16mm Stack Height Final Inch Designs In PCI Express Applications Generation 2 5.0 Gbps Revision Date: February 13, 2009 Copyrights and Trademarks Copyright 2009 Samtec, Inc. Developed in conjunction