Dimensions 49.5mm x 35mm PCB (56.5mm x 27mm including overhaning components) Stackable on 10mm pitch.

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1 Specification DSL32M RevB1 Key Features Stackable bidirectional high voltage multiplexer 32 independent channel switches Handles up to +/-100V signals Low on resistance (15ohm large signals, 25ohm small signal typical values) DC to 20MHz analogue small signal frequency range 20MHz Serial Peripheral Interface programming Dimensions 49.5mm x 35mm PCB (56.5mm x 27mm including overhaning components) Stackable on 10mm pitch. Channel Interface In 50way 1.27mm SMC plug (ERNI Electronics) on lower face 32 individual channel signals (with 2 associated common signal returns) from previous stage Vpp bias (+100V) and Vnn bias (-100V) power supplies from previous stage Logic power supply (+3.3V) and SPI interface from previous stage Channel Interface to next DSL32M 50way 1.27mm SMC socket (ERNI Electronics) on top face 32 individual channel signals (with 2 associated common signal returns) for next DSL32M Vpp bias (+100V) and Vnn bias (-100V) power supplies for next DSL32M Logic power supply (+3.3V) and SPI interface for controlling next DSL32M Array Interface 50way 1.27mm SMC right angle socket (ERNI Electronics) on top face 32 individual multipexed signals (with 2 associated common signal returns) to array Vpp bias (+100V) and Vnn bias (-100V) power supplies for array interface Logic power supply (+3.3V) and SPI interface for controlling array interface Stack of four DSL32Ms for 32 channel 128 element interface Diagnostic Sonar Ltd. Page 1 of 6 Last update: 21 November 2011

2 Channel Interface In 50way 1.27mm SMC plug (ERNI Electronics) on under side Signal Name Function Type Comments Ch0..Ch31 32 individual Tx/Rx channels IO Channel interface to pulsers &/or receivers FDTx0..FDTx3 4 FRD transmit channels I Reserved AGND Analogue Ground G Common analogue signal return Vpp bias +ve high voltage power rail PI +ve PSU in for HV multiplexers Vnn bias -ve high voltage power rail PI -ve PSU in for HV multiplexers DGND Digital Ground G Common digital ground Vdd +3.3 digital power rail PI Digital power in for SPI interface SCLK SPI Serial Clock I Clock signal for SPI data SCLR SPI Clear I Clear signal for latched SPI data SLE- SPI Latch Enable I Low to transfer data from SPI registers SDI SPI Data In I Serial data into multiplexers SDR Serial Data Return O Serial Data back to SPI control interface Reserved Not Connected Leave unconnected 50way plug is ERNI part number ( See website ( for mating parts. Channel Interface Out 50way 1.27mm SMC socket (ERNI Electronics) on top side Signal Name Function Type Comments Ch0..Ch31 32 individual Tx/Rx channels IO Channel interface to next DSL32M FDTx0..FDTx3 4 FRD transmit channels O Reserved AGND Analogue Ground G Common analogue signal return Vpp bias +ve high voltage power rail PO +ve PSU out for next DSL32M Vnn bias -ve high voltage power rail PO -ve PSU out for next DSL32M DGND Digital Ground G Common digital ground Vdd +3.3 digital power rail PO Digital power out for next DSL32M SCLK SPI Serial Clock O Clock signal for SPI data SCLR SPI Clear O Clear signal for latched SPI data SLE- SPI Latch Enable O Low to transfer data from SPI registers SDO SPI Data Out O Serial data out to next DSL32M SDR Serial Data Return I Serial Data back from next DSL32M Reserved Not Connected Leave unconnected 50way socket is ERNI part number ( See website ( for mating parts. Diagnostic Sonar Ltd. Page 2 of 6 Last update: 21 November 2011

3 Array Interface Out 50way 1.27mm SMC right angle socket (ERNI Electronics) on top side Signal Name Function Type Comments Arr0..Arr31 32 individual Muxed channels IO Multiplexed element interface to array AGND Analogue Ground G Common analogue signal return Vpp bias +ve high voltage power rail PO +ve PSU out for array interface Vnn bias -ve high voltage power rail PO -ve PSU out for array interface DGND Digital Ground G Common digital ground Vdd +3.3 digital power rail PO Digital power out for array interface SCLK SPI Serial Clock O Clock signal for SPI data SCLR SPI Clear O Clear signal for latched SPI data SLE- SPI Latch Enable O Low to transfer data from SPI registers SDO SPI Data Out O Serial data out to array interface SDR Serial Data Return I Serial Data back from array interface Reserved Not Connected Leave unconnected 50way socket is ERNI part number ( See website ( for mating parts. Channel Interface In (straight 50way surface mount plug on bottom surface of 32M) A1 reserved B1 Vpp bias A2 reserved B2 Vnn bias A3 SDR B3 GND A4 SCLR B4 Vdd A5 SDI B5 SCLK A6 GND B6 SLE- A7 FD_Tx1 B7 FD_Tx0 A8 FD_Tx3 B8 FD_Tx2 A9 Ch0 B9 GND A10 Ch2 B10 Ch1 A11 Ch4 B11 Ch3 A12 Ch6 B12 Ch5 A13 Ch8 B13 Ch7 A14 Ch10 B14 Ch9 A15 Ch12 B15 Ch11 A16 Ch14 B16 Ch13 A17 Ch16 B17 Ch15 A18 Ch18 B18 Ch17 A19 Ch20 B19 Ch19 A20 Ch22 B20 Ch21 A21 Ch24 B21 Ch23 A22 Ch26 B22 Ch25 A23 Ch28 B23 Ch27 A24 Ch30 B24 Ch29 A25 GND B25 Ch31 Diagnostic Sonar Ltd. Page 3 of 6 Last update: 21 November 2011

4 Channel Interface Out (straight 50way surface mount socket on top surface of 32M) A1 reserved B1 Vpp bias A2 reserved B2 Vnn bias A3 SDR B3 GND A4 SCLR B4 Vdd A5 SDO B5 SCLK A6 GND B6 SLE- A7 FD_Tx1 B7 FD_Tx0 A8 FD_Tx3 B8 FD_Tx2 A9 Ch0 B9 GND A10 Ch2 B10 Ch1 A11 Ch4 B11 Ch3 A12 Ch6 B12 Ch5 A13 Ch8 B13 Ch7 A14 Ch10 B14 Ch9 A15 Ch12 B15 Ch11 A16 Ch14 B16 Ch13 A17 Ch16 B17 Ch15 A18 Ch18 B18 Ch17 A19 Ch20 B19 Ch19 A20 Ch22 B20 Ch21 A21 Ch24 B21 Ch23 A22 Ch26 B22 Ch25 A23 Ch28 B23 Ch27 A24 Ch30 B24 Ch29 A25 GND B25 Ch31 Array Interface (right-angled 50way surface mount socket on top surface of 32M) B25 reserved A25 Vpp bias B24 reserved A24 Vnn bias B23 SDR A23 GND B22 SCLR A22 Vdd B21 SDO A21 SCLK B20 GND A20 SLE- B19 reserved A19 reserved B18 reserved A18 reserved B17 Arr0 A17 GND B16 Arr2 A16 Arr1 B15 Arr4 A15 Arr3 B14 Arr6 A14 Arr5 B13 Arr8 A13 Arr7 B12 Arr10 A12 Arr9 B11 Arr12 A11 Arr11 B10 Arr14 A10 Arr13 B9 Arr16 A9 Arr15 B8 Arr18 A8 Arr17 B7 Arr20 A7 Arr19 B6 Arr22 A6 Arr21 B5 Arr24 A5 Arr23 B4 Arr26 A4 Arr25 B3 Arr28 A3 Arr27 B2 Arr30 A2 Arr29 B1 GND A1 Arr31 Diagnostic Sonar Ltd. Page 4 of 6 Last update: 21 November 2011

5 Muxer Stack Output Connector (50way socket) SDO next 32 LAST STACK ARRAY SDO array 3 SCLR, SLE-, SCK pole Single way Single throw 32 Array Connector (50way socket) 3 3 SDR SDI 32 Muxer Stack Input Connector (50way plug) DSL32M Hardware Block Diagram Diagnostic Sonar Ltd. Page 5 of 6 Last update: 21 November 2011

6 Application Information The 32 individual switches are controlled by means of a 32bit serial shift register and transparent latch. Each of the 32 data bits controls a single analogue switch with logic 1 for On and logic 0 for Off. All switches are initialised to Off at power up. SLE- controls the transparent latch and is set to logic 0 to transfer the shift register outputs to the switches and so can be held at logic 1 for clocking data through the shift registers without affecting the switch outputs. The latch clear, SCLR, is set to logic 1 to reset all latch outputs to 0 irrespective of the shift register output states. The data is clocked into, and out of, the shift register on the rising edge of SCLK with the most significant bit first. After 32 clocks the most significant bit will arrive at the last switch, for controlling Channel 31. The 3 position jumper on the DSL32M provides the routing for the SPI (Serial Peripheral Interface) daisy-chaining. Fit the jumper in the: STACK position if the DSL32M in not the last in the stack; LAST position if the DSL32M is the last in the stack and is not being used with a DSL32A array interface board; ARRAY position if the DSL32M is the last in the stack and is being used with a DSL32A array interface board. Diagnostic Sonar Ltd. Page 6 of 6 Last update: 21 November 2011

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