Motherboard to MicroZed Interfaces

Transcription

1 Motherboard to MicroZed Interfaces Excerpts and Thoughts on Various Interfaces Christopher Woodall Benjamin Havey ADC Data (Parallel) Interface Requirements ADC Configuration Interface Parallel Interface Serial Interface Requirements Stage One Stage Two (After ADC proven functional) DDS Serial Interface Signals Serial Interface Timing Protocol Automatic IO_UPDATE Information* Connecting All DDS s Together Peripheral Interfaces Control/Enable Signals LEDs Buttons GPIO Pin Map

2 I. ADC Data (Parallel) Interface Figure 1: ADC Pins

3 Figure 2: I/O Characteristics for ADC Interfaces Figure 3:ADC DDR LVDS Mode Timing Characteristics

4 Figure 4: Timing Diagram for DDR LVDS System over a long time. Figure 5: Timing Diagram for DDR LVDS with Delays.

5 Requirements 2 Channel Interface Combines even and odd transmissions in the appropriate manner into one sample Interface should sign extend from 14 bits to 16 bits as needed. Should be able to take up to 32k Samples from each channel before the memory needs to be flushed out. Programmable Sample Size Build a FIFO or other queue of samples. Interlace the two 16 bit samples of the two channels into one 32 bit number for each sample period. Corresponds to pins labeled ADC_DATA in the pinmap file. 16 bit Sign Extended Sample Ch. A 16 bit sign extended sample ch.b II. ADC Configuration Interface A. Parallel Interface Figure fignum: Parallel Configuration Description

6 Figure fignum: Parallel Control Voltages

7 B. Serial Interface Figure fignum: Timing Diagram of ADC Serial Configuration Interface Figure fignum: Reset Timing for ADC Serial Configuration Interface

8 Figure fignum: Overview of Register Map for ADC Serial Interface C. Requirements 1. Stage One Implementation of Parallel Configuration. SCK tied to GND SEN tied to GND All CTRL pins tied to GND RESET tied to VDD 2. Stage Two (After ADC proven functional) Implementation of SPI Configuration Ability to control GAIN, LVDS vs. CMOS, Power Down Modes Operates with Serial Readout to confirm settings (Debug Feature)

9 III. DDS Serial Interface Signals The following signals are used as part of the AD9910 s serial interface. The interface is SPI like and transfers MSB first, but has a few quirks: 1) By default SDIO is bi directional. 2) SDO is by default inactive 3) IO_UPDATE needs to be strobed high for more than 1 SYNC_CLK period to move from IO buffers to the actual internal registers that set values. Signal Name Directionality Description SDIO BiDirectional by Default (Can be set to only be SDI) Data is always written into the AD9910 on this pin. However, this pin can be used as a bidirectional data line. Bit 1 of CFR1 Register Address 0x00 controls the configuration of this pin. The default is cleared, which configures the SDIO pin as bidirectional. SDO Output (not active by default) Data is read from this pin for protocols that use separate lines for transmitting and receiving data. When the AD9910 operates in single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. SCLK Input The serial clock pin is used to synchronize data to and from the AD9910 and to run the internal state machines.

10 #CS Input CS is an active low input that allows more than one device on the same serial communications line. The SDO and SDIO pins go to a high impedance state when this input is high. If driven high during any communications cycle, that cycle is suspended until CS is reactivated low. Chip select (CS) can be tied low in systems that maintain control of SCLK. IO_UPDATE Input (default) Output (IO Update active bit set) The I/O_UPDATE initiates the transfer of written data from the I/O port buffer to active registers. I/O_UPDATE is active on the rising edge, and its pulse width must be greater than one SYNC_CLK period. It is either an input or output pin depending on the programming of the internal I/O update active bit. IO_RESET Input I/O_RESET synchronizes the I/O port state machines without affecting the contents of the addressable registers. An active high input on the I/O_RESET pin causes the current communication cycle to abort. After I/O_RESET returns low (Logic 0), another communication cycle can begin, starting with the instruction byte write.

11 Serial Interface Timing Figure 1: Serial Interface Timing Charts. AD9910 Datasheet Page 49 *

12 Figure 2: Serial Interface Timing Charts for IO_UPDATE. AD9910 Datasheet Page 42 * Protocol This information is taken from page 48 of the AD9910 datasheet. First an INSTRUCTION byte is sent and then the appropriate number of bytes for the indicated register are sent. Most registers have 4 bytes, but a few have 8 bytes. MSB Instruction Byte D7 D6 D5 D4 D3 D2 D1 D0 LSB R/#W X X A4 A3 A2 A1 A0

13 Automatic IO_UPDATE Information

14 Connecting All DDS s Together The connection of all of the DDS s is not a difficult procedure, but requires some careful planning. The following signals are shared: DDS_CLK_EN DDS_POWER_GOOD DDS_SCLK DDS_IOUPDATE DDS_IORESET The following signals are individually addressed: CS MISO MOSI PWR_EN The turnon logic should work as follows: ALL DDS related IOs are tristated (except shared signals, which are tied LOW) PWR_EN is raised when we want to activate a channel POWER_GOOD goes high and all IOs are set to their default settings. Communications with DDS s continue as desired. Note that the shared signals are not set up to be tristated. This is an issue with the layout and may be fixed if deemed necessary. The CLOCK is shared, but there are different data lines and chip selects. We can load all of the data at once to all 6 DDS s (send arbitrary commands to all 6 at once synced to the same clock) or send transmissions as if the it were a genuine SPI bus. (MOSI tied together using CS to determine which is being selected). Note: The system is not designed to be hot pluggable. If any DDS is down the whole DDS interface should be tristated. IV. Peripheral Interfaces A. Control/Enable Signals DDS_POWER_GOOD: Open Collector output from all DDS boards, if low power is not good, if high good. Tristate all DDS communications until DDS_POWER_GOOD is on

15 DDS_CLK_EN: HIGH once POWER_GOOD. Option over ethernet to turn HIGH or LOW over ethernet. PWR_EN[1..6]: Enable Power for any given DDS. Default to LOW, HIGH when we want to enable. In early test versions default to HIGH (set all channels on). ADC_CLK_EN: Default to HIGH, allow to turn off clock via ethernet comms. B. LEDs STATUS_LEDS[3..0]: Use to breakout divided down system clock, errors, other indicators, as needed. RGB LED: Use for status, breathing, cool fades and effects (WOW factor little else) C. Buttons Use for whatever... D. GPIO Don t worry about this yet. V. Pin Map Pin Name Description Logic Level Group Clock? Bank 34, T10 SDOUT 3.3V LVCMOS ADC Serial No No Bank 34, T11 CTRL1 3.3V LVCMOS ADC Serial No No Bank 34, U12 SDATA 3.3V LVCMOS ADC Serial No No Bank 34, T12 SEN 3.3V LVCMOS ADC Serial No No Bank 34, V13 CTRL3 3.3V LVCMOS ADC Serial No No Bank 34, U13 CTRL2 3.3V LVCMOS ADC Serial No No Bank 34, W13 RESET 3.3V LVCMOS ADC Serial No No Bank 34, V12 SCLK 3.3V LVCMOS ADC Serial Yes No Bank 34, T15 SWITCH 3.3V LVCMOS SWITCH No No Bank 34, T14 RGB_LED_B 3.3V LVCMOS LED No No Bank 34, R14 RGB_LED_G 3.3V LVCMOS LED No No Bank 34, P14 STATUS_LEDS3 3.3V LVCMOS LED No No Bank 34, Y17 STATUS_LEDS2 3.3V LVCMOS LED No No Bank 34, Y16 RGB_LED_R 3.3V LVCMOS LED No No Bank 34, Y14 STATUS_LEDS1 3.3V LVCMOS LED No No Timing constraint

16 Bank 34, W14 STATUS_LEDS0 3.3V LVCMOS LED No No Bank 34, U17 DA0_P 25LVDS ADC_DATA No set for 250MHz Bank 34, T16 DA0_N 25LVDS ADC_DATA No set for 250MHz Bank 34, W15 DB12_N 25LVDS ADC_DATA No set for 250MHz Bank 34, V15 DB12_P 25LVDS ADC_DATA No set for 250MHz Bank 34, U15 DA2_P 25LVDS ADC_DATA No set for 250MHz Bank 34, U14 DA2_N 25LVDS ADC_DATA No set for 250MHz Bank 34, U19 DB10_N 25LVDS ADC_DATA No set for 250MHz Bank 34, U18 DB10_P 25LVDS ADC_DATA No set for 250MHz Bank 34, P19 DA4_P 25LVDS ADC_DATA No set for 250MHz Bank 34, N18 DA4_N 25LVDS ADC_DATA No set for 250MHz Bank 34, P20 DB8_N 25LVDS ADC_DATA No set for 250MHz Bank 34, N20 DB8_P 25LVDS ADC_DATA No set for 250MHz Bank 34, U20 DA6_P 25LVDS ADC_DATA No set for 250MHz Bank 34, T20 DA6_N 25LVDS ADC_DATA No set for 250MHz Bank 34, W20 DB6_N 25LVDS ADC_DATA No set for 250MHz Bank 34, V20 DB6_P 25LVDS ADC_DATA No set for 250MHz Bank 34, Y19 DA8_P 25LVDS ADC_DATA No set for 250MHz Bank 34, Y18 DA8_N 25LVDS ADC_DATA No set for 250MHz Bank 34, W16 DB4_N 25LVDS ADC_DATA No set for 250MHz Bank 34, V16 DB4_P 25LVDS ADC_DATA No set for 250MHz Bank 34, R17 DA10_P 25LVDS ADC_DATA No set for 250MHz Bank 34, R16 DA10_N 25LVDS ADC_DATA No set for 250MHz Bank 34, R18 DB2_N 25LVDS ADC_DATA No set for 250MHz Bank 34, T17 DB2_P 25LVDS ADC_DATA No set for 250MHz Bank 34, V18 DA12_P 25LVDS ADC_DATA No set for 250MHz Bank 34, V17 DA12_N 25LVDS ADC_DATA No set for 250MHz Bank 34, W19 DB0_N 25LVDS ADC_DATA No set for 250MHz Bank 34, W18 DB0_P 25LVDS ADC_DATA No set for 250MHz Bank 34, P18 CLKOUT_P 25LVDS ADC_DATA Yes set for 250MHz Bank 34, N17 CLKOUT_N 25LVDS ADC_DATA Yes set for 250MHz Bank 34, P16 ADC CLK Enable 3.3V LVCMOS ENABLES No No Bank 34, P15 NC, pull low 3.3V LVCMOS NC No No Bank 34, R19 NC, pull low 3.3V LVCMOS NC No No

17 Bank 34, T19 NC, pull low 3.3V LVCMOS NC No No Bank 35, B20 NC 3.3V LVCMOS NC No No Bank 35, C20 NC 3.3V LVCMOS NC No No Bank 35, A20 DDS_IOUPDATE 3.3V LVCMOS DDS No No Bank 35, B19 DDS_IORESET 3.3V LVCMOS DDS No No Bank 35, D18 NC 3.3V LVCMOS NC No No Bank 35, E17 DDS_SCLK 3.3V LVCMOS DDS No No Bank 35, D20 DDS_CS1 3.3V LVCMOS DDS No No Bank 35, D19 DDS_PWR_EN1 3.3V LVCMOS DDS No No Bank 35, E19 DDS_CS6 3.3V LVCMOS DDS No No Bank 35, E18 DDS_PWR_EN6 3.3V LVCMOS DDS No No Bank 35, F17 DDS_MOSI1 3.3V LVCMOS DDS No No Bank 35, F16 DDS_MISO1 3.3V LVCMOS DDS No No Bank 35, L20 DDS_MOSI6 3.3V LVCMOS DDS No No Bank 35, L19 DDS_MISO6 3.3V LVCMOS DDS No No Bank 35, M20 DDS_CS2 3.3V LVCMOS DDS No No Bank 35, M19 DDS_PWR_EN2 3.3V LVCMOS DDS No No Bank 35, M18 DDS_CS5 3.3V LVCMOS DDS No No Bank 35, M17 DDS_PWR_EN5 3.3V LVCMOS DDS No No Bank 35, J19 DDS_MOSI2 3.3V LVCMOS DDS No No Bank 35, K19 DDS_MISO2 3.3V LVCMOS DDS No No Bank 35, L17 DDS_MOSI5 3.3V LVCMOS DDS No No Bank 35, L16 DDS_MISO5 3.3V LVCMOS DDS No No Bank 35, K18 DDS_CS3 3.3V LVCMOS DDS No No Bank 35, K17 DDS_PWR_EN3 3.3V LVCMOS DDS No No Bank 35, H17 DDS_CS4 3.3V LVCMOS DDS No No Bank 35, H16 DDS_PWR_EN4 3.3V LVCMOS DDS No No Bank 35, H18 DDS_MOSI3 3.3V LVCMOS DDS No No Bank 35, J18 DDS_MISO3 3.3V LVCMOS DDS No No Bank 35, G18 DDS_MOSI4 3.3V LVCMOS DDS No No Bank 35, G17 DDS_MISO4 3.3V LVCMOS DDS No No Bank 35, F20 DDS_POWER_G OOD 3.3V LVCMOS ENABLE No No Bank 35, F19 DDS_CLK_EN 3.3V LVCMOS ENABLE No No

18 Bank 35, G20 NC 3.3V LVCMOS NC No No Bank 35, G19 NC 3.3V LVCMOS NC No No Bank 35, H20 GPIO1 3.3V LVCMOS GPIO No No Bank 35, J20 GPIO0 3.3V LVCMOS GPIO No No Bank 35, J14 GPIO9 3.3V LVCMOS GPIO No No Bank 35, K14 GPIO8 3.3V LVCMOS GPIO No No Bank 35, G15 GPIO3 3.3V LVCMOS GPIO No No Bank 35, H15 GPIO2 3.3V LVCMOS GPIO No No Bank 35, N16 GPIO11 3.3V LVCMOS GPIO No No Bank 35, N15 GPIO10 3.3V LVCMOS GPIO No No Bank 35, L15 GPIO5 3.3V LVCMOS GPIO No No Bank 35, L14 GPIO4 3.3V LVCMOS GPIO No No Bank 35, M15 GPIO13 3.3V LVCMOS GPIO No No Bank 35, M14 GPIO12 3.3V LVCMOS GPIO No No Bank 35, J16 GPIO7 3.3V LVCMOS GPIO No No Bank 35, K16 GPIO6 3.3V LVCMOS GPIO No No Bank 35, G14 GPIO15 3.3V LVCMOS GPIO No No Bank 35, J15 GPIO14 3.3V LVCMOS GPIO No No