Synaptic Labs' AXI-Hyperbus Controller Design Guidelines

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Synaptic Labs' AXI-Hyperbus Controller Design Guidelines Table of Contents Introduction...3 1.0 Set-Up Requirements...4 Step 1: Obtain core materials...4 Step 2: License Setup.

1 Synaptic Labs' AXI-Hyperbus Controller Design Guidelines Table of Contents Introduction Set-Up Requirements...4 Step 1: Obtain core materials...4 Step 2: License Setup...4 Step 3: Install AXI HBMC Vivado Component into the project IP Folder S/Labs' HBMC Configuration Synaptic Labs' AXI HBMC IP Vivado Component Option A Same Clock for the Hyperbus memory channel an AXI channel Clocking Wizard Configuration S/Labs' HBMC Configuration Option B Different Clocks for the Hyperbus memory channel and AXI channel Clocking Wizard Configuration S/Labs' HBMC Configuration Example : Synaptic Labs' AXI HBMC IP connected to the MicroBlaze processor MicroBlaze Cache Configuration example Supporting HyperFlash and HyperRAM memory regions in Eclipse / Vivado Address Editor AXI4 Limitations Signal Description...17 Section 5.1 : HyperBus Signal Interface...17 Section 5.2 : PLL Clock Signal Interface...18 Section 5.3: AXI Clock/reset interface...18 Section 5.4 : AXI Write Address Control Interfaces...18 Section 5.5 : Write response channel signals...19 Section 5.6 : Write data channel signals...19 Section 5.7: AXI Read Address Control Interfaces...20 Section 5.8 : Read data channel signals Static Timing Consideration Data Input Timing Constraint Timing Constraints Pin Clustering Current Pin assignment Using 3V HyperRAM and HyperFlash devices Selecting the correct operating frequency in Vivado Selecting the correct voltage in Vivado Connecting the HyperRAM signals to the FPGA I/O...23 Synaptic Labs' 2017 info@synaptic-labs.com V1.4 1

2 Introduction The HyperBus memory from Cypress/ISSI requires 11 external bus signals (12 if the memory is operating at 1.8v). Example data-sheets can be found at ttp:// ). Synaptic Labs' Hyperbus Controller IP has an AXI4 slave interface (please note that not the FULL AXI4 is implemented. These limitations are documented further below.). It supports burst mode access (up to 128 words). All external I/O pads to the Hyperbus memory are generated from within Synaptic Labs' Hyperbus Controller IP. The user does not need to manually instantiate the I/O pads in the design. An external pll is used to generate all the necessary clocks.. Note: Synaptic Labs' Hyperbus Controller IP does NOT support DCARS functionality (Hyper-RAM PSC mode). DCARS is a very specific capability requested by a very specific customer / chipset partner and is only supported by Cypress devices. ISSI devices do not have DCARS support. Cypress do not recommend the implementation of DCARS functionality. DCARS has a maximum frequency of 133 MHz. Synaptic Labs' 2017 info@synaptic-labs.com V1.4 2

3 1.0 Set-Up Requirements Step 1: Obtain core materials 1. Download and install Xilinx Vivado ( or later) on your PC, please ensure that your PC meets the required minimum specification. Step 2: License Setup 1. Next you need to register for Synaptic Labs' HyperBus Memory Controller IP. You can skip this step if you already registered and downloaded the IP. Free enrollment can be obtained from: Step 3: Install AXI HBMC Vivado Component into the project IP Folder 1. In this tutorial we assume that S/Labs HyperBus Memory Controller (HBMC) will be located in the Project directory. Alternatively, in the IP Catalog, you can add a new User Repository pointing to the directory where you have stored S/Labs HBMC IP. 2. Copy S/Labs AXI HBMC IP directory to the Vivado project directory/ip_lib and ensure it is linked in the IP Catalog. Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 3

4 2.0 S/Labs' HBMC Configuration S/Labs' HBMC IP can be configured in Vivado GUI window. Double Click on S/Labs HBMC IP and the following window will pop up. The following is a short description of S/LABS HBMC parameters Is HyperFlash Present : Select whether HyperFlash is used in the project. (For the demo, select none) Is HyperRam Present : Select whether HyperRAM is connected. The user can select the size according to the HyperRAM device connected on the FPGA board. Device Family : This reflects the FPGA device family being used in the project AXI/Hyperbus Clock Dependency : Select Same Hyperbus/AXI clock if the Hyperbus clock (i_hbus_clk_0) and AXI clock (s00_axi_aclk) are connected to the same clock. For the Demo, select Same Hyperbus/AXI clock. Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 4

5 Hyperbus Frequency in Mhz : this parameter has to be greater than or equal to the frequency of the hyperbus input clock (i_hbus_clk_0). For the Demo, use the 100Mhz option. It is used to select the correct timing parameters for the Hyperbus memory devices. Ensure that the hyperbus input clock frequency is less than or equal to the selected frequency. Parameter Value PLL Hyperbus input clock frequency 100 Mhz Less or equal to 100 Mhz 125 Mhz Less or equal to 125 Mhz 150 Mhz Less or equal to 150 Mhz For example, if the PLL clock frequency for the Hyperbus channel is set to 120 Mhz, then the 125 Mhz option should be selected. AXI BustCount Width - this reflects the maximum burst supported by the AXI channel. The actual burst count is calculated as (1 << AXI BustCount Width). For example, if AXI BustCount Width is set to 7, then maximum burst count is 128. Please note that a burstcount of 256 is not currently supported. This is due to the fact that a burstcount of 256 would violate the Tcsm timing paramters for the HyperRAM/HyperFlash memory device. AXI ID Width - this reflect the width of the ID signal for the AXI interface RDS_DELAY_ADJ : this parameter is used to generate a delayed RWDS clock signal in order to latch the incoming data from the HyperRAM or HyperFlash memory device. This parameter needs to be change if static timing violations occur on the HB_RWDS_clock/HB_dq path. The table shows gives an indication of values that can be used as the rds_delay_adj parameter for a given frequency. Frequency RDS_DELAY_ADJ 100 Mhz Mhz Mhz 5 S/Labs AXI HBMC user interface is designed for supporting Hyperbus memories running at up to 150Mhz. However, this is FPGA dependent, and not all FPGA families are capable of reaching that frequency. Top frequency mostly depend on the FPGA family, FPGA I/O pins, speed grade, routing, placement, etc. Setting pblocks on the IP and defining custom placement will slightly increase the top frequency. Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 5

6 3.0 Synaptic Labs' AXI HBMC IP Vivado Component Do not use HB_rstn from S/Labs HBMC IP Connect external pin to 1 if needed A clock wizard is used to generate the clocks for the Hyperbus memory controller and Utility Idelay Control module. The Utility Idelay Control module requires a reference clock of 200Mhz. S/Labs HBMC IP requires 4 clocks : i_hbus_clk_0 : clock driving the Hyperbus controller i_hbus_clk_90 : clock for driving some Hyperbus I/O Signals. It operates at the same frequency as i_hbus_clk_0 but is phase shifted 90 degrees i_hbus_clk_180 : clock for driving some Hyperbus I/O Signals. It operates at the same frequency as i_hbus_clk_0 but is phase shifted 180 degrees. s00_axi_clk : clock driving the AXI interface. When S/Labs HBMC IP is configured to run at a single clock speed, this clock is connected to i_hbus_clk_0 clock. Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 6

7 3.1 Option A Same Clock for the Hyperbus memory channel an AXI channel. This configuration shows how to connect S/Labs' HBMC IP so that the Hyperbus memory channel operates at the same frequency as the AXI bus interface. The advantage of this configuration is lower circuit area. Note how i_hbus_clk_0 and s00_axi_aclk are connected to the same clock Clocking Wizard Configuration The figure below shows a typical example of configuring the Clocking wizard. In this case, the clocks for the Hyperbus channel and AXI channels are all set to 100 Mhz. Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 7

8 3.1.2 S/Labs' HBMC Configuration In this example, S/Labs' HBMC IP is configured with : Is HyperFlash Present : none Is HyperRam Present : none. Device Family : 7SERIES AXI/Hyperbus Clock Dependency : Same Hyperbus/AXI clock Hyperbus Frequency in Mhz : 100Mhz AXI BustCount Width : 7 (maximum burst is 128 **) AXI ID Width : 4 RDS_DELAY_ADJ : 16 Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 8

interface. Note how i_hbus_clk_0 and s00_axi_aclk are connected to a different clock. 3.2.

9 3.2 Option B Different Clocks for the Hyperbus memory channel and AXI channel. This configuration shows how to connect S/Labs' HBMC IP so the Hyperbus memory channel operates at a different clock frequency then the AXI bus interface. Note how i_hbus_clk_0 and s00_axi_aclk are connected to a different clock Clocking Wizard Configuration The figure below shows a typical example of configuring the Clocking wizard. In this case, the clocks for the Hyperbus channel are all set to 100 Mhz, while the clock for the AXI channel is set to 50 Mhz. Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 9

10 3.2.2 S/Labs' HBMC Configuration In this example, S/Labs' HBMC IP is configured with : Is HyperFlash Present : none Is HyperRam Present : none. Device Family : 7SERIES AXI/Hyperbus Clock Dependency : Different Hyperbus/AXI clock Hyperbus Frequency in Mhz : 100Mhz AXI BustCount Width : 7 (maximum burst is 128 **) AXI ID Width : 4 RDS_DELAY_ADJ : 16 Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 10

3.3 Example : Synaptic Labs' AXI HBMC IP connected to the MicroBlaze processor The figure below shows a typical example of S/Labs' HBMC IP connected to the Microblaze processor.

11 3.3 Example : Synaptic Labs' AXI HBMC IP connected to the MicroBlaze processor The figure below shows a typical example of S/Labs' HBMC IP connected to the Microblaze processor. In this example, the Micoblaze Instruction and Data Cache are used and set to 4K with a line length of 8 words. It is important that both the Microblaze Instruction and data caches uses ONLY a line length of 8 words Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 11

12 3.3.1 MicroBlaze Cache Configuration example Synaptic Labs 2017 V1.4 page 12

3.4 Supporting HyperFlash and HyperRAM memory regions in Eclipse / Vivado Address Editor For now we will assume that you have configured S/Labs AXI HBMC IP with HyperFlash and HyperRAM enabled.

13 3.4 Supporting HyperFlash and HyperRAM memory regions in Eclipse / Vivado Address Editor For now we will assume that you have configured S/Labs AXI HBMC IP with HyperFlash and HyperRAM enabled. In this case, the 64 Mbyte HyperFlash memory is associated with chip select 0, while the 8 Mbyte HyperRAM memory is associated with chip select 1. Ensure that all the Hyperbus signals are properly exported to the external connections. Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 13

In the Address editor, a memory region is created for each memory device. Memory region HyperRAM links to the HyperRAM memory device. Memory region HyperFlash links to the HyperFlash memory device.

If this rule is not followed, the design will not operate correctly. This rule applies only when the design has both HyperRAM and HyperFlash enabled.

14 In the Address editor, a memory region is created for each memory device. Memory region HyperRAM links to the HyperRAM memory device. Memory region HyperFlash links to the HyperFlash memory device. ---VERY IMPORTANT--- When assigning the HyperRAM and HyperFlash base addresses in the Address editor ensure that the HyperRAM address offset is set exactly after the HyperFlash end address. If this rule is not followed, the design will not operate correctly. This rule applies only when the design has both HyperRAM and HyperFlash enabled. Example : 0x147ffffff 64 Mbit HyperRAM suppose the HyperFlash base address is set to 0x1000_0000 for a 64Mbyte HyperFlash, the end address is 0x13FF_FFFF then the HyperRAM base address is set to 0x1400_0000 0x Mbit HyperFLASH HyperRAM base address = HyperFlash Base address + HyperFlash Size 0x Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 14

15 4 AXI4 Limitations When designing the current revision of S/Labs HBMC IP, S/Labs focused on the minimum resource usage while servicing the widest applications. Hence, some limitations on the AXI4 interface exist. For most applications, the limitations will have NO effect. If for some reason, the projects needs one or more of the following AXI conditions, then S/Labs can modify the current design to accommodate these features. Maximum Burst : A maximum burst of 128 (32-bit) words is supported. Burst 256 is not supported due to a limitation on the HyperRAM/HyperFlash device. 8-bit or 16-bit bursts are NOT supported. Burst Mode : S/Labs HBMC IP supports a FIXED address and Increment address mode. It only supports a wrapping mode of 8 (32- bit) words. Address Wrapping for other burst lengths is NOT supported. If caches are used, ensure that the line length is set to 8 words. Out of Order and re-ordering : S/Labs' HBM IP does not support out of order or re-ordering on packets. Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 15

16 5.0 Signal Description Section 5.1 : HyperBus Signal Interface Hyperbus Signal Description Comments Board consideration HB_CLK0 Differential clock pair 0 To be connected to pin CK on Hyperbus Memory device 0. HB_CLK0n Differential clock pair 0 (used with 1.8V devices) To be connected to pin CK# on Hyperbus Memory device 0. Connect to HyperRam CK signal Connect to HyperRam CK# signal HB_CLK1 Differential clock pair 1 Additional Clock pair Not connected HB_CLK1n Differential clock pair 1 Additional Clock pair Not connected HB_CS0n Chip select device 0 To be connected to pin CS# on Hyperbus Memory device 0. HB_CS1n Chip select device 1 To be connected to pin CS# on Hyperbus Memory device 1. HB_Wpn HB_RWDS Disables writes to HyperFlash memory devices (Write protect) Read strobe/write mask signal To be connected to pin WP# on any HyperFlash device. To be connected to pin RWDS on all Hyperbus memory devices. Connect to HyperFlash CS# signal. Leave unconnected if HyperFlash not present Connect to HyperRam CS# signal Connect to HyperFlash WP# if needed. Currently not used. Connect to HyperRam/HyperFLASH RWDS signal HB_Dq Data bus (8-bit) DDR Data bus Connect to HyperRam/HyperFLASH Dq signals HB_INTn HB_RST0 HB_RSTn Hyperbus interrupt from HyperFlash to FPGA. Hyperbus reset from HyperFlash to FPGA Reset to Hyperbus Memory To be connected to pin INT# on all HyperFlash device. To be connected to pin RSTO on all HyperFlash devices. To be connected to pin RESET# on all HyperBus memory devices. Optional Pullup Resistor (not used for the HyperRam Only Configuraton) Connect to HyperFlash INT# signal. Connect to HyperFlash RSTO signal DO not USE HB_INTn and HB_RSTO signals of the Hyperbus memories are open drain output without a pull-up resistor. Therefore, when these signals are used in the design, it is suggested that a pullup resistor is inserted either by setting the appropriate constraint on the input FPGA pad or adding a resistor on the board itself. Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 16

17 Section 5.2 : PLL Clock Signal Interface Pll Signal Description Comments i_hbus_clk_0 Hyperbus Clock Hyperbus Clock i_hbus_clk_90 Hyperbus Clock (90 phase shift) 90 degress phase shift i_hbus_clk_180 Hyperbus Clock (180 phase shift) 180 degress phase shift Section 5.3: AXI Clock/reset interface AXI signal Description Comments s00_axi_aclk AXI clock source s00_axi_aresetn AXI reset source Section 5.4 : AXI Write Address Control Interfaces Avalon-MM signal Description Comments s00_axi_awid s00_axi_awaddr s00_axi_awlen s00_axi_awsize s00_axi_awburst Write address ID. This signal is the identification tag for the write address group of signals Write address. Burst length. The burst length gives the exact number of transfers in a burst. Burst size. This signal indicates the size of each transfer in the burst Burst type. The burst type and the size information, determine how the address for each transfer within the burst is calculated. s00_axi_awlock Lock type Not used s00_axi_awvalid s00_axi_awready Write address valid. This signal indicates that the channel is signaling valid write address and control information Write address ready. This signal indicates that the slave is ready to accept the address and associated control signals ** Maximum supported burst length is 128 ** Transfer size of 8, 16 and 32-bits are supported 32-bit Fixed and increment bursts are supported. Wrap is only supported for 32-bit, burst 8 Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 17

18 Section 5.5 : Write response channel signals AXI signal Description Comments s00_axi_bid s00_axi_bresp s00_axi_bvalid s00_axi_bready Response ID tag. This signal is the ID tag of the write response Write response. This signal indicates the status of the write transaction. Write response valid. This signal indicates that the channel is signaling a valid write respons Response ready. This signal indicates that the master can accept a write response Section 5.6 : Write data channel signals AXI signal Description Comments s00_axi_wid s00_axi_wdata s00_axi_wstrb s00_axi_wlast s00_axi_wvalid s00_axi_wready Write ID tag. This signal is the ID tag of the write data transfer. Write data Write strobes. This signal indicates which byte lanes hold valid data. There is one write strobe bit for each eight bits of the write data bus. Write last. This signal indicates the last transfer in a write burst Write valid. This signal indicates that valid write data and strobes are available Write ready. This signal indicates that the slave can accept the write data. Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 18

19 Section 5.7: AXI Read Address Control Interfaces Avalon-MM signal Description Comments s00_axi_arid s00_axi_araddr s00_axi_arlen s00_axi_arsize s00_axi_arburst Read address ID. This signal is the identification tag for the write address group of signals Read address. Burst length. The burst length gives the exact number of transfers in a burst. Burst size. This signal indicates the size of each transfer in the burst Burst type. The burst type and the size information, determine how the address for each transfer within the burst is calculated. s00_axi_arlock Lock type Not used s00_axi_arvalid s00_axi_arready Read address valid. This signal indicates that the channel is signaling valid write address and control information Read address ready. This signal indicates that the slave is ready to accept the address and associated control signals ** Maximum supported burst length is 128 ** Transfer size of 8, 16 and 32-bits are supported 32-bit Fixed and increment bursts are supported. Wrap is only supported for 32-bit, burst 8 Section 5.8 : Read data channel signals AXI signal Description Comments s00_axi_rid s00_axi_rdata s00_axi_rresp s00_axi_rlast s00_axi_rvalid s00_axi_rready Read ID tag. This signal is the ID tag of the write data transfer. Read data Read response. This signal indicates the status of the read transfer. Read last. This signal indicates the last transfer in a write burst Read valid. This signal indicates that valid write data and strobes are available Read ready. This signal indicates that the slave can accept the write data. Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 19

20 6.0 Static Timing Consideration 6.1 Data Input Timing Constraint The input read strobe (HB_RWDS) signal is edge aligned to the data signal (HB_dq). S/Labs HBMC RDS_DELAY_ADJ parameter is used to adjust the internal delay on the RWDS clock signal. 6.2 Timing Constraints A sample constraint script (HyperRAM.xdc) shows some typical timing constraints for the Hyperbus signals. Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 20

21 7.0 Pin Clustering Please ensure all HyperBus channel pins are clustered physically close together in the programmable FPGA fabric. The FPGA board designer will need to balance the place-androute requirements of the HyperBus Controller Logic against the ideal placement of pins from the board layout perspective to minimize skew across pins and to minimise pin-to-pin wire latency delay. The signals received on the HB_DQ pins are fed as an input into a single on-chip blockram. The parallel capture of those signals is clocked by HB_RWDS. Hence the location of the HB_DQ/HB_RWDS pins must be placed in a way to also ensure low wire latencies to that single on-chip SRAM. From the perspective of the Hyperbus memory controller, try to ensure that the data being transported over all DQ signals arrive as close as possible, with as little skew, at the I/O pads The following output signals { HB_CLK0, HB_CLK0n, HB_CLK1, HB_CLK1n, HB_CS0n, HB_CS1n} use an ddr output pad configured in DDR register mode. The following bi-direction signals HB_Dq and HB_RWDS (Output mode) - use a ddr output pad with output enable control (oe) and configured in DDR register mode. (Input mode) - Unregistered buffer mode (pass through) Please ensure these DDR signals are mapped to IO Elements with DDR capabilities. Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 21

22 8.0 Current Pin assignment All devices connected to a HyperBus memory channel must use the same Voltage standard. In Vivado Pin Assignment editor, all pins related to the Hyperbus Memories are set to 1.8 V. (This is device dependent and should be changed accordingly if a 3V Hyperbus memory device is used in the design). 8.1 Using 3V HyperRAM and HyperFlash devices 8.2 Selecting the correct operating frequency in Vivado The 3V HyperRAM and HyperFlash memories supports a maximum frequency of 100 Mhz. Hence the designer needs to select a frequency that is supported by the memory device. In Vivado block schematic, open S/Labs' HBMC IP component. Ensure that The Hyperbus channel clock Frequency is set to 100Mhz or less. We suggest that the designer use the One Clock operation for both the Avalon Port and the Hyperbus Channel Port. 8.3 Selecting the correct voltage in Vivado The designer needs to set the HyerRAM/HyperFlash voltage level signals to 3V. In Vivado, open the Assignment editor. Set the Hyperbus memory signals voltage level to 3V. 8.4 Connecting the HyperRAM signals to the FPGA I/O The 3V HyperRAM and HyperFlash devices do NOT require a differential clock pair. HB_CLK0n is left unconnected. Synaptic Labs 2017 info@synaptic-labs.com V1.4 page 22

Synaptic Labs' Hyperbus Controller Design Guidelines

Synaptic Labs' Hyperbus Controller Design Guidelines Table of Contents Introduction...1 1.0 Synaptic Labs' HBMC Controller IP Qsys Component...3 2.0 Typical S/Labs HBMC connection in Qsys...4 3.0 Typical