Synaptic Labs (S/Labs) HyperBus Memory Controller (HBMC) Tutorial for Intel FPGA devices

Transcription

1 Benjamin Gittins Chief Technical Officer Mbl: Synaptic Laboratories Ltd. Company ID Monday, July 16, 2018 Synaptic Labs (S/Labs) HyperBus Memory Controller (HBMC) Tutorial for Intel FPGA devices T001B: A Qsys based Nios II reference design with a simple Memory Bandwidth Benchmark of the HyperRAM device using S/ Labs' HBMC IP This tutorial is a a Qsys based Nios II reference design with a simple Memory Bandwidth Benchmark of the HyperRAM device using S/Labs' HBMC IP. This tutorial also shows how to download the Nios II firmware into the FPGA device using the Nios II development environment. This tutorial should be started only after completing all the steps described in the previous tutorial in this series titled: T001A: A Qsys based Nios II Reference design with a simple self test of the HyperFlash and HyperRAM device using S/Labs' HBMC IP The reference project for this Tutorial is bundled with a Free Trial License for the full-edition of S/Labs HBMC IP That Quartus License Key never expires. Please note: This tutorial assumes that the FPGA board type field in the Master Configuration tab of S/Labs HyperBus Memory Controller IP has been set to: Devboards - HyperMAX 10M25 (HyperRAM), or Devboards - HyperMAX 10M50 (HyperRAM), or Intel Cyclone 10LP Evaluation Kit (HyperRAM) T001B 16 July page 1 of 14

2 Table of Contents Synaptic Labs (S/Labs) HyperBus Memory Controller (HBMC) Tutorial for Intel FPGA devices 1 T001B: A Qsys based Nios II reference design with a simple Memory Bandwidth Benchmark of the HyperRAM device using S/Labs' HBMC IP 1 Table of Contents 2 1. Modify the memory initialization field(s) in Qsys 3 2. Synthesize the Design 3 3. Preparing the memory benchmarking firmware 4 4. Configure the Board Support Package (BSP) 6 5. Generate the BSP and clean the project 9 6. Install the memory testing source code 9 7. Build the Nios II Application 9 8. Program the FPGA Bitstream into the FPGA device Run the Benchmark from within Nios II SBT Obtaining good to excellent levels of effective memory bandwidth when using HyperBus devices 14 T001B 16 July page 2 of 14

3 1. Modify the memory initialization field(s) in Qsys 1.1. This memory benchmarking project does not fit within the 40 KB on-chip SRAM. Therefore, we are going to remove the.hex file initialization file for the on-chip memory in the Qsys project: In the Platform Designer application, open the hypernios.qsys project Open the parameters for the On-Chip Memory module Untick the [ ] Enable non-default initialization file field Optional: Untick the [ ] Initialize memory content field as memory initialization of this On-Chip Memory is not required in this example project Save and regenerate the Qsys design Close the Qsys window. 2. Synthesize the Design 2.1. Go to the Quartus Prime window In the menu bar, select: Processing Start Compilation 2.3. The assembler step will create the SRAM FPGA Bitstream file (.sof). Please note: The memory initialisation file (.hex) for the SRAM will no longer be embedded in that FPGA Bitstream file Please note that it is possible to configure the NIOS II Software Built Tools for Eclipse (SBT) independently of (re)compiling the FPGA bitstream. This is because: (a) the SBT tools use the hypernios.sopcinfo file generated by Qsys; but (b) does not use any files generated during hardware compilation process So while the computer is compiling your design we can immediately proceed to the next step below. T001B 16 July page 3 of 14

4 3. Preparing the memory benchmarking firmware 3.1. We will now open the NIOS II Software Built Tools for Eclipse In Quartus Prime, go to the menu bar and select: Tools NIOS II Software Built Tools for Eclipse. /software Click the [ Browse ] button. A new file selector window will open. In this tutorial we are going to select the software folder located inside the project folder as the workspace. Note: This is the same software folder that we previously used in Tutorial 001A of this Tutorial Series Be sure to leave the [ ] Use this as the default field unticked Click the [ OK ] button Create a simple application and BSP The software folder in the reference project will have the HelloWorld application from Tutorial 001A We now want to create a new Nios II application, and Nios II board support package for the Nios II software HyperRAM bandwidth benchmarking application In the Eclipse window, goto the menu bar and select: File New NIOS II Application and BSP from Template T001B 16 July page 4 of 14

5 A new window will pop up: (most of the fields below will initially be empty) /hypernios.sopcinfo In the Target hardware information section, click on the [ ] button A file browser window will open. Locate and select the hypernios.sopcinfo file generated by Qsys and stored in the reference project directory. Click [ Open ] It may take around 30 seconds for the Eclipse application to parse the.sopcinfo file Select a Project name. In this example, we are using Benchmark as the project name Ensure that: [x] Use default location is ticked We now need to select a template from the Project Template list. In this example, select the Hello World template Press the [ Finish ] button to complete the current step The Nios II SBT will now generate: T001B 16 July page 5 of 14

6 a Benchmark application folder that contains the hello_world.c file. We will replace that hello_world.c file with a custom program that tests the HyperRAM device later in this tutorial a Benchmark_bsp folder that contains the Nios II Board Support Package (BSP) hardware abstraction layer (HAL) specifically for the Benchmark application. 4. Configure the Board Support Package (BSP) 4.1. The Nios II BSP must be configured before we can compile the source code In the Project Explorer tab, right click on: Benchmark_bsp Nios II BSP Editor 4.3. A BSP Editor window will open In the Main Tab of the BSP editor, in the panel on the left hand side, select: Settings Common 4.5. Set the sys_clk_timer field to timer_0 This is used to generate a recurring system clock interrupt for the hardware abstraction layer Set the timestamp_timer field to interval_timer This field is used to enable the hardware abstraction layer to perform fine precision event timing The Newlib ANSI C standard library can be configured as small or normal: Generally, when mapping code and data to on-chip memory: Tick the [x] enable_small_c_library field to reduce the size of the executable code generated by the hardware abstraction layer (HAL). Ticking this option also reduces the functionality and performance of the HAL. Please note that the inbuilt memset() and memcpy() routines will be very slow Generally, when mapping code and data to HyperRAM and/or HyperFlash: Untick the [ ] enable_small_c_library field to increase the functionality and performance of the executable code generated by the hardware abstraction layer (HAL). Please note that the inbuilt memset() and memcpy() routines will achieve relatively good performance. However, the executable code will be considerably larger due to other code that is included by the Newlib library In this tutorial, as we have more memory capacity available to store the.elf file. Therefore we recommend ensuring the [ ] enable_small_c_library field is Unticked to improve the performance results of the memcpy benchmarking software. T001B 16 July page 6 of 14

7 4.8. In the Main Tab of the BSP editor, in the panel on the left hand side, select: Settings Advanced hal 4.9. Then, in the panel on the right hand side, scroll down to find the hal.linker as illustrated below We will use the following configuration: Tick [x] allow_code_at_reset Tick [x] enable_alt_load Tick [x] enable_alt_load_copy_rodata Tick [x] enable_alt_load_copy_rwdata Tick [x] enable_alt_load_copy_exception Please Note: This specific configuration may not be the best configuration for your future project s needs. Please refer to Altera s documentation for detailed information on how to setup the hal.linker fields in the: T001B 16 July page 7 of 14

8 Generic Nios II Booting Methods User Guide, UG-20001, niosii_generic_booting_methods.pdf Select the Linker Script Tab of the BSP editor: In this tutorial, we are going to: Map the reset vector (.reset) to the onchip memory (onchip_memory2_0). This is generated by Qsys and depends on the location of the Nios II reset vector Map the exception vector (.exceptions) to the onchip memory (onchip_memory2_0). This is generated by Qsys and depends on the location of the Nios II exception vector Map the instruction code (.text) to the HyperRAM memory (sll_hyperbus_controller_top_0) Map all other data regions (.bss,.heap,.rodata,.rwdata,.stack) to the HyperRAM memory (sll_hyperbus_controller_top_0) For more information about linker sections in general, please see: Nios II Gen2 Software Developer's Handbook, NII5V2Gen2, Section 5, Nios II Software Build Tools n2sw_nii5v2gen2.pdf Click on the [ Exit ] button on the bottom right hand corner of the BSP Editor window Then click on the [ Yes, Save ] button on the Save Changes window to save the BSP settings. T001B 16 July page 8 of 14

9 5. Generate the BSP and clean the project 5.1. The software developer must regenerate the BSP every time the Qsys project is regenerated. This ensures that the device drivers and addresses of peripherals are reflected correctly in the hardware abstract library To (re)generate the BSP for the Benchmark application: Go to the Nios II eclipse window Right click on Benchmark_bsp project then select Nios II then select Generate BSP Right click on the Benchmark project then select Clean Project to delete any intermediate files generated by the gcc compiler for this application library Right click on the Benchmark_bsp project then select Clean Project to delete any intermediate files generated by the gcc compiler for this board support package folder. 6. Install the memory testing source code 6.1. We now want to replace the original HelloWorld.c source code with software that benchmarks Nios II software memory access performance to the HyperRAM Copy and replace the files located in: /source/testmbs to: /software/benchmark 6.3. In the project explorer window of Eclipse, right click on the Benchmark folder. Then select Refresh. The new source code files should now be visible within Eclipse. 7. Build the Nios II Application 7.1. We now want to run the C compiler and linker: Go to the Nios II eclipse window Right click on the Benchmark project, then select Build Project If the project produces warning / error messages, you may need to build the project twice The Benchmark executable firmware.elf is now generated This.ELF file can be downloaded directly into on-chip SRAM and off-chip SDRAM using the Nios II Debugger. T001B 16 July page 9 of 14

10 8. Program the FPGA Bitstream into the FPGA device 8.1. Ensure that the HyperMAX / Intel C10 LP Evaluation Kit board is connected to the USB port of your computer 8.2. Open the Quartus Prime window 8.3. To start the Altera Programmer, in the menu bar, select: Tools Programmer 8.4. If the HyperMAX/Intel C10LP Evaluation kit device is not already selected: Click on Hardware Setup A new window will open Double Click on the HyperMax (or Intel C10 LP Evaluation Kit) device Click the [ Close ] button If the NIOS_HyperRAM_time_limited.sof is not already selected: Click Add File... in the programmer window Go to the output_files folder Double click on NIOS_HyperRAM_time_limited.sof 8.6. On the left hand side of the Programmer window, click the [ Start ] button 8.7. The FPGA bitstream will now be programmed into the SRAM configuration memory of the FPGA device A window called OpenCore Plus Status should open. T001B 16 July page 10 of 14

11 9. Run the Benchmark from within Nios II SBT 9.1. Select the Nios II Software Built Tools for Eclipse window Right click on Benchmark. Then left click on Run As Run Configurations 9.3. A new window will open 9.4. Make sure the Name: field says Benchmark Nios II Hardware configuration T001B 16 July page 11 of 14

12 9.5. Select the Target Configuration tab Press the [ Refresh Connections ] button to detect the Nios II processor on the FPGA board PLEASE NOTE: Please ensure that [ ] Disable Nios II Console view is Unticked to enable the Nios II output to be displayed in the Nios II Console tab in the Nios II Eclipse environment; If [X] Disable Nios II Console view is Ticked you will have to use the nios2-terminal application to see the output of the Nios II core While not normally recommended in day-to-day design, in this tutorial you can optionally: Tick the [x] Ignore mismatched System ID field Tick the [x] Ignore mismatched System timestamp field By ticking these two fields, the Nios II Debugger will attempt to load the software, no matter what version of the Qsys project / FPGA bitstream has been loaded into the FPGA design In most projects, you typically want to the development tools to check the System ID and System timestamp to avoid accidentally loading new software into a FPGA device programmed with an older / incompatible FPGA bitstream Press the [ Run ] button located in the bottom right of the window. This will: Download the.elf firmware from the desktop and program the contents into the relevant volatile memories. In this case, it will program the on-chip memory; and the HyperRAM Boot the firmware from on-chip memory, and run software resident in the HyperRAM If the download does not work, please check that the static timing constraints of your project are passing The output of the Memory Bandwidth Benchmarking program should be displayed in the Nios II Console Window. It will look something like the screenshot below. T001B 16 July page 12 of 14

13 9.12. In this reference design, the 32-bit Nios II core is only running at 100 MHz. The Nios II is an in order execution core that can issue and retire at most one 32-bit OPCODE per clock cycle. The average memcpy() speed is around 19.5 to 24.5 Megabyte/s depending on the length of memory copied per memcpy invocation. This is a good result for this type of simple soft processor core when accessing external memories. Increasing the CPU clock speed, while keeping the HyperBus channel clock speed constant, will measurably increase the performance of the memcpy() result To achieve significantly higher memory throughput use a dedicated Direct Memory Addressing (DMA) module. For example, Intel s Modular Scatter Gather Direct Memory Access (MSGDMA) unit can sustain up to ~281 MegaBytes/s throughput from HyperRAM running at 150 MHz clock speed. T001B 16 July page 13 of 14

14 10. Obtaining good to excellent levels of effective memory bandwidth when using HyperBus devices The HyperBus protocol has a memory access performance behavior that is conceptually similar to operating DDRx SDRAM devices in closed page mode. (e.g. SDRAM PRECHARGE, ROW, COL, PRECHARGE, ) To obtain good performance, all bus-masters directly or indirectly accessing S/Labs HyperBus Memory Controller IP should employ a memory transfer requests with a burst length of 256-bits (8 x 32-bit words) or higher For this reason, please ensure that the Nios II/f instruction and data caches have burst mode enabled in all your HyperBus enabled designs Furthermore, S/Labs HBMC IP can sustain up to ~281 MegaBytes/s (MBps) on the 8-bit DDR HyperRAM channel running at 150 MHz with memory transfer requests with long bursts! Therefore we strongly recommend using large burst lengths where possible (e.g. by using Intel s MSGDMA module configured with bursts lengths that are larger than or equal to 16 words and less than or equal to 128 words where possible). T001B 16 July page 14 of 14