Introduction to Zynq

Size: px

Start display at page:

Download "Introduction to Zynq"

Marvin Crawford
6 years ago
Views:

Introduction to Zynq Lab 2 PS Config Part 1 Hello World

2 Table of Contents Table of Contents... 2 Lab 2 Objectives... 3 Experiment 1: Enable and map a Zynq PS UART peripheral... 3 Questions:... 7 Experiment 2: Configure Memory and Clocks for the Zynq PS... 8 Questions: Experiment 3: Build the hardware platform and export to SDK Experiment 4: Create and Run a Hello World application Questions: Exploring Further Revision History Resources Appendix Calculating DDR 3 PCB Lengths Questions: Answers Experiment Experiment Experiment Appendix Lab 2 : Page 2

Lab 2 Objectives When you have completed Lab 2, you will know how to do the following: Enable and map a Zynq PS UART peripheral Configure Memory and Clocks for the Zynq PS Build the hardware platform

3 Lab 2 Objectives When you have completed Lab 2, you will know how to do the following: Enable and map a Zynq PS UART peripheral Configure Memory and Clocks for the Zynq PS Build the hardware platform and export to SDK Create and run a Hello World application Experiment 1: Enable and map a Zynq PS UART peripheral At the conclusion of Lab 1, an ARM Processing System was added to the Embedded Source. The Zynq configuration tool became visible in the System Assembly View: Zynq tabs. We ll do something very simple in this step by enabling a single UART peripheral in the design and mapping it to the Multiplexed I/O (MIO). Figure 1 Zynq Hardware Configuration in XPS Lab 2 : Page 3

Experiment 1 General Instruction: Set the Bank voltages to LVCMOS 3.3V for Bank 0 and LVCMOS 1.8V for Bank 1. Enable the UART1 peripheral and map it to MIO[48:49].

4 Experiment 1 General Instruction: Set the Bank voltages to LVCMOS 3.3V for Bank 0 and LVCMOS 1.8V for Bank 1. Enable the UART1 peripheral and map it to MIO[48:49]. Experiment 1 Step-by-Step Instructions: The System Assembly View shows that no ARM peripherals or Flash Memory interface are currently enabled. You can determine this since all peripheral and flash boxes are grey, as shown in Figure 2. This also means that no MIOs are connected. Figure 2 No Peripherals Activated 1. Click anywhere on the peripherals. This opens the Zynq PS MIO Configurations dialog. 2. Select the check box for Show I/O Standard Options. 3. Set Bank 0 I/O Voltage to LVCMOS 3.3V and Bank 1 I/O Voltage to LVCMOS 1.8V. Click Yes to confirm. The Bank voltage decisions on ZedBoard were made based on the interfacing devices (QSPI, PHYs, etc.). At this time, nothing is selected. Note that the MIOs on the right are listed in numerical order. However, the peripherals on the left are not listed in alphabetical order. The peripherals are listed from top to bottom in order of priority based on either their importance in the system (like the Flash) or how limited they are in their possible MIO mappings. The least flexible are at the top, while the most flexible (GPIO) is at the bottom. Lab 2 : Page 4

However, to simplify this experiment, we will focus just on a single peripheral to show how the process works. 4.

5 Figure 3 Initial View of MIO Configuration When mapping out a board, a designer should start at the top of the list and work their way down. A developer has to carefully balance which peripherals will map to the MIO and which ones are mapped to EMIO. However, to simplify this experiment, we will focus just on a single peripheral to show how the process works. 4. There are two UARTs, check the box in front of UART1. Click the pull-down for the IO. Notice that UART1 can be placed on EMIO or a number of MIO locations. Figure 4 UART1 IO Mapping Options Lab 2 : Page 5

5. Map the UART1 to MIO[48-49]. Notice if you scroll down the MIO table on the right, UART 1 is now identified with MIO[48..49]. Figure 5 UART1 Mapped to MIO[48:49] 6.

Note that if you enable the Modem Signals by clicking the checkbox, they must go to EMIO.

6 5. Map the UART1 to MIO[48-49]. Notice if you scroll down the MIO table on the right, UART 1 is now identified with MIO[48..49]. Figure 5 UART1 Mapped to MIO[48:49] 6. Expand the UART1 options in the Peripheral table by clicking on the plus sign to the left of UART1. 7. Note that if you enable the Modem Signals by clicking the checkbox, they must go to EMIO. We don't need the Modem Signals now, so disable them by clicking the checkbox to clear the selection. 8. Click Close. Notice in the I/O Peripherals table that UART1 is now colored instead of grey, indicating that it is active. Figure 6 UART1 Peripheral Now Enabled Lab 2 : Page 6

7 Questions: Answer the following questions: How many MIOs are there for peripheral and Flash I/O mapping? What are the major differences between MIO and EMIO? Why are the Peripherals not listed alphabetically in the I/O Peripherals Configuration tool? Lab 2 : Page 7

8 Experiment 2: Configure Memory and Clocks for the Zynq PS A few critical Zynq PS elements must be configured before even a simple Hello World can be run. This includes the DDR3 memory, as it is the RAM that will execute the Zynq PS applications. Also, the system clocks must be configured correctly. Experiment 2 General Instruction: Use the Xilinx-provided memory timing spreadsheet to determine the proper parameters for the ZedBoard DDR3 delays. Configure the Memory GUI for a 32-bit interface using Micron MT41J128M16HA-15E components. Configure the clocks to operate the CPU at 667 MHz and the memory at 533 MHz. Experiment 2 Step-by-Step Instructions: 1. Click on the box for Clock Generation. Figure 7 PS Clock Generation Lab 2 : Page 8

9 2. Click on the icon to expand all the clocks. You should see the same view as shown in Figure 8. Figure 8 PS Clock Wizard Lab 2 : Page 9

Much on this screen works out by default to match ZedBoard. 3. Verify the following: o Input frequency is 33.33333 MHz o CPU frequency is 666.666666 MHz o DDR frequency is 533.

10 Much on this screen works out by default to match ZedBoard. 3. Verify the following: o Input frequency is MHz o CPU frequency is MHz o DDR frequency is MHz Figure 9 ZedBoard Clock Settings You may also notice that the UART IO Peripheral Clock is enabled, with the IO PLL assigned as the clock source. However, the UART Peripheral Clock is fixed at 100 MHz. 4. Click Validate Clocks to confirm clock settings then press OK. Next, we will configure the memory controller. 5. Click on the box labeled Memory Interfaces. Figure 10 Launch PS7 DDR Configuration Lab 2 : Page 10

The PS7 DDR Configuration screen allows for configuration of the DDR Controller, the Memory Part, and the board details used for DDR interface training.

11 The PS7 DDR Configuration screen allows for configuration of the DDR Controller, the Memory Part, and the board details used for DDR interface training. Figure 11 Default Settings for PS7 DDR Configuration 6. Make sure that the Enable DDR Controller box is checked and the Memory Type is assigned to the DDR 3 option. Figure 12 DDR3 Controller Enabled Lab 2 : Page 11

details specific to the selected memory device.

12 7. Select the MT41J128M16HA-15E option from the Memory Part drop-down menu. Figure 13 Select Micron MT41J128M16HA-15E Notice how the Memory Part Configuration section becomes grayed out and populated with details specific to the selected memory device. If your memory device of choice was not in the default catalog, you could select Custom. Then these boxes would be available for manually entering timing parameters for your selected device. Figure 14 Auto-populated Parameters for Micron DDR3 on ZedBoard Lab 2 : Page 12

8. In the DDR Controller Configuration section, the Effective DRAM Bus Width must be assigned to 32-bits since we are using a 2x16 DDR3 configuration.

13 8. In the DDR Controller Configuration section, the Effective DRAM Bus Width must be assigned to 32-bits since we are using a 2x16 DDR3 configuration. Since we are using DDR3 on a 7Z020 device, the ECC and Burst Length settings are predetermined. Notice also that the operating Frequency has automatically been inherited from the Clock Configuration screen to be 533 MHz. 9. Check the box for Internal Vref. The operating temperature can remain at the Normal (0-85) range. Figure 15 DDR Controller Configuration 10. Setting the Training/Board Detail parameters are next. DRAM Training must be enabled for Write leveling, Read gate, and Read data eye options. Check those 3 boxes now. An explanation of what these are is in the Zynq TRM, Section Notice there are four entries to allow for DQS to Clock Delay (ns) and Board Delay (ns) information to be specified for each of the four byte lanes. These numbers assist the training algorithm with a starting point inside the DDR3 data valid window. All delays by default start at Keep in mind the parameters for these fields are specific to each individual PCB design. The values are based on the PCB trace lengths and the specific Zynq package chosen. XPS already understands which package has been chosen, but the user must enter several values for the PCB trace lengths. Lab 2 : Page 13

Figure 16 DRAM Training Enabled, Default Delays are all 0.000 11.

Figure 17 Allow New Delay Values With 14.

14 Figure 16 DRAM Training Enabled, Default Delays are all Click to open the area for entering PCB trace lengths. Click Yes to continue. Figure 17 Allow New Delay Values With 14.1 tools, Xilinx Answer Record originally provided a spreadsheet for calculating these numbers. Starting in 14.2, you no longer need this spreadsheet, but the information in the AR may be useful, so it is included in the Support Documents for your reference. Lab 2 : Page 14

15 Here is a view of the Delay Calculation tool when first expanded. Notice that the tool already knows the Package Lengths. The Length (mm) column needs to be filled in with the PCB trace lengths for ZedBoard. Figure 18 Default Settings for 7Z020-CLG484 Notice that there are 4 byte groupings, each of which contains: CLK clock DQS strobe DQ 8 bits of data The procedure to calculate these lengths is included in Appendix Calculating DDR 3 PCB Lengths. If you have enough time after you finish the lab, complete the exercises there. However, in the interest of time, the Length numbers will be given to you now. 12. Fill in the 12 values for Length (mm) as shown in Figure 19. Figure 19 ZedBoard PCB Lengths Calculated and Entered 13. Collapse the worksheet area now by clicking. Lab 2 : Page 15

16 14. Compare with the completed settings shown below, and then click OK. Figure 20 PS7 DDR Configuration Complete Keep in mind for LPDDR2 there is no write leveling, and for DDR2 there is no training whatsoever. In these memory use cases, the accuracy of the trace length info is more important. This is covered in further detail in section of the TRM. 15. Close the XPS project by selecting File Exit. The active PlanAhead tool session updates with the project settings. Lab 2 : Page 16

17 Questions: Answer the following questions: Write leveling on Zynq-7000 is not supported for which two types of memory? The Read Data Eye DRAM Training option of Zynq-7000 is not available for which memory type? Lab 2 : Page 17

Experiment 3: Build the hardware platform and export to SDK A basic ARM hardware platform is now configured. The configuration includes clock and DDR controller settings.

18 Experiment 3: Build the hardware platform and export to SDK A basic ARM hardware platform is now configured. The configuration includes clock and DDR controller settings. It also enables and maps a UART peripheral. Now we ll build the hardware platform and export to the Software Development Kit (SDK) so that an application can be developed. Experiment 3 General Instruction: Add a top-level module for the design. Export the hardware to SDK. Experiment 3 Step-by-Step Instructions: 1. Expand Design Sources in the Sources pane, right-click system(system.xmp) and select Create Top HDL. Figure 21 Create Top HDL for Embedded System Lab 2 : Page 18

PlanAhead generates the system_stub.v top-level module for the design. Notice that the embedded system (system.xmp) is now a sub-module of system_stub. Figure 22 system_stub.

19 PlanAhead generates the system_stub.v top-level module for the design. Notice that the embedded system (system.xmp) is now a sub-module of system_stub. Figure 22 system_stub.v Generated and Added to Project 2. In the PlanAhead tool, select File Export Export Hardware for SDK The Export Hardware for SDK dialog box opens. By default, the Export Hardware check box is checked. Check the Launch SDK check box. Click OK. SDK now opens. The PlanAhead design tool exported the Hardware Platform Specification for your design (system.xml in this example) to SDK. In addition to system.xml, there are four more files exported to SDK. They are ps7_init.c, ps7_init.h, ps7_init.tcl, and ps7_init.html. The system.xml file opens by default when SDK launches. The address map of your system read from this file is shown by default in the SDK window. The ps7_init.c and ps7_init.h files contain the initialization code for the Zynq Processing System and initialization settings for DDR, clocks, plls, and MIOs. SDK uses these settings when initializing the processing system so that applications can be run on top of the processing system. Lab 2 : Page 19

20 Experiment 4: Create and Run a Hello World application In this experiment, you will use SDK to create and run a simple Hello World application. Experiment 4 General Instruction: Create the Standalone BSP. Generate and run the Hello World application. Experiment 4 Step-by-Step Instructions: 1. Select File New Xilinx Board Support Package. 2. Accept the default settings for the standalone BSP OS. Click Finish. Figure 23 Standalone BSP Lab 2 : Page 20

correct. Figure 24 stdin and stdout settings 4. Click Overview.

21 3. Click standalone. Note that the stdin and stdout are automatically set to the ps7_uart_1 peripheral, which is correct. Figure 24 stdin and stdout settings 4. Click Overview. No changes will be made to the BSP settings. None of the Supported Libraries are needed for this experiment. Click OK to accept the defaults and close this dialog. Figure 25 BSP Settings Lab 2 : Page 21

22 Based on the default settings in SDK, the BSP will automatically be built once added to the project. This take a minute to compile the new BSP. The standalone_bsp_0 is now visible in the Project Explorer. 5. Expand standalone_bsp_0 under the Project Explorer. Figure 26 BSP Added to the Project Lab 2 : Page 22

23 6. In SDK, select File New Xilinx C Project. 7. Select Hello World from the Select Project Template field. This will automatically change the default project name to hello_world_0, which is acceptable. Click Next >. Figure 27 New Xilinx C Project: Hello World Lab 2 : Page 23

24 8. Select the radio button for Target an existing Board Support Package. Since there is only one BSP in the project, the standalone_bsp_0 is automatically selected. Click Finish. Figure 28 Target the standalone_bsp_0 Lab 2 : Page 24

Notice that the hello_world_0 application is now visible in Project Explorer. By default, SDK will build the application automatically after it is added.

25 Notice that the hello_world_0 application is now visible in Project Explorer. By default, SDK will build the application automatically after it is added. C Software Application Board Support Package ARM Embedded Hardware Figure 29 Project Explorer View with Hello World C Application Added Figure 30 hello_world_0 Application Expanded Lab 2 : Page 25

26 Figure 31 Hello World Application Automatically Built 9. Connect the power cable to the ZedBoard. 10. Connect two micro-usb cables between the Windows Host machine and the ZedBoard connectors J17 (JTAG) and J14 (UART). 11. Set jumpers to Cascaded JTAG Mode MIO[6:2] = GND Figure 32 PLL Used, JTAG Boot, Cascaded JTAG: MIO[6:2] = Power on the ZedBoard. If this is the first time you've connected the Zedboard to this computer, you may see Windows install device drivers for the USB-UART and Digilent JTAG. Lab 2 : Page 26

13. Use Device Manager to determine the COM port for the Cypress USB-UART. In Windows 7, click Start Control Panel, and then click Device Manager. Click Yes to confirm. 14. Expand Ports.

27 13. Use Device Manager to determine the COM port for the Cypress USB-UART. In Windows 7, click Start Control Panel, and then click Device Manager. Click Yes to confirm. 14. Expand Ports. Note the COM port number for the Cypress Serial device. This example shows COM6. Figure 33 Find the COM port number for the Cypress Serial device 15. Right-click on the hello_world_0 application and select Run As Run Configurations 16. Select Xilinx C/C++ ELF and then click the New icon. 2 1 Figure 34 Create a New Xilinx C/C++ ELF Run Configuration Lab 2 : Page 27

Figure 35 New Run Configuration 17. Switch to the STDIO Connection tab. 18.

28 SDK creates the new Run Configuration and automatically assigns a name to the configuration <application_name> Debug, which in this case is hello_world_0 Debug. Figure 35 New Run Configuration 17. Switch to the STDIO Connection tab. 18. Check the box for Connect STDIO to Console. 19. Select the PORT for the Cypress USB-UART. 20. Set the BAUD Rate to Figure 36 STDIO Connection Lab 2 : Page 28

29 21. Click Apply and then Run. 22. The tools will now initialize the processor, download the hello_world.elf to DDR, and then run hello_world. This takes approximately seconds to complete, depending on the USB traffic in your system. You can follow the progress in the lower right corner of SDK. Figure 37 Launching hello_world Progress SDK will download the Hello World ELF to the DDR3 and the ARM begins executing the code. 23. Close SDK. Figure 38 Hello World Complete Lab 2 : Page 29

30 Questions: Answer the following questions: Does the Hello World C source include Zynq initialization? How did the Zynq get initialized in this Hello World experiment? Lab 2 : Page 30

31 Exploring Further If you have more time and would like to investigate more Explore the source and include code provided with Hello World. Complete Appendix Calculating DDR 3 PCB Lengths This concludes Lab 2. Revision History Date Version Revision 11 Oct Initial release for ISE Oct Emphasized UART Settings in PS Config Resources Lab 2 : Page 31

32 Appendix Calculating DDR 3 PCB Lengths Zynq allows for up to 4 memory devices to be configured for DDR3 4x8 fly-by topology. ZedBoard is configured for DDR3 2x16 fly-by topology. For a description of fly-by topology, see Micron TN Figures 1 and Figure 7 show the basic daisy-chain topology used for Command/Address/Control/Clocks. With the two DDR3 chips, the DQS s and DQ s are all point-to-point. Those values can easily be obtained from a simple trace length report. However, because of the fly-by routing, the CLK routing is daisy-chained. ZedBoard only has one DDR3 clock pair, which goes to IC26 first and then IC25. The CLK trace length in the report is going to be the total length. Getting the CLK2 and CLK3 lengths will be more challenging, and we ll have to open the layout to get this measurement. First, let s calculate the length values that we can easily get from a trace length report. 1. A trace length report for ZedBoard is provided in the support_documents folder. Open ZedBoard_RevB_PCB_Trace_Length_Report.txt now. All the DDR3 signals are prefixed in this report with DDR3- so these are easy to search. For differential pairs, calculate the average length of the P and N traces. For the data busses, calculate the average of the Minimum and Maximum values in the set. Each chip services two byte groups, so you ll find 16 DQ s and 2 DQS s per chip, but only one CLK. Therefore, the CLK lengths for byte groups 0 and 1 are the same; CLK2 and CLK3 are also the same. 2. Use the trace length report to calculate and then enter the trace lengths for CLK0, DQS0, and DQ[7:0]. Pin Group CLK0 DQS0 DQ[7:0] ZedBoard Traces Used in Calculation DDR3-CLK0_N, DDR3-CLK0_P DDR3-DQS0_N, DDR3-DQS0_P DDR3-D[7:0] Length (mm) Since CLK2 and CLK3 must be calculated differently, we ll look at them next. CLK2 is associated with Byte Group 2. CLK3 is associated with Byte Group 3. Byte Groups 2 and 3 are driven from IC26. Since traces DDR3-CLK0_P/N route daisy-chain first to IC26 and then IC25, the length to the trace segments between Zynq and IC26 must be measured manually. This must be done in Altium or Altium Viewer, which is the layout source for Lab 2 : Page 32

33 ZedBoard. To simplify this exercise, these trace segments were previously measured and screen captured. 3. Average these two trace segments and enter for CLK2 and CLK3. Figure 39 Trace Segment DDR3-CLK0_N = mm Figure 40 Trace Segment DDR3-CLK0_P = mm Lab 2 : Page 33

34 4. Calculate the remaining lengths in similar fashion. Enter these now. Pin Group Length (mm) CLK1 DQS1 DQS2 DQS3 DQ[15:8] DQ[23:16] DQ[31:24] The completed worksheet should appear as shown below. Figure 41 ZedBoard PCB Lengths Calculated and Entered Lab 2 : Page 34

35 Questions: Answer the following questions: In a multi-component memory design, how do you calculate the CLK trace length for the first component in the daisy chain? How do you calculate the trace length for a DQ byte group? Lab 2 : Page 35

36 Answers Experiment 1 How many MIOs are there for peripheral and Flash I/O mapping? 54 total What are the major differences between MIO and EMIO? MIOs tied to PS; limited in number; can be configured from ARM; can be used for first-stage boot devices; better timing for some things, like USB-ULPI EMIO tied to PL; more in number; must configure the PL with bitstream to use; more flexible for some things, like ethernet Why are the Peripherals not listed alphabetically in the I/O Peripherals Configuration tool? Peripherals are listed from top to bottom in priority order. The ones at the top should typically be picked first as they are the least flexible, have fixed pins, or are a boot device. Experiment 2 Write leveling on Zynq-7000 is not supported for which two types of memory? LPDDR2 and DDR2 The Read Data Eye DRAM Training option of Zynq-7000 is not available for which memory type? DDR2 Lab 2 : Page 36

37 Experiment 4 Does the Hello World C source include Zynq initialization? No How did the Zynq get initialized in this Hello World experiment? When you created the Run Configuration, there was a Device Initialization tab. Here there is a field to point to an initialization TCL file. This is set by default to the ps7_init.tcl file that was created as part of the Export to SDK. Inside this TCL, you will find a number of XMD commands that initialize all the registers exactly how you specified in XPS. Appendix Pin Group ZedBoard Traces to Average Length (mm) CLK0 DDR3-CLK0_N, DDR3-CLK0_P Average( , ) = mm DQS0 DQ[7:0] DDR3-DQS0_N, DDR3-DQS0_P DDR3-D[7:0] Average ( , ) = mm Min = Max = Avg = mm Lab 2 : Page 37

38 Pin Group Length (mm) CLK DQS DQS DQS DQ[15:8] DQ[23:16] DQ[31:24] In a multi-component memory design, how do you calculate the CLK trace length for the first component in the daisy chain? You must open the layout tool to find the trace lengths for clk_p and clk_n from the Zynq to that component. Then average the _p and _n lengths. How do you calculate the trace length for a DQ byte group? Find the minimum length and the maximum length out of the 8 traces then average them. Lab 2 : Page 38

MicroZed: Hello World. Overview. Objectives. 23 August 2013 Version 2013_2.01

MicroZed: Hello World. Overview. Objectives. 23 August 2013 Version 2013_2.01 23 August 2013 Version 2013_2.01 Overview Once a Zynq Hardware Platform is created and exported from Vivado, the next step is to create an application targeted at the platform and see it operating in hardware.