Commercial-Off-the-shelf Hardware Transactional Memory for Tolerating Transient Hardware Errors
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1 Commercial-Off-the-shelf Hardware Transactional Memory for Tolerating Transient Hardware Errors Rasha Faqeh TU- Dresden Dresden,
2 Transient Error Recovery Motivation Folie Nr. 12 von XYZ
3 Trend in silicon fabrication technology Microprocessor Feature size [Image Source: Advances in Solid Circuit Tech.] Folie Nr. 23 von XYZ
4 Transient Errors Vscale_H Vscale_M Vscale_L Nominal One failure per DAY per 100 chips One failure per MONTH per 100 chips [Image Source: Shoestring: probabilistic soft error reliability on the cheap, ASPLOS 2010] Folie Nr. 34 von XYZ
5 Transient Errors Vscale_H Vscale_M Vscale_L Nominal One failure per DAY per chip Aggressive voltage scaling (near-threshold computing) [Image Source: Shoestring: probabilistic soft error reliability on the cheap, ASPLOS 2010] Folie Nr. 35 von XYZ
6 Transient Errors Vscale_H Vscale_M Vscale_L Nominal One failure per DAY per chip With high error rates, reliability cannot be reserved only for mission-critical systems. One failure per MONTH per 100 chips There is a need for low-cost commodity solutions One failure per DAY per 100 chips Aggressive voltage scaling (near-threshold computing) [Image Source: Shoestring: probabilistic soft error reliability on the cheap, ASPLOS 2010] Folie Nr. 36 von XYZ
7 How to handle Transient Errors? Execution Error Detection Error Recovery Folie Nr. 47 von XYZ
8 How to handle Transient Errors? Execution Error Detection Error Recovery Folie Nr. 48 von XYZ
9 How to handle Transient Errors? Execution STOP Error Detection Error Recovery Folie Nr. 49 von XYZ
10 How to handle Transient Errors? Execution Replication Encoded Processing STOP Error Detection Error Recovery Folie Nr. 410 von XYZ
11 How to handle Transient Errors? Execution Execution Replication Encoded Processing STOP Error Detection Error Recovery Folie Nr. 411 von XYZ
12 How to handle Transient Errors? Replication Encoded Processing Execution STOP Execution ECC TMR Checkpoint/ Restarts Error Detection Error Recovery Folie Nr. 412 von XYZ
13 How to handle Transient Errors? Out Of Scope Replication Encoded Processing Execution STOP Execution ECC TMR Checkpoint/ Restarts Error Detection Error Recovery Folie Nr. 413 von XYZ
14 How to handle Transient Errors? Out Of Scope Checkpoint/Restarts Replication Encoded Processing Execution STOP Execution ECC TMR Checkpoint/ Restarts Error Detection Error Recovery Folie Nr. 414 von XYZ
15 Checkpoint/restarts using Transactional Memory Transaction 2 Application Tra ansaction 1 Folie Nr. 515 von XYZ
16 Checkpoint/restarts using Transactional Memory Error Detection Tx_start Transaction 2 Application Tra ansaction 1 Folie Nr. 516 von XYZ
17 Checkpoint/restarts using Transactional Memory Error Detection Tx_start Application Tra ansaction 1 Transaction 2 Tx_abort Tx_commit Folie Nr. 517 von XYZ
18 Checkpoint/restarts using Transactional Memory Error Detection Tx_start Transactional Memory Application Tra ansaction 1 Tx_abort Tx_commit Software: + Flexible Tx Size -Slow Hardware: + Low overhead -Limited Tx size Transaction 2 Folie Nr. 518 von XYZ
19 Checkpoint/restarts using Transactional Memory Error Detection Tx_start Transactional Memory Application Tra ansaction 1 Tx_abort Tx_commit Software: + Flexible Tx Size -Slow Reliability Hardware: + Low overhead -Limited Tx size Transaction 2 Example: Transactional Encoding (TE) Simulation: FaultTM Real HTM:?? Folie Nr. 519 von XYZ
20 Checkpoint/restarts using Transactional Memory Error Detection Tx_start Transactional Memory Application Tra ansaction 1 Transaction 2 Tx_abort Software: + Flexible Tx Size -Slow Using Commercial off the shelf HTM Tx_commit to tolerate Transient Errors? Example: Transactional Encoding (TE) Reliability Hardware: + Low overhead -Limited Tx size Simulation: FaultTM Real HTM:?? Folie Nr. 520 von XYZ
21 Transient Error Recovery Commercial off the shelf Hardware Transactional Memory Folie Nr. 621 von XYZ
22 HTM available in commodity processors Intel Haswell Transactional Synchronization Extensions (TSX) IBMPower8 : L2 private cache (512KB, 64 byte cache line) Reliability vs. Concurrency Transactions Concurrency Reliability Purpose of TX Parallelism Failure Atomicity Tx size Fixed Customizable Failure ConcurrencyConflicts Detectionof Reliability Errors Folie Nr. 722 von XYZ
23 Limitations- Features of COTS HTM Limitations: -COTS HTM are Best Effort Tx may always abort due to: - Capacity of transactional buffer (cache) - Faults and signals. -Not allowed Instructions retry Folie Nr. 823 von XYZ
24 Limitations- Features Limitations: -COTS HTM are Best Effort - Fixed Conflict Detection: Tx may always abort due to: - Capacity of transactional buffer (cache) - Faults and signals. -Not allowed Instructions retry Detected implicity by the hardware: - Automatically aborted by the hardware. No concurrent access to the same data Folie Nr. 824 von XYZ
25 Limitations- Features Limitations: -COTS HTM are Best Effort - Fixed Conflict Detection: Tx may always abort due to: - Capacity of transactional buffer (cache) - Faults and signals. -Not allowed Instructions retry Detected implicity by the hardware: - Automatically aborted by the hardware. No concurrent access to the same data Features: - Power8: suspend and resume mode: -Debug -Allows to externalize transactional state (read) before commit - ROT transactions: -No read-set -Track writes Folie Nr. 825 von XYZ
26 Evaluation COTS HTM Folie Nr. 26 von XYZ
27 Power8 Minimal Transaction cost: 20 cycles Cost vs size: No retry Folie Nr von XYZ
28 Power8: Spurious Aborts 7 Folie Nr. 128 von XYZ
29 Power8: Reason Spurious Aborts Folie Nr von XYZ
30 Power8: Restarts Spurious Aborts Folie Nr von XYZ
31 Power8: Cost of Restarts Spurious Aborts Folie Nr von XYZ
32 Summary -COTS HTM can be used to tolerate transient faults. -Need to find optimal transactional size that reduce the performance overhead and has high probability that it will commit. -Retry help to reduce the effect of spurious aborts. Folie Nr von XYZ
33 Q&A Folie Nr. 24/24 33 von XYZ
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