AS the digital design moves through increased levels of integration

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1 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL 52, NO 5, OCTOBER Parity Bit Signature in Response Data Compaction and Built-In Self-Testing of VLSI Circuits With Nonexhaustive Test Sets Sunil R Das, Fellow, IEEE, Made Sudarma, Mansour H Assaf, Member, IEEE, Emil M Petriu, Fellow, IEEE, Wen-Ben Jone, Senior Member, IEEE, Krishnendu Chakrabarty, Senior Member, IEEE, and Mehmet Şahinoğlu, Senior Member, IEEE Abstract The design of efficient time compression support hardware for built-in self-testing (BIST) is of great importance in the design and manufacture of VLSI circuits The test data outputs in BIST are ultimately compressed by the time compaction hardware, commonly called a response analyzer, into signatures Several output response compaction techniques to aid in the synthesis of such support circuits already exist in literature, and parity bit signature coupled with exhaustive testing is already well known to have certain very desirable properties in this context This paper reports new time compaction techniques utilizing the concept of parity bit signature that facilitates implementing such support circuits using nonexhaustive or compact test sets, with the primary objective of minimizing the storage requirements for the circuit under test (CUT) while maintaining the fault coverage information as best as possible Recently, Jone and Das proposed a multiple-output parity bit signature generation method extending the basic idea of Akers, for exhaustive testing of digital combinational circuits, where, given a multiple-output circuit, a parity bit signature is generated by first XORing all the outputs to produce a new output function and then feeding this resulting function to a single-output parity bit signature generator The method, as shown by the authors, preserves all the desirable properties of the conventional single-output response analyzers and can also be easily implemented by using the current VLSI technology The subject paper further augments the aforesaid concepts of Jone and Das, and proposes a multiple-output parity bit signature for nonexhaustive testing of VLSI circuits Design algorithms are proposed in the paper, and the simplicity and ease of their implementations are demonstrated with examples Extensive simulation experiments on ISCAS 85 combinational benchmark circuits using FSIM, ATALANTA, and COMPACTEST programs demonstrate that the proposed signature generation method achieves high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead A performance comparison of the designed time compactors with conventional space-time compaction is also presented to demonstrate improved tradeoff for the new circuits in terms of fault coverage and the CUT resources consumed contrasted with existing designs, and to appreciate the resulting performance enhancements Manuscript received December 15, 2002; revised June 29, 2003 This work was supported in part by the Natural Sciences and Engineering Research Council of Canada under Grant A 4750 S R Das, M Sudarma, M H Assaf, and E M Petriu are with the School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, ON K1N 6N5, Canada W-B Jone is with the Department of Electrical and Computer Engineering and Computer Science, University of Cincinnati, Cincinnati, OH USA K Chakrabarty is with the Department of Electrical and Computer Engineering, Duke University, Durham, NC USA M Şahinoğlu is with the Department of Computer and Information Science, Troy State University Montgomery, Montgomery, AL USA Digital Object Identifier /TIM Index Terms Built-in self-test (BIST), circuit under test (CUT), multiple-output parity bit signature generation, nonexhaustive or compact test sets, parity testing, space-time compaction, stuck-line faults, time compaction I INTRODUCTION AS the digital design moves through increased levels of integration densities, it is desirable that better and effective methods of testing be made available to ensure reliable systems operation Frankly speaking, the concept of testing has broad applicability, and as such, finding efficient testing techniques that guarantee correct systems performance has attracted considerable attention of the testing community for quite sometime [1] [32] The conventional testing techniques of digital systems require application of test stimuli generated by a test pattern generator (TPG) to the circuit under test (CUT) and subsequent comparison of the produced responses with known correct responses However, for large circuits, because of higher storage requirements for the fault-free responses, the procedure turns out to be rather expensive, and hence alternative approaches are sought Built-in self-testing (BIST) is a design approach that can significantly improve the testability of digital circuits and save testing time It combines concepts of both built-in test (BIT) and self-test (ST) in one termed built-in self-test (BIST) In BIST, test generation, test application, and response verification are all done through built-in hardware, which allows different parts of a chip to be tested in parallel, reducing the required testing time, besides eliminating the necessity for external test equipments A typical BIST environment, as shown in Fig 1, uses a test pattern generator (TPG) that sends its outputs to a circuit under test (CUT), and the resulting output streams from the CUT are fed into a response data analyzer A fault is detected if the CUT response is shown to be different from that of the fault-free circuit The test data analyzer is comprised of a response compaction unit (RCU), a storage for the fault-free responses of the CUT, and a comparator In order to reduce the amount of data represented by the fault-free and the faulty CUT responses, data compression is used to create signatures from the CUT and its corresponding fault-free circuit BIST techniques use pseudorandom, pseudoexhaustive, and exhaustive test patterns, or even sometimes on-chip storing of reduced test sets The standard response compaction unit is comprised of a space compression unit and /03$ IEEE

2 1364 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL 52, NO 5, OCTOBER 2003 Fig 1 BIST environment a time compression unit In general, responses coming out of a CUT are first fed into a space compressor, providing output streams such that Most often, test responses are compressed into only one sequence Space compression generates a solution to the problem of achieving high test quality for built-in self-testing of complex digital circuits without the requirement of monitoring a large number of internal test points, by merging test responses coming from the internal test points into a single bit stream, reducing in the process the test time and the resulting area overhead This single bit stream of length is eventually fed into a time compressor and a shorter sequence of length, is obtained at the output It is desirable that the extra logic representing the compaction circuit must be as simple as possible, to be easily embedded within the CUT, and should not introduce response delays to affect either the test execution time or normal functionality of the circuit Further, the length of the signature must be as short as possible in order to minimize the storage requirements of the fault-free responses [31], [32] In addition, signatures derived from the faulty CUT responses and their corresponding fault-free signatures should not be the same, which unfortunately is not always the case A fundamental problem with all compression techniques, in general, is error masking or aliasing [19], which occurs when the signatures from faulty output responses map into fault-free signatures Aliasing causes loss of information, which in turn affects the test quality of BIST, and thus reduces the overall fault coverage There exist several methods in the literature for computing the aliasing probability, of which the exact computation is known to be an NP-hard problem [33] The design of time-efficient support hardware for BIST is of crucial importance in the design and fabrication of modern VLSI circuits The test data outputs in BIST are ultimately compressed by the time compression hardware, commonly called a response analyzer, into signatures Several output response compaction techniques for the synthesis of such support circuits already exist in the literature, and parity bit signature coupled with exhaustive testing is already recognized to have certain very desirable properties in this context The subject paper presents time compression techniques based on parity bit signature to facilitate implementation of BIST support hardware using nonexhaustive (or compact) test sets, with the primary objective of minimizing the storage requirements for the CUT while maintaining the fault coverage information as much as possible Recently, Jone and Das proposed a multiple-output parity bit signature generation method extending the basic idea of Akers [14], for exhaustive testing of digital combinational circuits, where, given a multiple-output circuit, a parity bit signature is generated by first XORing all the outputs to produce a new output function and then feeding this resulting function to a single-output parity bit signature generator The method, as shown by the authors, preserves all the desirable properties of the conventional single-output response analyzers, and can also be easily implemented by using the current VLSI technology The present paper further augments the aforesaid concepts of Jone and Das, and proposes a multiple-output parity bit signature for nonexhaustive testing of VLSI circuits Design algorithms are proposed in the paper, and the simplicity and ease of their implementations are demonstrated with many examples Extensive simulation runs on ISCAS 85 combinational benchmark circuits using FSIM, ATALANTA, and COMPACTEST programs demonstrate that the proposed signature generation method achieves high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead The paper provides a performance comparison of the designed time compactors with conventional space-time compaction to demonstrate improved tradeoff for the new circuits between fault coverage and the CUT resources consumed in comparison with existing designs, in order to fully appreciate the resulting performance enhancements II TIME COMPACTION-BRIEF OVERVIEW In this section, we provide a brief overview of some of the time compaction methods that have been suggested in the literature and some of which are in actual use The well-known response compaction techniques include parity bit checking, transition count, one s count, Walsh coefficients, linear feedback shift register, parallel compaction analysis, etc Based on these approaches, the compressed response data can be used to evaluate the correctness of the CUT One s count was proposed by Hayes [6] and is given by the number of ones in the binary circuit response stream during test execution The hardware that represents the compaction unit consists of a simple counter, and is independent of the circuit under test It only depends on the nature of the test response The signatures values do not depend on the order in which the

3 DAS et al: PARITY BIT SIGNATURE IN RESPONSE DATA COMPACTION 1365 input test patterns are applied to the CUT The length of the signature is a logarithmic function of the length of the output response data Therefore, if the circuit response is of length bits, then its signature will be of length The probability distribution function of aliasing is approximately Gaussian with a mean value at, where being the length of the output stream The masking probability [26] is low when the one s count of the signature is near either the minimum or maximum of its length range Therefore, it takes a maximum value whenever the signature length approaches a maximum at the midrange of the count Syndrome testing [9] differs from the ordinary one s counting technique The syndrome testing requires application of patterns to be applied to an -input combinational circuit A fault can be detected by comparing the number of ones of the output signature to the number of ones of the previously stored fault-free signature In transition counting [7], on the other hand, the signature is the number of 0-to-1 or 1-to-0 transitions in the output bit stream The response-compression length is less than or equal to, where is the length of response stream The masking probability takes high values when the signature value is close to, and low values when it is close to 0 or In other words, masking in transition count depends on the number of faulty circuits that have the same transition count as the fault-free circuit Unlike one s counting, transition counting is sensitive to the order of the bits in the response vector However, transition counting does not guarantee the detection of all single-bit errors Double or multiple transition counting (DTC or MTC) [1], [2] has recently been proposed as a new compaction technique, which does not result in any loss of information Single-output circuits can be tested using DTC testing, while MTC testing is used for multi-output circuits DTC/MTC detects many faults that can also be detected by conventional testing methods However, DTC/MTC techniques do not require repeated input test patterns, and they do not use a counter Test circuitry consists of an inverter, a switch, an OR logic gate, and a D flip-flop Parity compaction [14] on the response bit stream is realized by compression of the output data to a signature of length of only one bit The value of this bit stream is 1 if the parity of the test response sequence is odd, and 0 if the parity is even Parity compaction detects all errors involving an odd number of bits, while faults that give rise to an even number of error bits are not detected This fact shows that parity checking is a relatively ineffective compaction method The hardware implementation consists of a flip-flop and an XOR gate Walsh spectral compaction method is similar to syndrome analysis, which requires all possible input patterns be applied to the combinational network In Walsh spectral analysis [10], the switching functions are represented by their spectral coefficients that are compared to known correct coefficient values Testing procedure checks the correctness of Walsh coefficients, which requires both an exhaustive and verification test of all Walsh coefficients The spectral coefficient guarantees higher percentage of error coverage of the tested circuit However, it also requires higher area overhead for generating them Testing using two different compaction schemes in parallel has been extensively investigated The combination of signature TABLE I SINGLE-OUTPUT PARITY BIT SIGNATURE analysis and transition counting has been analyzed [13] However, analysis shows that using simultaneously both techniques leads to a very small overlap in their error masking As a result, the fault coverage can be improved while the fault signature size and the hardware overhead are increased Cyclic redundancy check (CRC) is an alternative method to transition count testing and is more popular The CRC is easily implemented to detect errors in data communications The CRC requires little overhead and it has extreme error detection capabilities The CRC technique has been used for the compression of test response data [4] The residue that is left in the feedback shift register after the response from the circuit under test has been compressed is the signature In addition, one of its applications is as a source of pseudorandom binary test sequences, while the others are as means to carry out response compression This latter process is commonly known as signature analysis [8] Signature analysis is a compression technique based on the concept of cyclic redundancy checking (CRC) and realized in hardware using linear feedback shift registers (LFSRs), consisting of flip-flops and XOR gates Signature analysis currently is the most popular time compaction technique LFSRs are used for generating pseudorandom input test patterns, and for response compaction as well The nature of the generated sequence patterns is determined by the LFSR s characteristic polynomial as defined by its interconnection structure Response sequence is fed into the signature analyzer, and then divided by the characteristic polynomial of the signature analyzer s LFSR The remainder obtained by dividing by over a Galois field such that represents the state of the LFSR In other words, represents the observed signature The signature analysis involves comparing the observed signature to a known fault-free signature An error is detected if these two signatures differ from each other Suppose that is the correct response and is the faulty one,

4 1366 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL 52, NO 5, OCTOBER 2003 Fig 2 Implementation of an (n +1)-bit binary signature Fig 3 Two-level AND-OR combinational circuit where is an error polynomial It can be shown that aliasing occurs whenever is a multiple of or A method for computing and reducing the aliasing probability in signature analysis has been proposed by William et al [3], which uses Markov chains and derive an upper bound on the aliasing probability in terms of the test length and probability of an error occurring at the output of the CUT An approach to the computation of the aliasing probability is presented in [17] In addition, an error pattern in signature analysis causes aliasing, if and only if, it is a codeword in the cyclic code generated by the LFSR s characteristic polynomial Unlike other methods, the fault coverage in signature analysis may be improved without changing the test This process can be implemented by changing the length of the LFSRs or by using different characteristic polynomial As presented in [11], for short test lengths, signature analysis detects all single-bit errors However, there is no known theory that characterizes fault detection in signature analysis Multiple-output circuits can be tested [28] using multiple-input signature registers (MISRs) The use of MISRs in testing eliminates the need for a space compactor However, MISRs increase aliasing and require extra hardware, which make it far from being practical A new approach based on modification of the test response for reducing aliasing probability has been proposed by Zorian et al [19], [32] This method suffers from two drawbacks: it involves large hardware overhead and increases testing time without ensuring zero aliasing III SINGLE-OUTPUT PARITY BIT SIGNATURE Single-output parity bit signature is particularly well suited for exhaustive testing of digital circuits In built-in self-testing, the test output responses are compressed by the output response analyzer into a signature The advantages of using the exhaustive test set for self-testing have been widely discussed: test patterns can be easily generated, no fault models are required, and a high fault coverage can be achieved However, the disadvantage of exhaustive test patterns is their exponential number A Parity Bit Signature In this section, we will present some of the useful properties of single-output parity bit signature for exhaustive testing of digital circuits as widely discussed in literature Consider a fourvariable combinational switching function as defined by the truth table in Table I The parity bit signature of is given by a five-bit binary vector where and denoting the primary parity of the function, while representing the parity of the subfunction obtained by setting the th variable in equal to (0 or 1) as shown in Table I In general, given an -variable Boolean function, the parity bit signature of is given by an -bit vector where and denoting the primary parity of the function [15], with representing the parity of the subfunction obtained by setting the th variable in equal to 0

5 DAS et al: PARITY BIT SIGNATURE IN RESPONSE DATA COMPACTION 1367 TABLE II FAULT TABLE FOR THE DETECTION OF ALL SINGLE STUCK-AT FAULTS FOR THE CIRCUIT IN FIG 3 TABLE III FAULT-FREE SIGNATURE TABLE VI TABLE IV TABLE VII TABLE V TABLE VIII Based on the definition of the s above, it is evident that a total of parity bits are required in if the given function has input variables Fig 2 shows a straightforward implementation of this -bit binary signature in which the bit streams of interest are directed into T flip-flops The general case (with any number of primary inputs) of single-output parity bit signature can also be readily analyzed The parity bit signature as defined is a functional signature and is test-order independent This signature is also uniform as shown in [14] Given an -input arbitrary combinational function, the parity bit signature of is defined to be uniform since all of the possible -bit signatures are equally likely to result A parity bit signature is test-order independent since the order in which the test-inputs are generated has no effect on the signature TABLE IX B Basic Properties As mentioned above, an important property of the parity bit signature under exhaustive testing is its uniformity Given an arbitrary combinational function, all )-bit signatures are equally likely, thereby ensuring that the intrinsic lower bound on the error escape probability [14], [15] of is achieved

6 1368 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL 52, NO 5, OCTOBER 2003 TABLE X FAULT-FREE SIGNATURE TABLE XIII TABLE XI TABLE XIV TABLE XII TABLE XV In the following discussion, we present some of the basic properties of parity functions [14] that are relevant in the context of fault detection using single-output parity bit signature, and also multiple-output parity bit signature as discussed next Property 1: If a switching function of variables is independent of a variable, then its parity relative to will always be 0 Example: Consider a 3-variable function Now, can be expressed as This function is obviously independent of the variable and its parity Property 2: On the other hand, if a switching function of variables is a dependent function of all its variables, then its parity Property 3: If a switching function of variables is comprised of a single canonical product term or minterm, then its parity Example: Consider a function Its parity Property 4: If a switching function of variables is comprised of a single canonical sum of all its variables or a maxterm, then its parity Example: Consider a function ; then, in minterm form is given by Thus, Property 5: If a switching function of variables is specified as the XOR sum of all its variables, then its parity TABLE XVI Example: Consider a 3-variable function This function is an odd parity function and can be expressed as Obviously, its parity of is the complement of a function, then Property 6: If a switching function variables Example: Consider the 3-variable function Obviously, Property 7: If a switching function obtained by complementing a variable, then Property 8: If a switching function obtained by interchange of two variables, then, such that is of the function is of a function

7 DAS et al: PARITY BIT SIGNATURE IN RESPONSE DATA COMPACTION 1369 Fig 4 Proposed implementation of an (n +1)-bit multiple-output parity bit signature Property 9: Consider two switching functions of variables as and Then, the parity Example: Consider two 3-variable functions as and Then TABLE XVII MULTIPLE-OUTPUT PARITY BIT SIGNATURE Now, Property 10: Consider two switching functions of variables as and Then Example: Consider two 3-variable functions as and Then Property 11: Consider two switching functions, one of variables and another of variables Then, Property 12: Similarly, for the two functions and in Property 11 above, Property 13: Consider a switching function of variables Then, the parity of, where and are, respectively, the subfunctions obtained by setting its th variable equal to 0 and 1 Property 14: Consider a switching function of variables Then the parity of, where are, respectively, the reduced functions obtained by expanding about the variables The last property (Property 14) only states that if we form the Boolean difference of a function with respect to one of its variables, then If we repeatedly differentiate a function with respect to its variables, then the resulting th Boolean difference (which is 1 or 0) will be equal to Many of the aforesaid properties of the parity bit and parity bit signature for exhaustive testing are still valid when we use nonexhaustive testing Consider the following example as an illustration Example: Consider the irredundant two-level AND-OR circuit as given in Fig 3 The output function (fault-free) realized by the circuit is The fault table for the detection of all single faults of the circuit (excluding

8 1370 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL 52, NO 5, OCTOBER 2003 Fig 5 Detecting all single stuck-line faults of ISCAS 85 benchmark circuit c17 the faults on the primary output line) is depicted in Table II In this table, denotes the output function of the faultless version of the circuit and is the output when the th line is stuck-at- ( or ) From an inspection of the table, we identify the following groups of indistinguishable or equivalent faults We combine them, choose one function from each group, and delete the rest of them from the table We name the six distinguishable faults as, and, where It can be shown that the test set is a minimal complete test set of this circuit for the detection of all single distinguishable faults We now investigate if the faults could be detected using the parity bit signature if we subject the circuit to the above set of compact tests under condition of no faults and all single stuck-line faults Tables III IX show the fault-free signature and all the faulty signatures corresponding to the application of the test set Comparing the fault-free signature with all the faulty signatures, and, we see that all the six faults are detectable, which is to be expected since the compact test set chosen is a minimal complete test set of the circuit If the compact test set is not properly chosen (in the sense that it might not exercise all the detectable faults of the circuit), some faults may remain undetected Consider now another test set being applied to the circuit, viz, Tables X XVI show the fault-free signature and all the faulty signatures corresponding to the application of the test set Comparing the fault-free signature with all the faulty signatures, and, we see that many of the faults are not detectable A generalized algorithm is now given below to generate the single-output parity bit signature, given any single-output combinational circuit Algorithm 1: Step 1) Given an -input single-output combinational circuit with input variables, with output, and a given set of test-input combinations, record the input combinations for which the function output and Step 2) Generate all the subfunctions by setting, respectively, the variables to 0 To obtain a subfunction for any variable, check only the rows of test-input combinations with, and accordingly set the corresponding subfunction column (comprised of 0s and 1s) Step 3) Get the fault-free signature a) To get, take XOR sum of all 0s and 1s in the column of b) To get, take XOR sum of all 0s and 1s in the column of Step 4) Repeat Steps 1) 3) for all single-line faults Step 5) Compare the fault-free signature (fault-free) with all the faulty signatures (faulty) Take the bitwise XOR sum of the fault-free signature with each of the faulty signatures a) If for any equals 0, then the fault is not detected b) If for any equals 1, then the fault is detected Stop IV MULTIPLE-OUTPUT PARITY BIT SIGNATURE Obviously, the simplest strategy to extend the single-output parity bit signature to the multiple-output case is to generate a separate signature for each output An excessive amount of hardware overhead makes such an approach impractical Given an -input combinational circuit with outputs as shown in Fig 4, a multiple-output parity bit

9 DAS et al: PARITY BIT SIGNATURE IN RESPONSE DATA COMPACTION 1371 TABLE XVIII FAULT-FREE SIGNATURE TABLE XXI TABLE XIX TABLE XXII TABLE XX TABLE XXIII signature can be generated by first XORing all the outputs to produce a new output and then feeding this new output to a single-output parity bit signature generator This signature can be represented as a binary vector as Table XVII is an example of multiple-output parity bit signature generation It was shown in [14], [15] that the proposed method of signature generation under exhaustive testing evidently makes the signature test-order independent The uniformity property of the signature similarly holds for the general case of multiple-output functions, and is proved in [15] using a shorter and more elegant method based on linear algebraic techniques and properties of GF(2), and is omitted here [16] In this paper we investigate the possibility of detecting all single stuck-line faults in digital circuits by using parity bit signature not coupled with an exhaustive set of tests, but rather, nonexhaustive set of tests Before we explore the feasibility of such an approach in general, let us first demonstrate if some of the earlier discussed desirable properties of such a signature will still be valid while using nonexhaustive set of tests These are discussed below in the form of properties and theorem Property 15: A parity bit signature (single-output or multiple-output) in the context of nonexhaustive testing of digital circuits is a functional signature This is obvious since irrespective of whether we use exhaustive or nonexhaustive testing, the signature remains independent of the particular implementation involved Property 16: A parity bit signature (single-output or multiple-output) in the context of nonexhaustive testing of digital circuits is test-order independent The order in which the independent tests in the compact test sets are generated and applied has no effect on the signature Property 17: A parity bit signature (single-output or multiple-output) in the context of nonexhaustive testing of digital circuits is easily implementable and can be shown to be effective for single fault detection The property evidently follows based on the properties of parity bit signature and also of parity bits as discussed earlier Theorem 1: A parity bit signature (single-output or multipleoutput) in the context of nonexhaustive testing of digital circuits is obviously not uniform in the sense that given any arbitrary combinational switching function, all signature bit patterns in are not equally likely to result Proof: Since the different sin are each derived not on exhaustive application of all the input combinations or ordered -tuples, it follows rather obviously that the th parity bit in cannot be equal to 0 or 1 with equal probability, thus providing a signature which is not uniform, a property unfortunately shared by many counting techniques

10 1372 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL 52, NO 5, OCTOBER 2003 TABLE XXIV TABLE XXVII TABLE XXV TABLE XXVIII TABLE XXVI TABLE XXIX Let us first illustrate the feasibility of the proposed approach considering the following example Example: The circuit in Fig 5 is the first circuit c17 of the ISCAS 85 combinational benchmark circuits We obtain a single output from this circuit by XORing its two outputs and Table XXX is the fault table for the detection of all single faults of the circuit at the output (faults on lines, and are not considered) when all the input patterns are applied In this table, denotes the output function of the faultless version of the circuit and is the output when the th line is stuck-at- ( or ) From an inspection of the table, we identify the following groups of indistinguishable or equivalent faults: guishable faults as, and, where We combine them, choose one function from each group, and delete the rest of them from the table We name the 11 distin- It can be shown that the test set is a minimal complete test set of this circuit for the detection of all single distinguishable faults We now investigate if the faults could be detected using the parity bit signature if we subject the circuit to the above set of compact tests under condition of no faults and all single stuck-line faults Tables XVIII XXIX show the fault-free signature and all the faulty signatures corresponding to the application of the test set Comparing the fault-free signature with all the faulty signatures

11 DAS et al: PARITY BIT SIGNATURE IN RESPONSE DATA COMPACTION 1373 TABLE XXX FAULT TABLE FOR THE DETECTION OF ALL SINGLE STUCK-AT FAULTS OF THE CIRCUIT IN FIG 5, and, we observe that all the 11 faults are detectable, which is to be expected since the compact test set chosen is a minimal complete test set of the circuit An algorithm for the implementation of the proposed multiple-output parity bit signature generation is provided next Algorithm 2: Step 1) Given an -input -output combinational circuit with input variables, with outputs, combine the outputs by an XOR gate to produce a single output

12 1374 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL 52, NO 5, OCTOBER 2003 TABLE XXXI SIMULATION RESULTS OF THE ISCAS 85 BENCHMARK CIRCUITS USING ATALANTA SIMULATOR WITH NO ADDITIONAL CIRCUIT AT THE OUTPUTS TABLE XXXIV FAULT LOSS OF THE ISCAS 85 BENCHMARK CIRCUITS PROVIDED BY ATALANTA SIMULATOR DUE TO OUTPUT MERGER BY XOR GATE TABLE XXXII SIMULATION RESULTS OF THE ISCAS 85 BENCHMARK CIRCUITS USING FSIM SIMULATOR WITH NO ADDITIONAL CIRCUIT AT THE OUTPUTS TABLE XXXV FAULT LOSS OF THE ISCAS 85 BENCHMARK CIRCUITS PROVIDED BY FSIM SIMULATOR DUE TO OUTPUT MERGER BY XOR GATE TABLE XXXIII SIMULATION RESULTS OF THE ISCAS 85 BENCHMARK CIRCUITS USING COMPACTEST SIMULATOR WITH NO ADDITIONAL CIRCUIT AT THE OUTPUTS Step 2) Given a set of test-input combinations, record the input combinations for which the function output and Step 3) Generate all the subfunctions by setting, respectively, the variables to 0 To obtain a subfunction for any variable, check only the rows of test-input combinations with, and accordingly set the corresponding subfunction column (comprised of 0s and 1s) Step 4) Get the fault-free signature a) To get, take XOR sum of all 0s and 1s in the column of b) To get, take XOR sum of all 0s and 1s in the column of Step 5) Repeat Steps 2) 4) for all single-line faults Step 6) Compare the fault-free signature (fault-free) with all the faulty signatures (faulty) Take the bitwise XOR sum of the fault-free signature with each of the faulty signatures a) If for any equals 0, then the fault is not detected b) If for any equals 1, then the fault is detected Stop V SIMULATION RESULTS In our simulation experiments, as mentioned above, we used ISCAS 85 combinational benchmark circuits in order to demonstrate the feasibility of the proposed multiple-output signature generation for time compaction using nonexhaustive test sets The independent simulations were conducted on all ISCAS 85 combinational benchmark circuits using

13 DAS et al: PARITY BIT SIGNATURE IN RESPONSE DATA COMPACTION 1375 TABLE XXXVI FAULT LOSS OF THE ISCAS 85 BENCHMARK CIRCUITS PROVIDED BY COMPACTEST SIMULATOR DUE TO OUTPUT MERGER BY XOR GATE TABLE XXXIX FAULT LOSS OF THE ISCAS 85 BENCHMARK CIRCUITS USING ATALANTA/FSIM SIMULATOR FOR TIME COMPACTION TABLE XXXVII SIMULATION RESULTS OF THE ISCAS 85 BENCHMARK CIRCUITS USING ATALANTA/FSIM SIMULATOR WITH TIME COMPACTION TABLE XL FAULT LOSS OF THE ISCAS 85 BENCHMARK CIRCUITS USING COMPACTEST SIMULATOR FOR TIME COMPACTION TABLE XLI HARDWARE OVERHEAD ESTIMATES TABLE XXXVIII SIMULATION RESULTS OF THE ISCAS 85 BENCHMARK CIRCUITS USING COMPACTEST SIMULATOR FOR TIME COMPACTION ATALANTA, FSIM, and COMPACTEST simulators The ATALANTA [34] was used to generate the fault-free output streams required to construct the CUT signatures and to test the benchmark circuits using reduced or compact test sets FSIM [35] was used as a fault simulation program to generate pseudorandom test sets for testing the benchmark circuits The COMPACTEST [36] program was used to generate the reduced test sets that detect most detectable single stuck-line faults for all benchmark circuits The ATALANTA and FSIM programs were simulated on a SUN SPARC 5 workstation, while the COMPACTEST program was implemented on an IBM AIX machine For each ISCAS 85 combinational benchmark circuit, we determined the number of test vectors used to construct the required signatures, CPU simulation time taken for the construction, together with the percentage fault coverage The fault coverage was first computed at the output of the benchmark circuits alone without any additional circuits, next when the circuit outputs were merged by XOR gate, and was finally computed when the XOR gate output was fed to a parity bit signature generator, that is, at the output of the CUT together with the compression network The combination of these simulation results provides a clearer picture

14 1376 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL 52, NO 5, OCTOBER 2003 TABLE XLII FAULT-FREE AND FAULTY SIGNATURES FOR c432 BENCHMARK CIRCUIT USING ATALANTA/FSIM SIMULATOR WITH TIME COMPACTION TABLE XLIII FAULT-FREE AND FAULTY SIGNATURES FOR c432 BENCHMARK CIRCUIT USING COMPACTEST SIMULATOR WITH TIME COMPACTION in determining the fault loss introduced by the XOR gate, and multiple-output parity bit signature generator which includes the XOR gate as part of its overall hardware The area overhead introduced by the multiple-output signature generator for all simulated benchmark circuits using ATALANTA, FSIM, and COMPACTEST was determined as well The experimental results are summarized in the following sets of tables Tables XXXI XXXIII show the results of simulation on the ISCAS 85 benchmark circuits using ATALANTA, FSIM, and COMPACTEST simulators, respectively, with no additional circuits at the outputs From these results we see that ATALANTA and COMPACTEST provide almost similar fault coverage results for all the benchmark circuits, being much higher than the corresponding values provided by FSIM, while COMPACTEST provides the highest CPU simulation time for all the circuits except c17 Tables XXXIV XXXVI, on the other hand, show the simulation results on the ISCAS circuits using ATALANTA, FSIM, and COMPACTEST simulators, respectively, when the outputs of each circuit are merged by an XOR gate Here, as is evident, ATALANTA and COMPACTEST provide best results in terms of fault coverage compared to FSIM; fault loss due to merger by XOR gate is also computed in these tables Tables XXXVII and XXXVIII provide results on simulation using, respectively, ATALANTA/FSIM and COMPACTEST with time compression (viz XOR gate followed by parity bit signature generator), while Tables XXXIX and XL show the corresponding fault loss values, respectively, for ATALANTA/FSIM and COMPACTEST From the experimental results, we might conclude that time compaction results in better CPU simulation time in general Also, in all cases, we obtained lower fault coverage for the circuits, which is to be expected The hardware overhead estimates for all the ISCAS 85 benchmark circuits are given in Table XLI The estimates were found to be as small as 07 73% in most cases, with a value of 143% for the c17 benchmark circuit only A Fault-Free and Faulty Signatures for Circuit c432 Tables XLII and XLIII provide the fault-free signature as well as faulty signatures for the second benchmark circuit c432 comprised of 160 gates, 36 primary inputs, and seven primary outputs while using, respectively, ATALANTA/FSIM and COM- PACTEST In the simulation experiment, we use one XOR gate

15 DAS et al: PARITY BIT SIGNATURE IN RESPONSE DATA COMPACTION 1377 TABLE XLIV SIMULATION RESULTS OF THE ISCAS 85 BENCHMARK CIRCUITS USING ATALANTA/FSIM SIMULATOR FOR SPACE-TIME COMPACTION TABLE XLVI FAULT LOSS OF THE ISCAS 85 BENCHMARK CIRCUITS USING ATALANTA/FSIM SIMULATOR FOR SPACE-TIME COMPACTION TABLE XLV SIMULATION RESULTS OF THE ISCAS 85 BENCHMARK CIRCUITS USING COMPACTEST SIMULATOR FOR SPACE-TIME COMPACTION TABLE XLVII FAULT LOSS OF THE ISCAS 85 BENCHMARK CIRCUITS USING COMPACTEST SIMULATOR FOR SPACE-TIME COMPACTION to merge all the outputs of the circuit to a single output However, for large circuits such as c2670, c7552, we use more than one XOR gate to group two, three, or four outputs for merger at one time VI SPACE-TIME COMPACTION Instead of using only time compaction for the multiple-output circuits (that is, multiple-output parity bit signature generator), it is also possible to first use space compression which is ultimately followed by time compaction In the present section, we discuss the outcomes of such experimentation on ISCAS 85 benchmark circuits In our experimentation, we carry out the design of space compressors for the ISCAS 85 benchmark circuits following the optimal mergeability criteria as developed in [32] to merge suitable sets of candidate outputs of the benchmark circuits to single outputs and then use parity bit time compaction The details for the design of such space compressors comprised of AND (NAND), OR (NOR), and XOR (XNOR) gates, in general, could be found in [29] [32] and are thus omitted here The results of simulation on ISCAS 85 benchmark circuits using this kind of space-time compaction are given in Tables XLIV XLVII, using ATALANTA/FSIM and COMPACTEST, respectively These results are evidently self-explanatory VII CONCLUDING REMARKS The implementation of time-efficient BIST support hardware is of great importance in the synthesis of complex digital integrated circuits This paper reports on developing compression techniques of test data outputs for digital integrated circuits that facilitate the design of such time-efficient BIST support hardware using compact test sets Specifically, extending the concept of multiple-output parity bit signature generation as suggested for exhaustive testing of VLSI circuits recently by Jone and Das [15], the subject paper proposes a multiple-output parity bit signature generation method for use with nonexhaustive or compact test sets in testing digital integrated circuits The suggested compaction technique, as evidenced by extensive simulation experiments on ISCAS 85 combinational benchmark circuits using fault simulation programs FSIM, ATALANTA, and COMPACTEST, provides a high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead for the compactor As is obvious, the design of zero-aliasing compressors was not our priority; we rather endeavored in the paper to reinforce the connection between the input test sets, their lengths, and their reduction into recommended algorithms in the construction of the compaction trees Information loss [37] may not be completely avoided when the size of all output responses is reduced Therefore, depending on the amount of information loss, the corresponding time compactor design will be affected as well In our design experiments, we used the reduced test sets provided by ATALANTA

16 1378 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL 52, NO 5, OCTOBER 2003 and COMPACTEST to simulate all the ISCAS 85 combinational benchmark circuits Even though these reduced input test sets are not the minimal test sets needed to ensure a 100% fault coverage, experimental results indicate that our designed multiple-output parity bit signature generators are comparable in all respects with conventional space-time compression, usually considered ideal for multiple-output combinational circuits REFERENCES [1] P H Bardell, W H McAnney, and J Savir, Built-In Test for VLSI: Pseudorandom Technique New York: Wiley, 1987 [2] S Mourad and Y Zorian, Principles of Testing Electronic Systems New York: Wiley, 2000 [3] T W Williams and K P Parker, Testing logic networks and design for testability, Computer, vol 21, pp 9 21, Oct 1979 [4] E J McCluskey, Built-in self-test techniques, IEEE Design Test Comput, vol 2, pp 21 28, Apr 1985 [5] R G Daniels and W B Bruce, Built-in self-test trends in Motorola microprocessors, IEEE Design Test Comput, vol 2, pp 64 71, Apr 1985 [6] J P Hayes, Check sum methods for test data compression, J Design Automat Fault-Tolerant Comput, vol 1, pp 3 7, Jan 1976 [7], Transition count testing of combinational logic circuits, IEEE Trans Comput, vol C-25, pp , June 1976 [8] R A Frohwerk, Signature analysis A new digital field service method, Hewlett-Packard J, vol 28, pp 2 8, May 1977 [9] J Savir, Syndrome-testable design of combinational circuits, IEEE Trans Comput, vol C-29, pp , June 1980 [10] A K Susskind, Testing by verifying Walsh coefficients, IEEE Trans Comput, vol C-32, pp , Feb 1983 [11] N R Saxena and J P Robinson, A unified view of test response compression methods, IEEE Trans Comput, vol C-36, pp 94 99, Jan 1987 [12] T W Williams, W Daehn, M Gruetzner, and C W Starke, Aliasing errors in signature analysis registers, IEEE Design Test Comput, vol 4, pp 39 45, Apr 1987 [13] N R Saxena and J P Robinson, Syndrome and transition count are uncorrelated, IEEE Trans Inform Theory, vol 34, pp 64 69, Jan 1988 [14] S B Akers, A parity bit signature for exhaustive testing, IEEE Trans Comput Aided Design, vol 7, pp , Mar 1988 [15] W B Jone and S R Das, Multiple-output parity bit signature for exhaustive testing, J Electron Testing: Theory Applicat, vol 1, pp , Mar 1990 [16] N S Khabra and S R Das, Multiform partial symmetry and parity functions, IEEE Trans Comput, vol C-22, p 804, Aug 1973 [17] D K Pradhan and S K Gupta, A new framework for designing and analyzing BIST techniques and zero aliasing compression, IEEE Trans Comput, vol C-40, pp , June 1991 [18] K Chakrabarty and J P Hayes, Cumulative balance testing of logic circuits, IEEE Trans VLSI Syst, vol 3, pp 72 83, Mar 1995 [19] K Chakrabarty, Test Response Compaction for Built In Self Testing, PhD Dissertation, Dept Computer Science and Engineering, Univ of Michigan, Ann Arbor, MI, 1995 [20] K K Saluja and M Karpovsky, Testing computer hardware through compression in space and time, in Proc Int Test Conf, 1983, pp [21] Y Zorian and V K Agarwal, A general scheme to optimize error masking in built-in self testing, in Proc Int Symp Fault-Tolerant Comput, 1986, pp [22] Y K Li and J P Robinson, Space compression method with output data modification, IEEE Trans Comput Aided Design, vol 6, pp , Mar 1987 [23] S M Reddy, K K Saluja, and M G Karpovsky, Data compression technique for test responses, IEEE Trans Comput, vol C-37, pp , Sept 1988 [24] M Karpovsky and P Nagvajara, Optimal robust compression of test responses, IEEE Trans Comput, vol C-39, pp , Jan 1990 [25] W-B Jone and S R Das, Space compression method for built-in selftesting of VLSI circuits, Int J Comput Aided VLSI Design, vol 3, pp , Sept 1991 [26] S R Das, H T Ho, W B Jone, and A R Nayak, An improved output compaction technique for built-in self-test in VLSI circuits, in Proc Int Conf VLSI Design, 1994, pp [27] K Chakrabarty and J P Hayes, Efficient test response compression for multiple-output circuits, in Proc Int Test Conf, 1994, pp [28] J Savir, Reducing the MISR size, IEEE Trans Comput, vol C-45, pp , Aug 1996 [29] S R Das, E M Petriu, T Barakat, M H Assaf, and A R Nayak, Space compaction under generalized mergeability, IEEE Trans Instrum Meas, vol 47, pp , Oct 1998 [30] S R Das, T F Barakat, E M Petriu, M H Assaf, and K Chakrabarty, Space compression revisited, IEEE Trans Instrum Meas, vol 49, pp , June 2000 [31] J Y Liang, Response Data Compaction in BIST Under Generalized Mergeability Based on Switching Theory Formulation and Utilizing a New Measure of Failure Probability, MASc Thesis, School of Information Technology and Engineering, Univ of Ottawa, Ottawa, ON, Canada, Sept 2000 [32] S R Das, C V Ramamoorthy, M H Assaf, E M Petriu, and W-B Jone, Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities, IEEE Trans Instrum Meas, vol 50, pp , Dec 2001 [33] M R Garey and D S Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness New York: W H Freeman, 1979 [34] H K Lee and D S Ha, On the Generation of Test Patterns for Combinational Circuits, Dept Electrical Engineering, Virginia Polytechnic Institute and State Univ, Blacksburg, VA, Tech Rep 12-93, 1993 [35], An efficient forward fault simulation algorithm based on the parallel pattern single fault propagation, in Proc Int Test Conf, 1991, pp [36] I Pomeranz, L N Reddy, and S M Reddy, COMPACTEST: A method to generate compact test sets for combinational circuits, in Proc Int Test Conf, 1991, pp [37] M Şahinoğlu, C Bayrak, and T Cummings, High assurance software testing in business and DoD, Trans Soc Design Process Sci, vol 6, pp , June 2002 Sunil R Das (M 70 SM 90 F 94) received the BSc (Honors) degree in physics and the MSc (Tech) and PhD degrees in radiophysics and electronics from the University of Calcutta, Calcutta, West Bengal, India He is a Professor of Electrical and Computer Engineering at the School of Information Technology and Engineering, University of Ottawa, Ottawa, ON, Canada He previously held academic and research positions with the Department of Electrical Engineering and Computer Sciences, Computer Science Division, University of California, Berkeley, the Center for Reliable Computing (CRC), Computer Systems Laboratory, Department of Electrical Engineering, Stanford University, Stanford, CA (on sabbatical leave), the Institute of Computer Engineering, National Chiao Tung University, Hsinchu, Taiwan, ROC, and the Center of Advanced Study (CAS), Institute of Radiophysics and Electronics, University of Calcutta He has published extensibly in the areas of switching and automata theory, digital logic design, threshold logic, fault-tolerant computing, microprogramming and microarchitecture, microcode optimization, applied theory of graphs, and combinatorics He has edited, jointly with P K Srimani, a book entitled Distributed Mutual Exclusion Algorithms (Los Alamitos, CA: IEEE Computer Society Press, 1992) He is coauthor, with C L Sheng, of a text on digital logic design, being published by Ablex Publishing Corporation He is an Associate Editor of the International Journal of Parallel and Distributed Systems and Networks published by Acta Press, Calgary, AB, Canada, and a member of the Editorial Board and a Regional Editor for Canada of VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing published by Gordon and Breach Science Publishers, Inc, NY He is a former Associate Editor of the SIGDA Newsletter, the publication of the ACM Special Interest Group on Design Automation, and a former Associate Editor of the International Journal of Computer Aided VLSI Design published by Ablex Publishing Corporation, Norwood, NJ He was also Guest Editor of the International Journal of Computer Aided VLSI Design (September 1991) as well as VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing for the March 1993, September 1996, and December 2001 Special Issues on VLSI Testing

17 DAS et al: PARITY BIT SIGNATURE IN RESPONSE DATA COMPACTION 1379 Dr Das has served as the Managing Editor of the IEEE VLSI Technical Bulletin, a publication of the IEEE Computer Society Technical Committee (TC) on VLSI, and also as an Executive Committee Member of the IEEE Computer Society Technical Committee (TC) on VLSI He is currently an Associate Editor of the IEEE TRANSACTIONS ON SYSTEMS, MAN, AND CYBERNETICS (now of Part A, Part B, and Part C) and the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT He is a former Administrative Committee (ADCOM) Member of the IEEE Systems, Man, and Cybernetics Society and a former Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS (for two consecutive terms) He has served on the Technical Program Committees and Organizing Committees of many IEEE and non-ieee International Conferences, Symposia, and Workshops, and also acted as Session Organizer, Session Chair, and Panelist He also served as the Co-Chair of the IEEE Computer Society Students Activities Committee from Region 7 (Canada) He was the Associate Guest Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS Special Issues on Microelectronic Systems (Third and Fourth Special Issues) and Guest Editor, jointly with Rochit Rajsuman, for a Special Section of the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT on Innovations in VLSI Automatic Test Equipment, October 2003 Dr Das is a Member of the Association for Computing Machinery (ACM) He was elected one of the delegates of the prestigious Good People, Good Deeds of the Republic of China in 1981 in recognition for his outstanding contributions in the field of research and education He is listed in the Marquis Who s Who Biographical Directory of the Computer Graphics Industry, Chicago, IL (First Edition, 1984) He is the 1996 recipient of the IEEE Computer Society s highly esteemed Technical Achievement Award for his pioneering contributions in the fields of switching theory and modern digital design, digital circuits testing, microarchitecture and microprogram optimization, and combinatorics and graph theory He is also the 1997 recipient of the IEEE Computer Society s Meritorious Service Award for excellent service contributions to the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS AND THE SOCIETY, and was elected a Fellow of the Society for Design and Process Science in 1998 for his accomplishments in integration of disciplines, theories and methodologies, development of scientific principles and methods for design and process science as applied to traditional disciplines of engineering, industrial leadership and innovation, and educational leadership and creativity He became a Golden Core Member of the IEEE Computer Society in 1998 in recognition for being one of the distinguished core of dedicated volunteers and staff whose leadership and services made the IEEE Computer Society the world s preeminent association of computing professionals He is the recipient of the IEEE Circuit and Systems Society s Certificates of Appreciation for services rendered as Associate Editor, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, during and , and of the IEEE Computer Society s Certificates of Appreciation for services rendered to the Society as Member of the Society s Fellow Evaluation Committee, once in 1998 and again in 1999 He served as a Member of the IEEE Computer Society s Fellow Evaluation Committee for 2001, as well He was elected a Fellow of the Canadian Academy of Engineering in 2002 for pioneering contributions to computer engineering research specifically in the fields of switching theory and computer design, fault-tolerant computing, microarchitecture and microprogram optimization, and to some problem areas in applied theory of graphs and combinatorics He is the recipient of the prestigious Rudolph Christian Karl Diesel Best Paper Award of the Society for Design and Process Science in recognition of the excellence of their paper presented at the Fifth Biennial World Conference on Integrated Design and Process Technology held in Dallas, TX, June 4 8, 2000 He is also the co-recipient of the IEEE s esteemed Donald G Fink Prize Paper Award for 2003 for a paper published in the December 2001 issue of the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT He was elected a Fellow of the IEEE in 1994 for contributions to switching theory and computer design Made Sudarma received BEng degree in computer engineering from the Department of Electrical Engineering, Institute of Technology Sepuluh Nopember Surabaya (ITS), East Java, Indonesia, in 1992, and the MASc degree in electrical and computer engineering from the School of Information Technology and Engineering, University of Ottawa, Ottawa, ON, Canada, in 2000 He is currently a faculty member in the Department of Electrical Engineering, Udayana University in Jimbaran, Bali, Indonesia, where he has been since 1993 He is currently the Secretary General of the Indonesian Computer Society in Bali, as well His research interests are in the areas of fault-tolerance and fault diagnosis in digital systems Mansour H Assaf (M 03) received the Honors degree in applied physics from the Lebanese University, Beirut, Lebanon, in 1989, and the BASc and MASc degrees in electrical engineering and the PhD degree in electrical and computer engineering, from the University of Ottawa, Ottawa, ON, Canada, in 1994, 1996, and 2003, respectively From 1994 to 1996, he was associated with the Fault-Tolerant Computing Group, University of Ottawa, where he studied and worked as a Researcher After working at the Applications Technology, a subsidiary of Lernout and Hauspie Speech, McLean, VA, in the area of software localization and natural language processing, he joined the Sensing and Modeling Research Laboratory, where he currently works on projects in the field of human-computer interaction, 3-D modeling, and virtual environments His research interests are in the areas of human-computer interactions and perceptual-user interfaces, and in fault diagnosis in digital systems He is the co-recipient of the IEEE s esteemed Donald G Fink Prize Paper Award for 2003 for a paper published in the December 2001 issue of the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT Emil M Petriu (M 86 SM 88 F 01) received the DiplEng and DrEng degrees from the Polytechnic Institute of Timisoara, Romania, in 1969 and 1978, respectively He is a Professor at the School of Information Technology and Engineering, University of Ottawa, Ottawa, ON, Canada, where he has been since 1985 His research interests include test and measurement systems, interactive virtual environments, intelligent sensors, robot sensing and perception, neural networks, and fuzzy control During his career, he has published more than 180 technical papers, authored two books, edited two books, and received two patents Dr Petriu is a Fellow of the Canadian Academy of Engineering and Fellow of the Engineering Institute of Canada He is currently serving as a member of the AdCom, and chair of TC-15 Virtual Systems and co-chair of TC-28 Instrumentation and Measurement for Robotics and Automation of the IEEE Instrumentation and Measurement Society He is an Associate Editor of the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT and member of the editorial board of the IEEE INSTRUMENTATION AND MEASUREMENT MAGAZINE He is co-recipient of the 2003 IEEE Donald G Fink Prize Paper Award Wen-Ben Jone (S 85 M 88 SM 01) was born in Taipei, Taiwan, ROC He received the BS degree in computer science and the MS degree in computer engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1979 and 1981, respectively, and the PhD degree in computer engineering and science from Case Western Reserve University, Cleveland, OH, in 1987 In 1987, he joined the Department of Computer Science at the New Mexico Institute of Mining and Technology, Socorro, NM, where he was promoted as an Associate Professor in 1992 From 1993 to 2000, he was with the Department of Computer Engineering and Information Science, National Chung- Cheng University, Chiayi, Taiwan He was a Visiting Research Fellow with the Department of Computer Science and Engineering, the Chinese University of Hong-Kong, in 1997 Since 2001, he has been with the Department of Electrical and Computer Engineering and Computer Science, University of Cincinnati, OH He was a Visiting Scholar with the Institute of Information Science, Academia Sinica, Taiwan, in 2002 His research interests include VLSI design for testability, built-in self-testing, memory testing, high-performance circuit testing, MEMS testing and repairing, and low-power circuit design He has served as a reviewer in these research areas in various technical journals and conferences He has published more than 100 papers and holds one US patent He has served on the program committee of VLSI Design/CAD Symposium ( , Taiwan), the program committee of the 1995, 1996, and 2000 Asian Test Conference, the Asia and South Pacific Design Automation Conference, the 1998 International Conference on Chip Technology, the 2000 International Symposium on Defect and Fault Tolerance in VLSI Systems, the 2002 and 2003 Great Lake Symposium on VLSI, and he was the General Chair of the 1998 VLSI Design/CAD Symposium Dr Jone is listed in the Marquis Who s Who in the World (15th Edition, 1998, 2001) He received the Best Thesis Award from The Chinese Institute of Electrical Engineering (Republic of China), in 1981 He is a co-recipient of the 2003 IEEE Donald G Fink Prize Paper Award He is a member of the IEEE Computer Society Test Technology Technical Committee

18 1380 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL 52, NO 5, OCTOBER 2003 Krishnendu Chakrabarty (S 92 M 96 SM 00) received the BTech degree from the Indian Institute of Technology, Kharagpur, in 1990, and the MSE and PhD degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively, all in computer science and engineering He is currently Associate Professor of electrical and computer engineering at Duke University, Durham, NC From 2000 to 2002, he was a Mercator Visiting Professor at University of Potsdam, Germany His current research projects (supported by NSF, DARPA, ONR, Army Research Office, and industrial sponsors) are focused on system-on-a-chip test, embedded real-time systems, distributed sensor networks, and modeling, simulation, and optimization of microelectrofluidic systems He is a coauthor of two books: Microelectrofluidic Systems: Modeling and Simulation (Boca Raton, FL: CRC, 2002) and Test Resource Partitioning for System-on-a-Chip (Norwell, MA: Kluwer, 2002), and the Editor of SOC (System-on-a-Chip) Testing for Plug and Play Test Automation (Norwell, MA: Kluwer, 2002) He is an Editor of the Journal of Electronic Testing: Theory and Applications (JETTA) He was the Guest Editor of a special issue of JETTA on system-on-a-chip testing, published in August 2002 He was also a Guest Editor in 2001 of a special issue of Journal of the Franklin Institute on distributed sensor networks He has published over 120 papers in archival journals and refereed conference proceedings, and he holds a US patent in built-in self-test Dr Chakrabarty is a member of ACM and ACM SIGDA, and a member of Sigma Xi He serves as Vice Chair of Technical Activities in IEEE s Test Technology Technical Council, and is a member of the program committees of several IEEE/ACM conferences and workshops He is an Associate Editor of the IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING He is a recipient of the National Science Foundation Early Faculty (CAREER) award and the Office of Naval Research Young Investigator award He is a recipient of a best paper award at the 2001 Design, Automation and Test in Europe (DATE) Conference Mehmet Şahinoğlu (S 78 M 81 SM 93) received the BS degree in electrical and computer engineering from the Middle East Technical University (METU), Ankara, Turkey, in 1973, the MS degree in electrical and computer engineering from the University of Manchester Institute of Science and Technology, Manchester, UK, in 1975, and the PhD degree in both electrical and computer engineering and statistics from Texas A&M University, College Station, in 1981 Prior to joining the CIS Department, Troy State University, Montgomery, AL, as its first Eminent Scholar and Chairman in 1999, he was at METU for 20 years as a Reliability Consultant to the Turkish Electricity Authorities (TEK) and The National Defense Industry, Ankara, from 1976 to 1992, as a Professional Certified Engineer He then served for five years as a Founder Dean of Science and Founder Chairman of the Department of Statistics at Dokuz Eylul University, Izmir, Turkey, from 1992 to 1997 He taught at Purdue University, West Lafayette, IN, from 1989 to 1990 and 1997 to 1998, and Case Western Reserve University, Cleveland, OH, from 1998 to 1999 as a Visiting Fullbright and NATO Research Scholar, respectively He retired in 2000 after 26 years of civil service in Turkey as a Professor Emeritus He published in electric power earlier in his career, and computer software reliability and testing in later years He is accredited for the original findings of the Compound Poisson Software Reliability Model to account for the multiple (clumped) failures in predicting the total number of failures at the end of a mission time, and the MESAT: Compound Poisson Stopping Rule Algorithm in software testing literature He is also jointly responsible, with Dr David L Libby, for the original derivation of the Forced Outage Ratio (FOR) or Generalized Three-Parameter Beta (G3B) pdf He recently created an Exact Reliability Block Diagram Calculation (ERBDC) Tool, which is a novel graphical technique in the literature for quantifying and designing the reliability of computationally very complex systems Dr Şahinoğlu is a Fellow of the Austin-based Society of Design and Process Science, a member of ASA, and an elected member of ISI