On Broad-Side Delay Test

Transcription

1 Abstract On Broad-Side Delay Test A broad-side delay test is a form of a scan-based delay test, where the first vector of the pair is scanned into the chain, and the second vector of the pair is the combinational circuit s response to this first vector. This delay test form is called broad-side since the second vector of the delay test pair is provided in a broad-side fashion, namely through the logic. This paper concentrates on generation of broad-side delay test vectors; shows the results of experiments conducted on the ISCAS sequential benchmarks, and discusses some concerns of the broad-side delay test strategy. 1 Introduction Jacob Savir Srinivas Patil IBM Microelectronics Division ing to the path delay fault model, a path may be delay fault-free while one or more of the gates along the path may exceed their specified propagation delay. This phenomenon may happen since the response of slow gates may be compensated for by the response of faster gates along the path, so that the total input to output delay happens to be within the acceptable range. For a gate delay fault to cause an incorrect value to be latched at a circuit output, the size of the delay fault must be such that at least one path originating at the gate has a propagation delay that exceeds its specification. A gate delay fault whose magnitude is such that it causes the propagation delays of all paths passing through the fault site to exceed the clock period (or observation time) is called a gross delay fault [15]. To test for a gross delay fault, it is only necessary to excite and propagate the fault effect to any output of the circuit. Ascertaining correct operation of digital logic circuits requires verification of functional behavior as well as correct operation at desired clock rates. Failures causing logic to malfunction at desired clock rates are called delay faults, or AC faults. These delay faults are normally due to random variation in process parameters that often cause propagation delays to exceed their limits. Detection of a delay fault normally requires the application of a two-pattern test: the first pattern applies an initialization value at the site of the suspected fault, and the second pattern provokes the transition at the site of the fault and propagates its effect to a primary output or latch. The two-pattern test will provoke a 0-to-1 transition at the site of the fault to test for a slow-to-rise (STR), and a 1-to-0 transition to test for a slow-tefall (STF) fault. By measuring the output at the desired time interval one can ascertain whether or not a delay fault exists in the circuit. Two models have been proposed for delay faults: the gate delay fault [4] and the path delay fault [16]. According to the gate delay fault model any input to a gate can be subjected to a delay fault that may cause the response of the gate to be slow compared to its specification. The path delay fault model focuses on the aggregate delay along the path and not on the individual delays of the gates comprising the paths. Thus, according to the path delay fault model, a path has a delay fault if the time it takes to propagate a signal along the path exceeds some specified value. Note that accord- This paper concentrates on transition tests. The gate delay fault model, or the point defect assumption, is implicit in the transition fault model. Another important assumption is the assumption of gross gate delay faults, i.e. gate delay faults which manifest themselves on all paths passing through the site of the fault. It is easy to see that the only extra excitation which needs to be satisfied under the transition fault model (beyond what is required for stuck-faults) is the presence of an initializing pattern immediately before the application of the stuck-at test pattern. It can be expected that the fault coverage figures obtained using transition patterns will be very close to those obtained for stuck-at faults for the same logic circuit. One should keep in mind, however, that the fault coverage figures obtained for transition patterns are for gross delay faults, and a more detailed analysis will be necessary to evaluate the coverage for smaller delay faults [9]. Note that an important distinction between transition tests and robust tests [ll] is that transition tests do not require complementary initial and final output values when the delay fault is detected, while robust tests do. A robust test would result in a 0-tel or a 1-to-0 transition on at least one output (probably with some hazards between transitions), while a transition test may result in a waveform with the same initial and final values, but a complementary value in between; the duration of the complementary value being determined by the size of the fault /94 $ IEEE 284

2 This paper discusses several issues concerning broadside delay test. A broad-side delay lcsf is a form of scan-based (such as level sensitive scan designs (LSSD) [3]) delay test, where the first pattern is scanned into the chain, and the second vector of the pair is supplied through the combinational logic. Both the launching of transition and the capture of the circuit response are accurately timed according to the system requirement. Since the first vector is applied through the scan and the second through the logic, the broad-side delay test can be viewed as a semi-functional test run at speed. This method is different from the skewed-load transition test [13, lo], where both the first and second vectors of the delay test pair are applied by the scan hardware. Test generation for delay faults in nonscan designs can be found in [l]. Test generation for delay faults in scan designs and synthesis issues can be found in [SI. We will show that in many cases the broad-side delay test coverage is relatively low. This is due to the limited potential of the broad-side method to apply a rich set of two-pattern tests. This paper is organized in the following way. Section 2 shows how to compute broad-side delay test vectors both analytically and practically. Section 3 describes some experimental results of the broad-side method and compares it to skewed-load. Section 4 expresses some concerns about the broad-side method, and concludes with a brief summary. 2 Computation of a Broad-Side Delay Test Vector Let VI and V? be the two test vectors that comprise the broad-side delay test pair, where VI is the first vector and Vz is the second vector of the pair. For (VI, V2) to constitute a transrtzon test for a given fault, VI needs to set the net in question to its initial value, and Vz needs to be a test for the dual stuck-fault. The initial value for an STR (STF) fault is 0 (l), and the final vector is a stuck-at 0 (1) test. In this section we develop a Boolean-difference-based calculus for broad-side delay test. With this calculus it is possible to compute all the broad-side delay test pairs (called a complete broad-side delay test set) that detect a given transition fault. The calculus allows the computation of both VI and V2 simultaneously. Since the method is Boolean-difference-based, it has all the advantages and disadvantages that go with this method. In the discussion that follows it is assumed that the reader is farriiliar with the Boolean difference technique. The interested reader is referred to [2, 71. Let g be a line in a circuit having n inputs. We will sometimes use g to refer to the name of the line, and sometimes to refer to the Boolean function realized by this line. The actual meaning should be clear from the context. We also denote by I = (zl,z2,..., I,) an input - 0 a - s- 4 a COMBINATIONAL a a 0 CIRCUIT 1 :, Figure 1: A single section LSSD network vector, and by y = (yl, yz,..., y,) an output vector of a combinational section of the network, where y = F(I). In this notation 2, is the i-th component of vector x. We first deal with the computation of broad-side delay test in single section networks, and then generalize it to multiple section networks. 2.1 Single Section Circuits Assume that there is a parity between the number of inputs and the number of outputs in the combinational circuit section (see Fig. 1). The formulas derived here could be easily generalized when a circuit has different number of inputs and outputs. This might happen in a case where some of the scan stages are fed from pure primary inputs. Thus, let the feedback connection realized by the LSSD circuit be such that output line y, drives input line I, via the scan. From a broad-side test perspective, zi provides the corresponding VI value, and yi provides the corresponding "2 value for the input line i. To detect an STR fault on line g! the vector I must set the line to a value 0, and the vector y must detect a stuck-at 0 fault on line g (during the Vz phase). Since y is the response of the combinational section to I, we have y = F(z), where F is the output function vector. The solution of the following equation, therefore, constitutes a complete test set for the initial vector I that participates in the broad-side delay test pair that detects an STR fault on line g. In a similar fashion, the solution to the following equation constitutes a complete test set for the initial vector I that participates in the broad-side delay test pair that detects an STF fault on line g. Note that the summations in eqs. Boolean. 1 and 2 are 285

3 Figure 2: Circuit for example 1 8-sde The second vector of the broad-side delay test pair, y, is computed by substituting I in y = F(z). The vector 2 is the solution to eq. 1 or 2, depending on the case. Example I: Compute the broad-side test vectors for g-str, and g-stf in Fig. 2. The circuit in Fig. 2 shows the combinational network section only. The signals y; appear in parenthesis in Fig. 2. Note that signals y; are considered output values during 1 1, and input values during V2. During the VI phase we have: g = 11 During the C; phase we have: Thus, To compute an STR broad-side test, we solve eq. 1. We get: Since there is no solution to eq. 1. the g-str fault is undetectable. To compute an STF broad-side test, we solve eq. 2. We get: Figure 3: The undetectable transition faults using broad-side and skewed-load for the circuit of example 1 Figure 4: A double section LSSD network 2.2 Multiple Section Circuits We generalize here our previous results to multiple section LSSD networks. We will show the generalization in a double section network, although everything we show here applies to two adjacent sections in a general multiple section network. Consider a double section network, like in Fig. 4. To detect an STR fault on line g in section A, the first vector, I, must initialize g to 0, and the second vector, FB(Z), must detect the dual stuck-fault. Thus, the solution to the following equation constitutes the complete broad-side delay test for the initial vector, 2. In a similar manner, the solution of the following equation constitutes the complete broad-side delay test for the initial vector, 1, that detects the STF fault on line g. = I IVl = 21- = ZlZZ = 1 Thus, the STF broad-side test is 1112 = 10. It is interesting to compare the broad-side method to the skewed-load on this example. Fig. 3 shows the undetectable faults per these two methods. The undetectable faults are marked by up/down arrows. An up arrow indicates an undetectable STR fault, and a down arrow an undetectable STF fault. When both faults are undetectable, the line is marked by a joint up/down arrow. Notice that the broad-side method has quite a few more undetectable transition faults than the skewed-load method. To compute test vectors for transition faults residing in section B. interchange A and B in eqs. 3 and 4. We illustrate the computation by an example. Example 2: Fig. 5 shows the two combinational sections in a double section LSSD network, like in Fig. 4. Compute the initial vector of the broad-side test that detects both g-str. and g-stf. The first vector of the broad-side test is denoted by Z. Inputs 11 and 12 refer to the initid vector stored in the scan driving section A, and inputs 13 and zq refer 286

4 A E E Figure 5: Circuit for example 2 A 0 "1 Figure 7: Portion of a double section circuit that is used to generate the VI vector to detect an STR fault, in section A A B Figure 6: The undetectable transition faults using broad-side and skewed-load for the circuit of example 2 to the initial vector stored in the scan driving section B. The outputs of section B, y1 and yz, constitute the second vector of the broad-side delay test pair, and appear in parenthesis in the drawing of section A. We have: During the Vl phase: g = 21 During the V2 phase: af1 g = yi = ~ 3x4, Fi = gyz, - = yz = as To compute a test for an STR fault we solve: - = 21132'4(r3 + 14) =?113l4 = 1 Thus, the initial vector of the broad-side delay test pair that is used to detect this fault is I = (0 - ll}, where a dash means a don't care. To compute a test for an STF fault we solve: Thus, the initial vector of the broad-side delay test pair that is used to detect this fault is I = (1-01,l - 10). Like in the previous example, it is interesting to compare the undetectable faults using broad-side and skewed-load. Fig. 6 shows the set of undetectable faults for this example using both broad-side and skewed-load. " Figure 8: Portion of a double section circuit that is used to generate the Vz vector to detect an STR fault in section A The arrows in Fig. 6 indicate the type of the undetectable transition fault. As can be seen in Fig. 6 both methods have comparable number of undetectable faults. As seen in this example, the broad-side method is not doing that bad. Experiments have shown that the broad-side delay test coverage is considerably better in multiple section circuits than in single section circuits, as was also observed in the two examples shown previously. 2.3 Test Generation of Broad-Side Delay Test Patterns Since Boolean difference is not an attractive method for test generation, one needs a more efficient way to handle large structures. The question, therefore, arises whether it would be possible to extend stuck-fault test generation engines to accommodate the broad-side method. The answer to this is yes, and we will show here what kind of extensions are necessary. Test generation of broad-side delay test patterns can be performed with any existing package aimed at stuckat-faults, like [12, 81. Consider for example a double section LSSD network, as in Fig. 4. Let the fault in question be an STR fault in section A. Fig. 7 shows the circuit that has to be analyzed to generate the VI vector. The test generation package (TGP) needs to search for an input vector Vi that will assign an initial value 0 to line g. This can be done by simply invoking the line justification program of the TGP. Fig. 8 shows the portion of the circuit that h.as to

5 be analyzed to compute the Vz vector of the broad-side delay test pair. Notice that both sections have been concatenated, such that section B feeds section A. To compute the vector, the TGP needs to search for a test pattern for the Fault g stuck-at 0 (g/o). The computatmion of such a vector can be done very efficiently, because the TGP has been designed to perform this kind of task. Notice that the test generation process generally requires a two consecutive time frame analyses. 3 Experimental Results We have conducted an experiment on the entire set of ISCAS sequential benchmark circuits [5] to see how the broad-side delay test compares with the skewed-load method, and to see whether or not a combination of these two methods has any merit. Tab. 1 shows the fault coverages obtained by this experiment. The first column in Tab. 1 identifies the circuit by name. The second column, referred to as Stuck, shows the attainable single stuck-fault coverage for the circuit. The reason why this column is added to the table is that it also constitutes an upper bound on the attainable transit ion fau It coverage. The third column, referred to as Indep, shows the transition fault coverage achieved by applying 100,000 independent set of random pattern test pairs against the circuit. The vectors have been independently generated such that there was absolutely no correlation between the VI and the Vz. Obviously, the asymptotic transition fault coverage attainable in this mode is identical to the single stuck-fault coverage. As seen in Tab. 1, some circuits already achieve the maximum transition fault coverage after 0 independent test pairs. The fourth column, referred to as B-side, shows the transition fault coverage obtained after applying 100,000 pseudmrandom broad-side patterns against the circuit. Notice that in this mode, VI is a pseudo-random vector that is independently generated, and the V2 vector is the combinational circuits response to this first vector. The fifth column of the table, referred to as, shows the transition fault coverage obtained after applying 100,000 pseudo-random skewed-load patterns against the logic. In this mode of test, the V2 vector is essentially a one-bit-shift of its VI predecessor. As can be seen in Tab. 1, except for few cases, the transition fault coverage obtained for skewed-load is considerable better than for broad-side. As a matter of fact, the average transition fault coverage difference between skewed-load and broad-side is 6.2 % for the 100,000 pattern experiment. The last three columns of Tab. 1 show the performance of a nuniber of hybrid or extended methods. The sixth column, referred to as + B-side, shows the transition fault coverage achieved by first applying 100,000 pseudo-random patterns in a skewed-load fashion, and then supplementing it by another 100,000 patterns applied in a broad-side manner. Thus, this column represents a fault coverage that is obtained after applying altogether 200,000 pseudo-random patterns. This hybrid method was able to lift the average transition fault coverage achieved by the first 100,000 skewed-load patterns by 5.26 %. One should be careful in granting this fault coverage boost solely to the broad-side phase. It is quite possible that some of this increase would have been achieved if the first phase of the skewed-load would have continued for another 0 pseudo-random patterns. The seventh column of Tab. 1, referred to as t, shows the transition fault coverage achieved by applying 100,000 pseudo-random patterns, when the latches in the scan path are allowed to be re-ordered to enhance the delay test performance. As described in [6,7], it is possible to re-order the position of the latches along the scan in order to minimize the shift dependency effect, on the combinational logic. This re-ordering can substantially increase the transition fault coverage attainable by skewed-load. As seen in Tab. 1, this latch re-ordering was able to increase the transition fault coverage of skewed-load by an average of 3.3 %. The eight-th column of Tab. 1, referred to as t+ B-side, is a repetition of the hybrid method described earlier, with the exception that the scan latches were allowed to be re-ordered to enhance the transition test coverage. The number of pseudorandom tests applied in this mode is a total of 200,000, as before. This hybrid method was able to increase the transition fault coverage by an average of 3.46 % over what the skewed-load with only latch re-ordering ( seventh column) was able to achieve. Here again, one should be very careful in attributing this increase solely to the broad-side phase, because it is quite possible that some of the increase is due to the additional 100,000 patterns, and that it could have been achieved by continuing the skewed-load phase. 4 Conclusions and Other Concerns About Broad-Side Delay Test As shown in the previous section, the broad-side method does not perform nearly as well as skewed-load. It is, therefore, difficult to justify why the broad-side method should be the primary scan-based delay test strategy. It should not, however, be dismissed completely, because it might have some incremental value when used in a hybrid delay test scheme. There are several problems with the broad-side delay test method. The primary problem is its limited capability to generate a rich set of two-pattern tests, 288

6 Table 1: Transition Fault Coverage for the ISCAS Sequential Benchmark Circuits Circuit s208 s298 s344 s349 s382 s386 s400 s420 s444 s510 s526 s526n s64 1 s713 s820 s832 s953 s1196 s1238 s1423 s1488 s1494 s5378 s9234 s13207 s15850 s35932 Stuck Indep B-side B-side t t + B-side tafter re-ordering the flip-flops based on sub-cones The skewed-load/broad-side combination results were obtained by first running 100,000 patterns for skewed load and then running broad-side on the remaining faults for another 100,000 patterns. 289

7 especially in single-section networks. What aggravates the situation even further is that generally there is nothing that can be done in terms of design for testability, to improve its delay test performance. When compared to skewed-load, this is a major disadvantage. The performance of skewed-load can be substantially improved by performing latch re-ordering, or even made to be ideal by performing a complete input separation [14]. The input separation method re-assigns the combinational circuit inputs to scan latches, so that no two inputs belonging to the same output cone emanate from adjacent latches on the scan chain. This separation of inputs completely breaks the shift dependency associated with the skewed-load method, and allows its transition fault coverage to assume the maximum possible value (equal to the stuck-fault coverage). Input separation, however, does not come without a cost (extra latches and performance degradation due to possible longer wires), and this is where the incremental value of the broad-side method may come into play. For cases were latch reordering is infeasible, a hybrid test methodology, that uses skewed-load as the primary mode. and broad-side as a secondary mode, is a viable alternative. There is also a secondary problem associated with the simulation of broad-side patterns. Since the second vector of the transition test is generated through the logic, the simulation is generally a two-time-frame event. This event slows down the processl and is quite profound in simulation of large structures. Still another problem with broad-side, when compared to skewed-load, is its unbounded (from below) fault coverage. The minimum transition fault coverage attainable by skewed-load is conjectured to be 50 %. Unfortunately, there is no such minimum attainable by broad-side. It is quite easy to come up with examples were the broad-side transition fault coverage is below 50 % (see Fig. 3). This paper has studied the problem of broad-side delay test generation. It has provided a Booleandifference-based approach to calculate broad-side delay test vectors. It has shown how to modify (in concept) existing test generation tools so that they be able to generate broad-side delay test vectors. As a final chapter, it has shown the results of an extensive experiment, conducted on the ISCAS sequential benchmark circuits, to assess the capability of the broad-side method, and other hybrid methods that involve broadside and skewed-load. References [l] P. Agrawal. V.D. Agrawal. and S.C. Seth. Generating tests for delay faults in nonscan circuits. IEEE Design and TES~ of Computers, 10:20-28, March [2] S. B. Akers. On a theory of boolean functions. J. Society of Industrial Math, 7(4): , [3] P. H. Bardell, W. H. McAnney, and J. Savir. Built- In Test for VLSI: Pseudorandom Techniques. Wiley Interscience, [4] Z. Barzilai and B. Rosen. Comparison of AC selftesting procedures. In Proc. Int. Test Conf., pages 89-94, October [5] F. Brglez, D. Bryan, and K. Kozminski. Combinational profiles of sequential benchmark circuits. In Proc. Int. Symp. Circutls and Systems, pages , May [S] K.T. Cheng, S. Devadas, and K. Kuetzer. Delayfault test generation and synthesis for testability under a standard scan design methodology. IEEE Trans. Computer-Aided Design, 12: , August [7] A. C. L. Chiang, I. S. Reed, and A. V. Banes. Path sensitization, partial boolean difference, and automated fault diagnosis. IEEE Trans. Computers, pages , February [8] H. Fujiwara. Logic Testing and Design for Testability. MIT Press, [9] V. S. Iyengar, B. K. Rosen, and J. A. Waicukauski. On computing the sizes of detected delay faults. IEEE Dans. Computer-Aided Design, pages , March [lo] S. Patil and J. Savir. -load transition test: Part 11, coverage. In Proc. Int. Test Conf., pages , September [ll] S. M. Reddy, C. J. Lin, and S. Patil. An automatic test pattern generator for the detection of path delay faults. In Proc. Int. Conf. Computer- Aided Design, pages , November [12] J. P. Roth. Diagnosis of automata failures: A calculus and a method. IBM J. Research Development, 10: , July [13] J. Savir. -load transition test: Part I, calculus. In Proc. Int. Test Conf., pages , September [14] J. Savir and R. Berry. At-speed test is not necessarily an AC test. In Proc. Id. Test Conf., pages , October [15] J. Savir and W.H. McAnney. Random pattern testability of delay faults. IEEE Trans. Computers, 37: , March [16] G. L. Smith. Model for delay faults based upon paths. In Proc. Int. Test Con&, pages , November