Mahsa Vahidi and Alex Orailoglu. La Jolla CA of alternatives needs to be explored to obtain the

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1 Metric-Based Transformations for Self Testable VLSI Designs with High Test Concurrency Mahsa Vahidi and Alex Orailoglu Department of Computer Science and Engineering University of California, San Diego La Jolla CA Abstract We propose an approach for improving the testability of a design under BIST methodology through behavioral restructuring. Our results show that the proposed transformations help reduce the number of required test sessions. 1 Introduction With the constant increase in chip sizes, access paths for testing chip modules have become increasingly scarce. Traditional test approaches are rapidly becoming major cost factors for high-frequency, submicron VLSI designs. Techniques, such as design for testability, make chips testable by placing test structures on parts of the circuit that are less accessible and hard to test, thus alleviating the impact of rapidly increasing test costs. It has been projected that the inclusion of design for testability techniques will increase from 25% to 90% during the next dozen years. This change will also result in a dramatic decrease in the number of required test vectors. While traditional test approaches capture increasingly a larger share of the overall design cost, traditional design approaches themselves have been having trouble in meeting the design challenges posed by large, high-density chips. Consequently, methodologies such as high-level synthesis have been instrumental in alleviating design costs by raising the abstraction level of design entry. High level synthesis addresses the design and implementation of digital circuits given a behavioral description. The function to be performed by the chip is given in a high level language, such as VHDL, along with a set of design constraints. The recent trend in moving from structural to system level design and the increasing importance of expediting the design and re-design cycles has driven an increased number of semiconductor companies to adopt synthesis as part of their design methodology. Anovel problem posed by the higher design entry levels necessitated by high level synthesis is the uniqueness of the specication. Frequently, a designer can express the same design specication in multiple behavioral forms, while a single behavioral description may map to multiple intermediate forms. This multiplicity of forms, even though semantically equivalent, This work was supported by the Semiconductor Research Corporation under contract number DJ-538. nonetheless, can lead to radically dierent implementations with current synthesis tools. Each of these representations has an associated, and frequently differing, time, area and test overhead. This rich set of alternatives needs to be explored to obtain the most suitable representation for the given design constraints. Traditionally, area and speed have been the most important constraints in the process of high level synthesis. However, due to the increased complexityof VLSI chips, design for testability constraints have recently become an important part of high level synthesis. As tradeo options increase, the evaluation of all possible alternatives becomes impossible without the use of an analysis tool. It is essential that methods for addressing tradeos, including test considerations, be addressed at the highest levels of design entry, where frequently the resultant impact of a design decision is the largest. In this paper we present a new approach onex- ploring test options at behavioral level. Our approach uses transformations to restructure behavioral design descriptions with the goal of improving the design's testability. Testability improvements in high level synthesis are aimed at reducing the time and area overhead associated with incorporating test structures. Test application time is a constraint that directly affects the production cost by lengthening the time required for testing. In this paper, we illustrate the ecacy of our transformational approach to test cost alleviation, by applying it to the problem of synthesis of self-testable designs. BIST is a design for testability approach wherein testability isachieved by performing test pattern generation and test result evaluation on chip. The specication restructurings are performed on an intermediate dataow graph format of the design which is transparent to the designers, but more suitable for performing algebraic transformations. Such transformational approaches are supported through testability metrics, previously developed, which capture the test time overhead measures, associated with BIST [11]. The metrics and the corresponding test synthesis model are described in the denition section. In the results section, we construct specic benchmark examples to illustrate the eect of transformations on test time issues in a conceptual manner. Furthermore, experimental results are obtained on standard benchmarks to show the coarse grain eects of restructuring on a design's testability.

2 2 Previous Research The recent advances in high level synthesis have provided an aid for designers to expedite the design cycle by automating the design process. Design constraints such as area and speed tradeos have been extensively studied in synthesis [5]. The increasing importance of generating testable designs has raised the need to incorporate testability constraints into high level synthesis. An overview of recent work in synthesis for testability can be found in [1]. Various metrics have been developed to help make focused decisions on performing testability improvements on a design. Thearling and Abraham have studied observability and controllability testability measures at the functional level [10]. Randomness and transparency metrics have helped explore the tradeos between test time and test hardware overhead at system level [3]. In [11], a set of metrics for measuring testability in terms of test time and concurrency are proposed. Transformations have been used to explore constraints such as register optimization [8], power minimization [2], and ecient resource utilization [9]. Transformations have also been applied in high level synthesis of fault-tolerant ASICs [7]. Dey proposes transformations for reducing the partial scan cost of test synthesis [4]. In this approach, test area minimization is achieved by using hot potato transformation techniques to minimize the number of scan registers needed to break CDFG loops and to avoid the formation of other types of loops during assignment. 3 Denitions 3.1 Testability Model The work in this paper intends to evaluate testability issues involved in incorporating Parallel BIST methodology. During BIST operations, the registers in a design are recongured as either linear feedback registers () or signature analysis registers (). We briey describe some features of our model in this section; a complete denition can be found in [6]. A test path is a collection of paths which are chosen in a manner to allow access to the ports of all modules. Two test paths can be performed in one test session as long as there is no conict between them. A conict can occur if the two paths share a register which is used as in one path and in the other. It can also happen when two sets of test vectors need to go through one at the same time. A conguration conict is illustrated in gure 1. In order to achieve high concurrency, the number of test sessions must be minimized. This can be done by reducing the number of conicts among test paths. A dataow graph (DFG) represents the data dependencies between operations, while a datapath contains the data dependencies between assigned modules. The test path will contain false paths when it is not a subgraph of the dataow graph. Our test model enables the possible use of false paths since the degree of freedom they provide in choosing test paths can result in reduced test time. Test controller optimization can be used to reduce this additional cost. R 1 R 2 R 3 R 4 TEST PATH 1 M 1 A 1 R 1 R 2 R 3 R 4 M 1 A 1 R 5 R 5 A 2 R 6 TEST PATH 2 TEST PATH 1 R 7 A 2 R 6 TEST PATH 2 Figure 1: conguration conict, Conict is eliminated due to more fan out at and the two test paths can be executed concurrently 3.2 Test Synthesis Model Research for synthesis of self-testable designs is still at early stages of development and consequently no methodology has as of yet been rmly established. In order to provide an appropriate context, we outline a specic test synthesis methodology in this section, for which the applicability of our test metrics [6] has been proven. Figure 2 illustrates the organization of this framework. The test synthesis framework con- Behavioral Description Dataflow Graph Generator Dataflow Graph Behavioral Restructuring DFG With Improved Testability Test Register Insertion Scheduling BIST Datapath Behavioral Synthesis RTL Datapath Test Scheduling Binding Structural Synthesis Figure 2: Test synthesis framework Test Path Definition BIST Test Plan sists of many modules which work towards producing a testable design and its BIST datapath and test plan. The module which performs Behavioral Restructuring is the topic of this paper and transforms chip level design into semantically equivalent forms which are more suitable for satisfying the given test constraints. Such restructuring is followed by the behavioral synthesis process which includes two modules. Dataow Scheduling and Binding determine the RTL interconnection structure of the design. Once the microarchitectural description has been dened, the test synthesis of the design is completed by performing structural synthesis. Structural synthesis includes three modules: Test Register Selection, Test Path Denition and Test Scheduling. 3.3 Metrics In this section, we briey review the testability metrics which form the basis of our restructuring techniques. These three metrics are dened as conict, coverage and correlation [11]. The metrics are formulated at the behavioral level and transition smoothly to all lower abstraction levels of synthesis. The behavioral formulation of the metrics is utilized in this work to address the needs of behavioral transformations. Since scheduling and

3 binding information is not available at these stages of synthesis, probability of common bindings (PCB) values model the probability that two operations will share a hardware unit in the nal datapath and are used as a basis for all the metrics. The concept behind the conict metric was shown in gure 1. Multiple occurrences of a component, within a concurrent test session, can introduce con- icts in component utilization during testing and result in a slower test application time. The conict metric is a measure of the amount of conict in a graph if all components were to be tested in one test session. The coverage metric represents test application time by looking at the design from a path-oriented perspective. Since coverage values are computed on the basis of a single test session assumption, high coverage values throughout the design denote few test sessions while low coverage values denote increased test sessions. While coverage and conict are aimed at solving the problems of test time minimization by minimizing the conicts among test paths, the correlation metric is developed to improve problem areas in the design which can cause increased test time due to a need for more test patterns. Correlation is caused when both inputs to a module are receiving random patterns originating from the same source and can either happen through false paths or be embedded in the structure of the ow graph. 4 Transformations The proposed transformations include associativity, distributivity, duplication, commutativity and strength reduction. The above transformations are divided into local and global categories based on their overall eect on the design's testability metrics. Global transformations such as associativity impact the mobility of a wide range of operations in the graph and can achieve higher optimization. Local transformations such as commutativity and distributivity follow the global transformations and are useful for ne grain improvements. They have the advantage of being simple and less computationally intensive. Transformations can frequently result in adverse eects on other design attributes. Detailed objective functions can be used to help resolve such conicts between design attributes. 4.1 Commutativity Commutativity is a local transformation which helps improve the conict and correlation metrics. This transformation is especially eective in cases where the problem lies in the interconnect structure of the dataow graph. We use the simple example of gure 3 to illustrate how commutativity reduces con- ict. Applying commutativity on node 1 eliminates the conguration conict which was caused by and registers. While two test sessions are needed to test the structure in gure 3, only one test session is needed for testing the structure in gure 3. Commutativity allows us to explore dierent interconnect options and nd the one which leads to the least amount of conict. 1 2 C-Step1 Commutativity 1 2 C-Step1 C-Step2 C-Step2 Test Path 1 Test Path Test Path 2 Figure 3: Applying commutativity on DFG reduces the number of test paths Commutativity helps improve correlation in the same fashion. This problem is eliminated by using commutativity toswap the correlating edges on one of the respective nodes. As a result, the correlating edges will be forced to go into the same input port in the resulting data path. It can be observed from gure 3 that commutativity reduces the interconnect and the number of required muxes in this example. Nonetheless, it is easy to observe that cases exist where the commutative transformation can lead to more complex interconnect. 4.2 Duplication Another transformation which helps improve both coverage and conict metrics is duplication. The amount ofcoverage that each node receives is dependent on its accessibility to the registers. This accessibility can be increased by performing duplication on low coverage nodes and providing them with more paths to reach the registers. Creation of these alternate paths can help increase the coverage of a node which has little or no access to an register. As a result, conict is also reduced on the modules which have a limited access to test paths. Duplication reduces correlation by increasing the length of the path from the source of correlation to the reconvergent fanout. Duplication can result in an increase in area overhead, especially for designs with high levels of hardware utilization. 4.3 Distributivity The distributivity transformation is used to eliminate reconvergent fanouts that are inherent in the structure of the owgraph. The eects of this transformation on correlation are illustrated in gure 4 where causes degradation of test data at. As can be seen in gure 4b, correlation is obviated as a result of the application of the distributive transformation. The fashion in which distributivity is applied for correlation problems decreases hardware requirements and area overhead. However, an additional clock cycle may be required, as shown in the above example.

4 A * * B Figure 4: Correlation is eliminated by applying distributivity 4.4 Associativity Associativity is a global transformation which affects the critical path of a design by changing the overall height of the dataow graph. As a result, the mobility and input paths of some operations will be altered in the dataow graph. Associativity is used to reduce the length of the paths with low coverage values and reduced access to registers. Applying associativity in this manner also reduces the folding of operations that result in correlation or conict problems. In addition, reducing the length of the critical paths of a design usually improves the performance of a design by sacricing its area. Associativity-induced owgraph restructurings help equalize the amount ofcoverage and conict in the graph and eliminate the problem areas which result in conicting test paths and increased number of test sessions. An example of how associativity can improve testability is shown in gures 6 and 7 and is described in the results section. 4.5 Strength Reduction Once operations of the same type are bound to the same hardware unit, their inputs can potentially compete for test path access and cause conict, coverage and correlation problems. Strength reduction can help improve these testability problems by changing the node operation types in a dataow graph and eliminating their folding probability. However, since this transformation can only be applied to certain structures (which typically happen infrequently) in design specication, its eect on testability improvement is not expected to be as signicant as the aforementioned transformations. 5 Results Our results are presented in two parts. We rst illustrate the eects of the proposed transformations by using small examples described in detail. This ne grain approach should make it easier for the reader to view restructuring eects. The examples at this level show how transformations aect the conict, coverage and correlation measures of a design. Furthermore, such detailed examples aord the opportunity tomo- tivate the benecial eects of such transformations on the actual testability of the projected designs, rather than on the metric values only. We follow this up with extensive results, cumulatively presented, applied on standard high-level synthesis benchmarks to show how our testability metrics are eected by the restructur- A * B ing process. These benchmarks include the dierential equation and the AR lter. In order to outline the eects of the proposed transformations, we derive results that show the improvements separately on each of the three proposed testability metrics. A greedy heuristic is employed in all three cases to derive results that outline the bene- ts of the proposed transformations. The transformations are guided by the criticality of these metric values and are selectively applied on the ow graph. Since these measures are a reection of test time, the transformations work towards producing an alternative design specication with less test time overhead. Global transformations are applied rst (since their far reaching eects would tend to inuence unpredicatably the improvements of the local transformations, otherwise) and local transformations follow for negrain improvements. This ordering of the transformations enables us to improve the areas in the graph which were either negatively aected by the global transformations or ignored by them. We start by rst discussing ne-grained design examples. Figure 5 illustrates the eect of applying commutativity tonode1 of the design. The metric values for gures 5 and 5 are shown in table 1. The folding of the multiply nodes causes the add and subtract operations to compete for the multiplier's input for access to registers. Reconvergent fanout probabilities for these nodes are due to the fact that even binding decisions can not prevent the multiply module from receiving the adder's output data from both input ports in the nal datapath as shown in gure 5. The metric values for the transformed design (table 1) show afavorable decrease in conict and correlation and a similarly favorable increase in coverage. In the transformed version, the add operations have a high probability of folding into the same physical module and they will not compete for test register access. Commutativity also places all the add nodes at the right input of the multiply nodes and eliminates the probability of reconvergent fanout at the output of the multipliers. *2 Correlation because of I8 I *3 <1 Conflict *2-1 1 I8 *3 3 2 Conflict and Correlation are improved I9 Commutativity Figure 5: Conict and correlation are reduced atthe multiply nodes after restructuring Figures 6 and 7 illustrate the eects of applying associativity. A conguration conict at the <1

5 Node Original Transformed Name DFG DFG Con/Cov / Cor Con/Cov / Cor /0.42/ /1.00/ /0.99/ /0.99/ /1.00/ /1.00/ /1.00/ /1.00/ /1.00/ /1.00/0.00 < /1.00/ /1.00/ /1.00/ /1.00/ /1.00/ /0.99/0.00 AVG 0.28/0.93/ /0.99/0.15 Table 1: Comparison of metrics for gure 5 inputs of the subtracter results in a minimum of two test sessions. The binding and scheduling steps in later stages of synthesis can not prevent this conict if only one subtracter module is to be utilized. Due to this conict, the ADD1 module can not be covered in the rst test path and will need a second test session to be added as shown in gure 6. Applying associativity helps eliminate this conict by altering the input paths of the subtracter and redirecting the output of the ADD1 module. The corresponding metric values are shown in table 2. As is to be expected, restructuring also helps reduce the number of required clock cycles while the area overhead remains the same. 1 R1 I 1 I 2 I 6 I 4 I 3 I /1 R R1 I 1 I 2 0 ADD1 I 6 I 4 I 3 I 7 Figure 7: Performing associativity eliminates con- ict, Datapath requires one test session natives becomes impossible without a computational model. In this section, we show the eects of our transformations on three standard benchmarks. Figure 8 shows the dierential equation dataow graph. After *X4 -X7 -X10 X3 <X6 O6 *X9 X11 1 ADD2 *X4 -X7 -X10 SUB 0 X3 <X6 O6 *X9 DIV 0 X / R1 0 0 ADD2 ADD1 Conflict Figure 6: DFG before restructuring contains con- ict, The corresponding datapath requires two test sessions denoted by the dashed and bold paths Node Original Transformed Name DFG DFG Con/Cov Con/Cov / / / / / / / / / /1.00 =1 0.00/ /1.00 AVG 0.33/ /1.00 Table 2: Comparison of metrics for gures 6 and 7 As we move to larger circuits, tradeo options increase drastically and evaluating all possible alter- SUB DIV Figure 8: Dierential Equation before restructuring, Conict is reduced after transformations applying transformations (gure 8), the metric values for all operations either improved or remained the same. After calculating the metrics for this graph, we can see that node X2 has the highest probability of conict in the graph. This is primarily due to the large number of nodes that can be folded onto X2 and having with a fanout of 1 as one of its input registers. Since does not source any other node, it has to be tested through the module that gets bound to X2 and therefore has a high probability of causing a conguration conict. This is illustrated in gure 9. Similarly, nodex5 has an input Fanout (3) (1) (4) (2) (3) (4) Figure 9: Possible data path for nodes X1 and X2 before restructuring, Same datapath after restructuring has much less conict which can only be tested through the multiplier module which X5 maps to. (1)

6 Figure 8 shows the same dataow graph after applying transformations to optimize for test application time. The amount of conict in the design is signicantly reduced by restructuring the graph. An example of this improvement is illustrated in gure 9 where the datapath resulting from folding X1 and X2 is shown before and after applying associativity. As we can see, the probability ofhaving a con- guration conict is eliminated at the left input port of the module and reduced at the right input. M2 Figure 10: Restructuring eliminates reconvergence Correlation was reduced on nodes X8 and X5 for similar reasons. Figure 10 illustrates the reconvergent fanout at the output of the module in one possible data path that is created by the folding of X8 and X1. The correlation of 's pseudorandom vectors at the input ports of can cause a degradation in test data results. Applying commutativity on node X8 eliminates the probability of creating a reconvergent test path through false paths. The resultant data path after applying commutativity is shown in gure 10. We utilize the AR lter to illustrate how restructuring techniques can help improve coverage throughout a dataow graph. The original dataow graph for the AR lter is shown in gure 11. Associativity was applied in order to improve the coverage in low coverage areas. Figure 11 shows the transformed graph. The coverage values for all highlighted nodes were improved after restructuring the graph. These improvements were done by shortening the paths which contain low coverage values in dierent parts of the graph. Low coverage nodes are the bottleneck operations in the design since their coverage is inversely related to the number of test sessions required. Equalizing the coverage values throughout the graph helps improve the overall accessibility of operations to test registers *3 *4 8 * *20 *21 *22 25 * M2 7 * M2 *2 *3 *4 8 6 * *20 *22 Figure 11: Restructuring increases coverage throughout the AR lter The results for conict and correlation improvements are summarized in tables 3 and 4 respectively. As we can see, the restructuring techniques have resulted in overall improved testability in both benchmarks. Benchmark Original Transformed DIFF EQUATION AR FILTER Table 3: The eects of restructuring on conict Benchmark Original Transformed DIFF EQUATION AR FILTER Table 4: The eects of restructuring on correlation 6 Conclusions We have presented an approach for improving the testability of a design at the behavioral level. A set of testability metrics are used to pinpoint testability problems with an emphasis on test application time and concurrency. Testability improvements were made by using transformations to restructure the behavioral representation and generate semantically equivalent designs with reduced test time overhead. It is essential, if high level synthesis is to achieve wide commercial acceptance, that design aids which help a designer traverse the rich space of semantically equivalent specications be provided, especially for design constraints such as testability which are consuming an ever increasing fraction of design costs. References [1] L. Avra and E.J. McCluskey. High-Level Synthesis of Testable Designs: An Overview of University Systems. In ITC, Test Synthesis Seminar, pages 1{8, [2] A.P. Chandrakasan, M. Potkonjak, J. Rabaey, and R.W. Broderson. HYPER-LP: A System for Power Minimization Using Architectural Transformations. In ICCAD, pages 300{303, [3] S. Chiu and C. A. Papachristou. A Design for Testability Scheme with Applications to Data Path Synthesis. In DAC, pages 271{277, [4] S. Dey and M. Potkonjak. Transforming Behavioral Specications To Facilitate Synthesis of Testable Designs. In ITC, pages 184{193, [5] D.D. Gajski, N.D. Dutt, A.C. Wu, and S.Y. Lin. High-Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, [6] I. G. Harris and A. Orailoglu. SYNCBIST: SYNthesis for Concurrent Built-In Self-Testability. InICCD, pages 101{ 104, [7] R. Karri and A. Orailoglu. Transformation-Based High- Level Synthesis of Fault-Tolerant ASICS. In DAC, pages 662{665, [8] R. Karri and A. Orailoglu. Transformation-Based Register Optimization in High-Level Synthesis. In The Asilomar Conference on Signals, Systems, and Computers, pages 894{898, [9] M. Potkonjak and J. Rabaey. Optimizing Resource Utilization using Transformations. In ICCAD, pages 88{91, [10] K. Thearling and J. Abraham. An Easily Computed Functional Level Testability Measure. In ITC, pages 381{390, [11] M. Vahidi and A. Orailoglu. Testability Metrics for Synthesis of Self-Testable Designs and Eective Test Plans. In IEEE VLSI Test Symposium, pages 170{175, 1995.