Self Test Built-in Plan for Data-Path Functional Units

Transcription

1 Self Test Built-in Plan for Data-Path Functional Units J. A. Quilici Gonzalez*, José Roberto de A. Amazonas**, Marius Strum***, Wang Jiang Chau**** Laboratório de Microeletrônica da EPUSP Av. Luciano Gualberto Travessa 3, no São Paulo SP -Brazil * gonzalez@lme.usp.br, *** strum@lme.usp.br, **** jcwang@lme.usp.br Fax: () Lab. de Comunicações e Sinais da EPUSP Av. Luciano Gualberto Travessa 3, no São Paulo SP Brazil ** jra@lcs.poli.usp.br Fax: () Abstract Given an architecture generated by a High Level Synthesis (HLS) System, the Built-in Self-Test (BIST) strategy consists in inserting Test Pattern Generators (TPGs) and Signature Analyzers (SAs) which will test the hardware blocks as the Functional Units (FUs), for instance. When transforming Data-Path registers in TPGs or SAs, a trade-off must be made on a series of parameters as area overhead, test time and fault coverage. This paper presents an efficient procedure to minimize both testability costs and test application time for the test of FUs, by means of multiple concurrent test sessions and registers sharing. The scheme is based on pre-computed test data, which are stored in the FU library. Results on benchmarks are presented and commented. INTRODUCTION The technological development in recent times has stimulated the production of highly complex and large chips forcing designers to incorporate testability at early stages of the project as one of its key features. The growing interest in high-level synthesis has produced high-level built-in self-test (BIST) synthesis systems such as SYNTEST, RALLOC and SYNCBIST [], whose outcomes are highly testable circuits. Even in such cases, not to mention those circuits synthesized without considerations for testability, the problem of deciding where to insert test registers or which registers must be transformed into test registers is a challenging task. We present a scheme aimed at solving the above problem in respect to the test of FUs in Data-Paths. This work is part of an ongoing research consisting of the development of tools to automatically generate BIST testable circuits along with complete optimized test plans for architectures synthesized by a High-Level Synthesis System. This environment [2] incorporates the concepts proposed by [3, 4, 5, 6 and 7] in what concerns the synthesis of structural testable circuits and minimization of test sessions, and it also extends the BIST strategy by: (i) Optimizing the random test vector generation[8]; (ii) Performing the test of FUs, connections and registers; (iii) Introducing cost functions that allow evaluating the quality of a serial, parallel or mixed test scheme. More specifically, the scheme is of structural offline BIST type and makes use of stored information about pre-tested FUs making it possible to know in advance the number of test vectors necessary to reach the desired fault coverage. This paper presents a procedure to optimize the parallel test plan for all FUs existing in a Data-Path, i.e., to define the set of test registers, assign the FUs to be tested concurrently and the order in which they are tested based in cost considerations. Besides that, we perform an analysis on the results, which showed to be good when applied to most of the benchmarks, confirming the manual simulation obtained in [2 and 9]. 2 RELATED WORKS In a related work[], the authors created a Microarchitectural Synthesis System for Rapid BIST

2 Testing, which addresses appropriately the problem of BIST test time by targeting test concurrency during highlevel and structural synthesis. As an upper bound on the achievable concurrency of the design, it is assumed that all registers have the option to act as CBILBO, which achieves high-test concurrency. In order to reduce area overhead with minimum concurrent testability impact, a substitution process is performed by gradually limiting registers to act only as an Signature Analyzer (SA) or Test Pattern Generator (TPG) instead of CBILBOs. Metrics for concurrent testability estimation was defined in order to drive the design of concurrent test during both behavioral and structural synthesis. The test plan is obtained at the end of the high level synthesis process and, therefore, if the final solution does not satisfy the demands, it is difficult to implement changes in the self-testable RT structure, since modifications must be introduced in the initial behavioral description of the circuit. In another work[], the authors proposed a Hardware-Optimal Test Register Insertion in a circuit considered at gate level, represented by a directed graph G with every cycle included in a strongly connected component (SCC) of G. Having assumed that a CBILBO cell is up to 3.5 times more expensive than a BILBO cell, they obtained results showing that BIST structures with minimum hardware overhead of a CBILBO based approach is still smaller than a BILBO solution, on the assumption that a minimum cost placement for G consists of minimum cost placements for all the SCCs of G. Differently, in our work, the test unit in the directed graph is always a node representing a FU with separate input and output registers, which can be shared with others FUs. Therefore, the use of CBILBOs was discarded and a minimum cost placement must be considered globally. 3 THE BIST STRATEGY In this work, we adopt the strategy of considering Test Register Selection following the High Level Synthesis (HLS), in a separate step, so that one has the option to interfere in only one sphere or in both. In particular, self-loops can be eliminated at the structural level, adding new registers or making new connections to existing ones by means of test muxes. An important feature of our scheme is the option the user has to define the amount of concurrency desired, to cope with the limits of power dissipation in test mode. By offering the means to adjust the amount of subcircuits tested simultaneously one will also be able to evaluate the hardware overhead caused by the test circuitry. The test registers are defined at register transfer level (RTL) in the Data-Path generated or not by a HLS. The circuit is divided into segments with sequential depth equal to one, i.e., each FU must have at least one register for each of its inputs and one for its output. Following this, the test paths also present the same sequential depth, each FU with at least one possible TPG and one SA. The test patterns are generated pseudo-randomly. For each type of FU there is a set of previously gathered test data which are stored in a library. The data reveal the fault coverage obtained by the application of a certain number of test vectors, generated by TPGs and SAs implemented as Cellular Automata (CA) under rule 9 or 5, with an area overhead equally known. One of these libraries, based on single stuck-at fault model, might be as Table, where v CTIME i = i n 2 Table : Functional Units Library FU name TPG Number of Test Vectors Fault Coverage C TIME [9] TPG x -3 TPG x -3 FU 2 TPG x -3 TPG x -3 FU 3 TPG x -3 TPG x -3 FU 4 TPG x -3 TPG x -3 FU 5 TPG x -3 TPG x -3 v i number of test vectors; FC Fault Coverage; n represents the total number of input bits (here, n=6); 4 THE ALGORITHM FC Our algorithm takes as input a netlist at register transfer level (RTL) and proceeds with a Testability Analysis. Once the circuit is ready to receive a BIST circuitry, the program decides which registers might be transformed into a TPG, SA or BILBO. The main steps of our algorithm are: i. Preprocessing, making the circuit suitable to BIST rules; 2. Build a Pair Compatibility Graph of the FUs; 3. Build the Test Status Matrix and call the Cost Function; 4. Apply Minimal Register Allocation Procedure.

3 Step : it includes setting up the databases for TPG/SA and FU libraries analysis, defining the preferential rules for CAs and verifying the necessity to insert multiplexers if some FU is not testable. Fig. shows two ways to turn a non-testable FU into testable, without using CBILBO. Solution : new connection to any of the existing registers; Solution 2: new register. In any case, it is necessary a new mux. 2 modified list scheduling approach [2]. Our algorithm is a constructive one in the sense that it begins with a partial solution, then adds another FU to the existing core, forming a sort of Test Status Matrix, where the number of vertical lines represent the maximum allowed number of parallel test sessions and the horizontal lines define the boundaries of test states. The way resourcesharing conflicts are dealt with can be better understood by means of the Cost Function, shown below: F_COST = COST_HW G_TIME G_ASS. COST_HW takes into account the area changes due to register transformation or register sharing (when two or more FUs are tested under the same CA rule). Fig. : (a) Non-testable FU (b) Testable FU Step 2: it consists of building a compatibility graph, in which each node represents a FU and there is an edge between two nodes whenever the units are test compatible. From Fig. 2 it is possible to know that no more than 3 FUs can be scheduled in parallel, for only 2 FUs are compatible with other 3. In order to reach a maximum of 4 FUs being tested simultaneously, it would be necessary at least 4 FUs which were compatible with other 3. The edge between nodes FU 2 and FU 3 reflects the fact that their compatibility is not complete, i.e., they must share the same TPG, whereas edge between nodes FU 2 and FU 4 means one of them could be tested under rule 9 while the other could be under rule 5. FU 5 FU 4 FU 3 FU 2 Fig.2: Compatibility graph for Data-Path of Fig. 3 Step 3: it refers to Test Session Scheduling. Instead of the traditional greedy approach, we adopted a A_ TPG t ( l + r) A_ TPG COST _ HW = N A_TPG represents area increase due to transformation of three simple registers into test registers, A_TPG, area reduction due to register sharing at left or right side, t assumes values or, depending whether the sharing registers have the same rule or not and N is the total number of registers in the circuit. G_TIME corresponds to the gain resulting from a schedule that may extend or not the overall test duration, compared to the test session if scheduled in series. C _ t _ core + C _ t _ FU _ ref C _ t _ L G _ TIME = C _ t _ ref C_t_core expresses the test time at that stage of scheduling of the most suitable test column found, C_t_FU_ref, the test time of the FU being scheduled, C_t_L, the longest test column and C_t_ref, the test time of the FU with the longest test session, taken as reference. G_ASS takes into account the impact of test sessions with different length, when scheduled in parallel on the nonscheduled tests. G _ ASS = st C _ time( st) Min( Comp _ FU ( st), tr _ left) C _ t _ ref Max _ parallel( st) C_time is the time span of each test state, Comp_FU and tr_left reflects the number of FUs or tracks available at that stage, and Max_parallel is the parallelism left. Based on F_COST the search for the best position of each FU in the Test Status Matrix is carried out. Once a position is found, all registers candidates to be transformed in dual-mode test registers are classified either as TPG9, TPG5 or SA9 for each test status. When a FU have only one option to SA (TPG), this register is excluded from the TPG (SA) candidates list in

4 an iterative way. All possible combinations are considered taking into account the number of independent output path of the current FU. Once all FUs tests are scheduled in the Test Status Matrix, the forth step is implemented. Step 4: those FUs with possibility of sharing the same CAs (not necessarily simultaneously) are submitted to a Minimal Register Allocation Procedure to optimize the global resource sharing for testability, based on a Hardware Cost Function, whose values are taken from a TPG/SA Library, like the one shown in Table 2: TPG/SA name Table 2: TPG/SA Library Rule(s) Number of Transistors Relative Cost Area (µm 2 ) Relative Cost 2 Normal none x 38.. TPG x TPG x 8..8 TPG9/5 9 and x SA x SA x SA/TPG x SA/TPG x SA/TPG9/ TPG5 9 and x The number of transistors and area of each type of register in Table 2 were derived considering the.7µm CMOS technology from ES2. 5 EXPERIMENTAL RESULTS The algorithm was implemented in C++ language and applied to some benchmarks such as DiffEq and Tseng circuits. Since the real FU library is not available yet, we tested the algorithm using the data from Table. Analyzing the results for different number of concurrent test sessions, it can be noted that the determination of the level of parallelism is conditioned by the trade-off between acceptable hardware overhead and test time duration. In some situations it is possible to optimize one with small or no penalty to the other. For the example circuit shown in Fig. 3, the test of all 5 FUs could be initially scheduled in a serial way, with a minimal hardware cost (HC) or a minimal time cost (TC) (Table 3): Table 3: Initial Schedule (Serial) for Arch Serial Test Plan Optimization Minimal Hardware Cost (TC:69; HC:4.48) Minimal Time Cost (TC:6; HC:6.59) Values of HC based on Relative Cost 2 of Table 2 FU-TPG9; FU2-TPG9; FU3-TPG9; FU4-TPG9; FU5-TPG9; FU-TPG9; FU2-TPG5; FU3-TPG9; FU4-TPG5; FU5-TPG9; In order to improve the time cost, two possible solutions are presented. Fig. 4 shows that a reduction of 48% in its time cost is obtained with an increase of 52% in its hardware cost, because more registers must be transformed in CAs Fig. 4: Intermediate Solution Fig. 5 shows that it is still possible to improve time cost (57%) and mitigate hardware cost (46%) with increased parallelism FU 4 FU 5 FU 3 FU FU 4 FU 3 FU 2 FU 5 State State 4 State 5 State : FU 2: FU 3: FU 4: FU 5: : FU 2 : FU 3 : FU 4 : FU 5 : R 3 R 2 R 4 R R 5 R 3 R 5 R R 7 R 4 R 7 R 5 R 2 R 6 R Fig. 5: Solution with Maximum Parallelism R 3 R 2 R 5 R R 6 R 3 R 7 R R 2 R 4 R 9 R 5 R 2 R 6 R R 3 R 2 R R 5 R 7 R 8 R 4 FU2 FU3 FU4 R 2 R 4 R 5 R 9 FU5 R 3 R 7 R R 6 Tseng benchmark (Fig. 6) was synthesized by the High Level Synthesis System MACH[3]. Taken the serial schedule as reference, there is a reduction of 48% in time and increase of 28 % in hardware cost when pairs of FUs are tested simultaneously (Fig. 7). In this first version, testability was considered during HLS, i.e., testability was one of the design constraints. Fig.3: Example circuit with 5 FUs (Arch )

5 2 FU 2 FU 5 8 State : FU 2: R 3 R 2 R 5 R 3 R 3 R 4 R 3 R 2 R 5 R 4 R 4 FU 5: R 5 R 2 R FU 6 FU 6: R R 4 R 2 POR 4 28 FU 2 POR 3 FU 5 POR 2 FU 6 State 4 36 R 3 R 2 R 4 R R FU 5 FU 6 FU 2 Fig. 6: Tseng_t benchmark State State 4 Fig. 7: Solution with Maximum Parallelism FU 5 and FU 6 are not compatible because R 2 must be used as TPG for FU 5 and as SA for FU 6. For that reason, the scheduling of FU 6 can not overlap that of FU 5. In the next version of the Tseng benchmark, testability improvement of the Data-Path was not taken into consideration during the HLS, producing a structure whose testability costs are higher, as shown in Fig. 8 and Fig. 9. : FU 2: FU 5: FU 6: R R 2 R 3 R 3 R 3 R 4 R 2 R 5 R 4 R R R 2 Fig. 9: Solution with Maximum Parallelism Other examples synthesized by the High Level Synthesis System MACH were submitted to our algorithm and produced results summed up in Table 4. Table 4: Examples and Rules Example # FUs # Original Parallel Test Plan Optimization Registers Rule / # FUs Arch / 3 9* / 5* / Tseng_t / 2 9* / 2 DiffEq 4 9 / 2 9* / 2 ArFil_t 3 9 / 9* / 5 / * Indicates non-preferential rule It is assumed that Tseng_t and ArFil_t benchmarks use FUs similar to FU 2, FU 3 or FU 4. Table 5: Results in Area and Timing for Serial and Parallel Optimization Example Time (# vectors) Serial Test Plan Optimization Hardware (cost over # registers) #TPG, #SA, #TPG/SA Parallel Test Plan Optimization Time (# vectors) Hardware (cost over # registers) #TPG, #SA, #TPG/SA Arch ;; ;;3 Tseng_t ;; ;;2 DiffEq ;; ;3; ArFil_t ;3; ;3; 6 CONCLUSION R 3 R 4 R 3 R 5 R 2 R POR 4 FU 2 POR 3 FU 5 POR 2 FU 6 R 5 R 4 R 2 R Fig. 8: Tseng_n benchmark The Parallel Test Plans show that the test time length can almost always be greatly cut making the offline BIST more attractive for critical situations. Given a benchmark, our program is able to find a solution only if the testability criterion established is satisfied. When the problem is a simple self-loop, our program is able to cope with it but in other situations it may only produce a serial solution without changing the architecture. We are now creating new examples, with 5 or 2 FUs to gather information about independent paths to SAs that permits finding one of the good parallel schedules without having to generate intermediate solutions between the serial and maximal parallel number of FUs.

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