SystemVerilog UVM. Student Workbook

Transcription

1 Student Workbook 2017 Mentor Graphics Corporation All rights reserved. This document contains information that is trade secret and proprietary to Mentor Graphics Corporation or its licensors and is subject to license terms. No part of this document may be photocopied, reproduced, translated, distributed, disclosed or provided to third parties without the prior written consent of Mentor Graphics.

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3 Module 1: Course Overview Objectives Why Learn UVM? How This Course Makes Sense of UVM Course Flow Introductions and Expectations Course Labs Examples & Labs Emphasize Scalable Best Practices Module 2: First Look At Objectives Course Glossary Verification Methodologies What is UVM? UVM Evolution UVM as a Complete Methodology What UVM Provides SystemVerilog OOP Techniques in UVM UVM Topology Agent UVM Class Hierarchy UVM Reporting/Messaging Verification Phases UVM Phases Hello World Example I

4 UVM Overview Example Simple Transaction Simple Driver Generating Stimulus An Agent Bundles Protocol Classes Testbench Environment Test Class Packages Running the Test Connecting Testbench and DUT: Dual Top Knowledge Check Configuration Classes The UVM Factory UVM Factory Introduction Viewing Topology Printing Messages in UVM Message Verbosity Message Tips UVM Source Code and Documentation Debugging UVM Testbenches Learning UVM Module 2 Lab: UVM First Look Questa SIM 10.6 Quick Guide Lab Instructions Description of Lab Environment II

5 Knowledge Check Answers Supplemental Information UVM Reporting Module 3: Transactions and Sequences Objectives Transactions and Sequences UVM Terminology and Class Hierarchy UVM Stimulus Built From Sequence Items What's Inside Your Transaction? Sequence Item Coding Styles Transaction Methods Each Transaction Method Calls a Virtual Method Implementing the Transaction do_*() Methods The do_copy() Method The do_compare() Method The convert2string() Method The do_print() Method Pack, Unpack, Record Extended Transaction Classes Best Practices with do_* Methods Knowledge Check - Transactions Building Stimulus From Transactions UVM Sequences Handshaking Between Test/Sequence/Driver Generating Multiple Transactions III

6 Randomized Sequences Complex Sequences Knowledge Check - Sequences Module 3 Lab: Define Transactions and Sequences Lab Instructions Knowledge Check Answers - Transactions Knowledge Check Answers - Sequences Supplemental Information Review: SystemVerilog Class Randomization Review: SystemVerilog Constraints Each Transaction Method Calls Two Virtual Methods Macros When You Want It Now Common `uvm_field_* Macros Field Macro Control Flags Module 4: Sequencers, Drivers, and TLM Objectives Communication Between Components TLM Communication TLM Pull Port Flow Sequencers, Drivers and Interfaces Review: Using SystemVerilog Interfaces The Role of Sequencers and Drivers Example UVM Driver Connecting the Driver and Sequencer Emulation Friendly Drivers IV

7 Handshaking Between Test/Sequence/Driver Associating a Sequence with a Sequencer Knowledge Check Module 4 Lab: Define a Sequencer and Driver Lab Instructions Knowledge Check Answers Module 5: Monitors and Agents Objectives UVM Monitors Monitoring Ins and Outs Capturing Scoreboard and Coverage Collector Values Communication Between Components TLM Analysis Port Flow Monitor Example Whose write() Method? UVM Agents Multiple Agents Active and Passive Agents UVM Testbench With Active and Passive Agents Analysis Port Connections Example: Analysis Ports Knowledge Check Module 5 Lab: Monitors and Agents Lab Instructions Knowledge Check Answers V

8 Module 6: Coverage Collectors Objectives Review: SystemVerilog Functional Coverage Project Coverage Flow UVM Coverage Covering Transactions What Should be Covered? Coverage Collector Example Connecting the Coverage Collector Debugging Coverage Knowledge Check Module 6 Lab: Define a UVM Coverage Collector Lab Instructions Knowledge Check Answers Module 7: Scoreboards and Environments Objectives Review: TLM Analysis Connections Introduction to Scoreboards Scoreboard Progression Scoreboard Storage Copy On Write (COW) Two UVM Scoreboard Examples Scoreboard TLM Communication Ex1: ALU Predictor, Internal to Scoreboard Ex1: Evaluator for the ALU with FIFO Ports for Storage VI

9 Ex1: Scoreboard for the ALU example Ex1: Environment for the ALU example Ex2: Scoreboard with Multiple Analysis Imp Exports UVM Environments An Example UVM Environment Knowledge Check Module 7 Lab: Scoreboards and Environments Lab Diagram Lab Instructions Knowledge Check Answers Module 8: Configuration and Factory Objectives Configurable Test Environments Passing Information Across the Topology The UVM Configuration Database UVM Configuration Database Example Configuration Class Example Configuration Flow Setting Configuration from Command Line Performance Considerations Configuring Sequences Component Arrays Debugging UVM Configuration Database UVM Factory Introduction Creating Objects With the Factory VII

10 Registering Classes in the Factory Factory Override The Benefits of Factory Overrides Module 8 Lab: Configuration and Factory Lab Instructions Supplemental Information The UVM Configuration Database Priority UVM Configuration exists() and wait_modified() Methods Configuring Sequences Without Referring to a Sequencer Viewing the Configuration Database Contents Controlling Tests From the Command Line Printing the Factory Contents Viewing the UVM Testbench Topology Module 9: Tests and Virtual Sequences Objectives UVM Test Class UVM Test Class Example Code Project-Level Base Classes Delaying the End of Run Phase Knowledge Check Review: Test and Sequence Handshaking Controlling Multiple Sequences Virtual Sequences and Running Multiple Sequences Acquiring a Sequencer Handle for a Sequence Sequencer Handle in a Configuration Object VIII

11 Configuration Objects in the Virtual Sequence Project-Level Base Classes Knowledge Check Module 9 Lab: Tests, and Virtual Sequences Lab Instructions Knowledge Check Answers Knowledge Check Answers Supplemental Information Sequencer Handle Connection Approaches Sequence Handle Declarations Sequencer Example The Environment Virtual Sequencer Example The Virtual Sequence Virtual Sequencer Example The Test Module 10: Sequences for Complex Stimulus Objectives Multiple Agents and Sequencers Virtual Sequence Starts Sequences on Both Agents A Virtual Sequence for Multiple Agents Passing Information Into a Sequence Parallel Multiple Sequences on the Same Sequencer Sequencer Arbitration Selecting Sequencer Arbitration Algorithm Setting Sequence Priority Exclusive Sequencer Access Generating Multiple Transactions in a Sequence IX

12 Parallel Sequence Gotchas Sequence Libraries and Hierarchical (Layered) Sequences Driver/Sequence: get_next_item() and get() Feedback to Sequence: Same Transaction Object Feedback to Sequence: Different Transaction Objects Knowledge Check Module 10 Lab: Sequences for Complex Stimulus Knowledge Check Answers Supplemental Information Feedback to Sequence: Driver Analysis Port Sequence Macros Module 11: UVM Register Layer Overview Objectives Advantages of the UVM Register Layer UVM Register Layer Components UVM Register Model UVM Register Models Working with Bus Agents UVM Register Model Hierarchy Software Tools Generate UVM Register Models Register Model Integration UVM Register Values Register Adapter Register Prediction Adding a Register Model to a Test Integrating a Register Model X

13 User-defined Register Tests (Sequences) UVM Register Access Methods Tests with User Defined Register Sequences Predefined Register Test Sequences Test for a Predefined Register Sequence Knowledge Check Module 11 Lab: UVM Register Layer Lab Instructions Knowledge Check Answers Supplemental Information Example Generated Register Example Generated Register Block Module 12: UVM Summary Objectives What is the Other 97% Advanced UVM Techniques XI