Tessent MemoryBIST Shell. Student Workbook

Transcription

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3 Module 1: Introduction to Tessent MemoryBIST Objectives Tessent MemoryBIST Solution Components Tessent MemoryBIST Implementation Memory BIST Hardware: Architecture Comparator Placement Tessent MemoryBIST Operating Protocol Scannable Memory Interface (Optional) Supported Memory Types Key Features Test Algorithms Built-In Standard Algorithms Base Capabilities: Fault Coverage Summary Memory Library File for Each Memory (.tcd_mem_lib) Memory Library Example Hierarchical Bottom Up Flow Advantages Tessent MemoryBIST Block Flow Example: Design Architecture and Clocking Generic Block Architecture Tessent MemoryBIST Flow Prerequisites Tessent Shell Database (TSDB) Typical TSDB Structure (First 2 Levels) Getting Help With Tessent Tools I

4 Accessing Support Center Material Lab Module 2: Standard Memory BIST Flow Objectives Tessent MemoryBIST Flow Tool Invocation Load Design: Contexts and Modes Load Design: System Modes Load Design: Reading Design Netlists Load Design: Reading Libraries Load Design: Elaborating the Design Load Design: Optional Data (after set_current_design) Useful Design Data Reporting Commands Load Design (Review) Specify Requirements: Design Level Specify Requirements: Memory BIST Options Specify Requirements: Memory Instance Options add_inputs_constraints set_attribute_value Specify Requirements: Clocks Specify Requirements: DRCs Specify Requirements: Review Tessent MemoryBIST Flow Create the DftSpecification DFTSpecification: report_config_data II

5 DFTSpecification: display_specification DFTSpecification: Insert Test Logic blocka: Design blocka: DFTSpecification blocka: Post DFTSpecification Processing Block Diagram blockb: Design blockb: DFTSpecification blockb: Block Diagram DFTSpecification: Review Tessent MemoryBIST Flow Extract ICL Patterns Specification Extract ICL and PatternsSpecification Review Tessent MemoryBIST Flow Simulation Validation Basic Flow Review Lab Module 3: Clocks and Clock DRCs Objectives Typical Clocking Network for Memories Defining Clocks Defining and Managing Clocks Option Defining and Managing Clocks Option Add / Define Clocks Clock Gating Cells III

6 Clock Muxes Defining and Managing Clocks Option Clock Divider / ICL Clock Divider / PDL DFT Specification Core: Design Core: DFTSpecification Core: Block Diagram PatternsSpecification Pre-DFT Clock Rules (DFT_C rules) Pre-DFT Clock Rule DFT_C Pre-DFT Clock Rule DFT_C Pre-DFT Clock Rule DFT_C Pre-DFT Clock Rule DFT_C Pre-DFT Clock Rule DFT_C Lab Module 4: DefaultsSpecification and DFTSpecification Objectives Specifications DefaultsSpecification DefaultsSpecification Wrappers DefaultsSpecification: PatternsSpecification DefaultsSpecification: DftSpecification DefaultsSpecification: IjtagNetwork DefaultsSpecification: BoundaryScan IV

7 DefaultsSpecification: MemoryBisr DefaultsSpecification: MemoryBIST DefaultsSpecification: DiagnosisOptions DefaultsSpecification: RepairOptions DefaultsSpecification: AlgorithmResourceOptions DefaultsSpecification: MemoryInterfaceOptions DefaultsSpecifications Editing Options Specification Editing Options Editing in the GUI Editing Using Command Line Command Line / Dofile Lab Module 5: Memory BIST Hierarchical Top Level Flow Objectives Top Level Tessent MemoryBIST Flow Top Level Flow Differences TAP Features BoundaryScan Requirements TAP/Boundary Scan Interface Boundary Scan Cells BoundaryScan Insertion BoundaryScan: Additional Attributes Pin Order File BoundaryScan in DftSpecification Bonding Configurations V

8 BoundaryScan in PatternsSpecification Top Level Tessent MemoryBIST Flow Load Design Specify Requirements Top Level Tessent MemoryBIST Flow DftSpecification Top: Design Top: DFTSpecification Top: Block Diagram Top Level Tessent MemoryBIST Flow Extract ICL Top Level Tessent MemoryBIST Flow PatternsSpecification PatternsSpecification PatternsSpecification PatternsSpecification Tessent MemoryBIST Flow Simulation Validation Manufacturing Patterns Manufacturing Patterns Lab 5: The Memory BIST Hierarchical Top Flow Module 6: Memory BIST Debug Patterns Objectives Debug and Characterization Patterns PatternsSpecification: Default VI

9 Creating Debug Patterns: Design loading Creating Debug Patterns: Design loading Testing a Single Test Step Testing a Single Memory Review: Define Alternate Algorithms in DftSpecification Apply Alternate Algorithms Testing Single Memory and Alternate Algorithm Test Time Multiplier Diagnosis and Debug Identify Failing Memory Memory-Level Only: comparator_location : per_interface Identify Failing Memory: comparator_location : shared_in_controller Identify Failing Memory : comparator_location : shared_in_controller Memory Address Level / Offline Bit Mapping Lab 6: Debug Patterns Module 7: Built-in Self Repair Objectives Tessent MemoryBIST Solution Components: BIRA and BISR Self-Repair Architecture Self-Repair Benefits Repair Analysis Repair Analysis Row OR Column Repair Analysis Row AND Column RedundancyAnalysis Wrapper Repair Analysis Row AND Column VII

10 Fully Autonomous Self-Repair Summary: Manufacturing Repair Flow Support for Power Domains Implementing Repair with Tessent MemoryBIST Load Design / Options DftSpecification: RepairOptions DftSpecification: MemoryBISR Design Rule Checks Implementing Repair with Tessent MemoryBIST DftSpecification Implementing Repair with Tessent MemoryBIST PatternsSpecification Implementing Repair with Tessent MemoryBIST Testbench Simulations FuseBox Fuse Box.tcd_fbox Additional BISR Options Lab 7: Repair Flow Accessing Support Center Material Customer Support Related Courses Module 8: Additional Topics Objectives Synthesis Synthesis / Scan VIII

11 IJTAG (IEEE 1687) Motivation Tessent IJTAG Use Model of IEEE How IJTAG Extends the use of JTAG Operation Example: Accessing Instruments Setup to Enable Access to BLOCK1/TDR Enable Access BLOCK1/TDR Load Data into BLOCK1/TDR Enable Block2/TDR Load Data into BLOCK2/TDR ICL Network Extraction PDL Retargeting Tessent SiliconInsight Overview Motivation Tessent SiliconInsight Desktop in Tessent Shell Tessent SiliconInsight for Memory BIST Interactive Memory BIST Diagnosis Volume ATE memory BIST offline ATE diagnosis Lab IX