Capital. Capital Logic Aero. v Student Workbook

Transcription

1 Capital v Student Workbook 2019 Mentor Graphics Corporation All rights reserved. This document contains information that is trade secret and proprietary to Mentor Graphics Corporation or its licensors and is subject to license terms. No part of this document may be photocopied, reproduced, translated, distributed, disclosed or provided to third parties without the prior written consent of Mentor Graphics.

2 This document is for information and instruction purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made. The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever. MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. U.S. GOVERNMENT LICENSE RIGHTS: The software and documentation were developed entirely at private expense and are commercial computer software and commercial computer software documentation within the meaning of the applicable acquisition regulations. Accordingly, pursuant to FAR 48 CFR and DFARS 48 CFR , use, duplication and disclosure by or for the U.S. Government or a U.S. Government subcontractor is subject solely to the terms and conditions set forth in the license agreement provided with the software, except for provisions which are contrary to applicable mandatory federal laws. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the owner of the Mark, as applicable. The use herein of a third- party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. A current list of Mentor Graphics trademarks may be viewed at: End-User License Agreement: You can print a copy of the End-User License Agreement from: Mentor Graphics Corporation 8005 S.W. Boeckman Road, Wilsonville, Oregon Telephone: Toll-Free Telephone: Website: SupportNet: supportnet.mentor.com/ Send Feedback on Documentation: supportnet.mentor.com/doc_feedback_form Part Number:

3 Module 1: Introduction and Course Overview Abbreviations Used in This Course Overview of Capital Products Overview of Capital Logic Course Introduction to Capital Logic General Terminology Logical (or Functional) Design Wiring Design Example Design Types Getting Started Capital Logic`s User Interface Module 1 Lab: Introduction to Capital Logic Module 2: Creating a Wiring Diagram Design Abstractions Design Flows Creating & Opening Projects Creating Designs Managing Diagrams Grid Preferences Borders Style Sets Adding Devices Associating Graphical Objects with Devices Replacing Symbols I

4 Adding Connectors Pins on Parameterized Objects Pin Properties and Graphics Adding Part Numbers Placing Pins as Group Interactive Plug Maps Manage Inline Connectors Device/Connector Association Object Names in Capital Logic Ring Terminals Saving Your Work Common Actions Module 2 Lab: Exercises #1 & # Moving Objects Wires Conductor Routing Grip Points Moving Conductors Design Rule Checks (DRCs) Report Generation Filtering the Project and Design Views Printing Designs Module 2 Lab: Exercise # Module 3: Introduction to Capital Project Capital Project Concepts II

5 Capital Project Process Getting Started with Capital Project Project Templates System vs. Project Parameters Release Levels Release Level Behaviors Release Level Transitions Design Abstractions Audit Trails Exporting a Project Export / Import Project Close Project Module 3 Lab: Exercise # Naming Conventions Object Type Information Default Names Duplicate Object Names Module 3 Lab: Exercise # Advanced Naming Overview Advanced Naming Counters Creating an Advanced Naming Composition Advanced Naming Condition Applying the Advanced Naming Compositions Batch Generation of Object Names Language Translation III

6 Project Preferences Project Export Facility for Data Corruption Module 3 Lab: Exercise # Module 4: Devices Devices Associating a Library Part with a Device Auto Generation of Connectors on Devices Associating a Connector with a Device Device Pin Generation Device Pin Mating Convert Device Symbol to Parameterized Inline Connectors Modular Connectors Module 4 Lab: Exercise # Properties, Attributes and Graphics Methods of Rapid Property Modification Top-Down vs. Bottom-Up Design Placing Library Parts onto a Diagram Batch Update Library Parts Module 4 Lab: Exercises #2 - # Footprints Device-Side Connector Footprints Generate Harness Connectors Find and Replace Within a Project Search for Objects and Designs IV

7 Module 4 Lab: Exercise # Module 5: Advanced Wiring Highways Conductor Manipulation Conductor Module Codes Splices Center Strip Splices Module 5 Lab: Exercise # Adding Multicores Adding Generic Multicores Associate a Library Part with a Generic Multicore Adding Multicores Directly from Library Multi-Level Multicores Shield Terminations Customizing Multicore Indicators Overbraids Daisy Chained Multicores Backshells Module 5 Lab: Exercises #2 & # Poke Home Wires Assemblies Stacked Pins Configurable Tree Structures Adding Images to Diagrams Block Diagrams vs. Block Views V

8 Module 5 Lab: Exercise # Module 6: Shared Objects Design Wide Objects Join Command Cross-Reference Text Changing the Home Instance Module 6 Lab: Exercise # Concurrency Shared Nets/Wires Shared Objects Shared Objects in Capital Logic Locating Shared Objects in a Project Finding, Navigating & Unsharing Shared Objects Module 6 Lab: Exercise # Shared Objects Pin Management Shared Pin Lists in Capital Project Creating an SPL with a Plug Map Shared Object Names Placing a Shared Device on a Design Shared Inline Connectors Manage Shared Inline Connectors Shared Conductors Module 6 Lab: Exercise # Shared Object Usages Report Revisions of Shared Objects VI

9 Swapping Out Shared Object Revisions Module 6 Lab: Exercises #4 & # Freezing/Unfreezing Shared Objects Composite Symbols as Shared Objects Build Lists Module 6 Lab: Exercise # Module 7: Symbols and Borders Symbol Overview Creating a Symbol Library Elements of a Symbol Symbol Creation Process Changing a Pin`s Name, Attributes & Properties Adding a Property to a Pin Symbol Properties Additional Symbol Tasks Symbol Library Management Module 7 Lab: Exercise # Composite Symbols Composite Symbols in Capital Logic Connectivity in Symbols Module 7 Lab: Exercise # Borders Border Preferences Creating a Border Adding Zones to a Border Symbol VII

10 Inserting Images Properties Intelligent Text Module 7 Lab: Exercise # Module 8: Options Options Overview Defining Options Assigning Options to Designs Mandating Applicable Options Deleting Options Assigning Options to Objects Configurations Filtered Configuration Views Option Combinations Module Code Definition Module 8 Lab: Exercise # Module 9: Design Validation Design Rule Checks Design Rule Checks: Manually Run Design Rule Checks: Background Run Design Rule Checks: Release Design Types of DRCs Defining and Applying Design Rules Module 9 Lab: Exercise # Design Revisions VIII

11 Engineering Change Orders Setting & Tracking ECO Progress Compare Designs To Do Lists Module 9 Lab: Exercise # Signal Tracing Simulation of Electrical Schematics Harness Attributes on Designs Module 9 Lab: Exercises #3 # Module 10: Design Management Design Folder Editing Design Abstractions Auto-Generating a Schematic from a Block Design Module 10 Lab: Exercises #1 & # Storing Circuit Information as a Composite Symbol Copying Designs Within a Project Copying Designs to Another Project Moving Diagram Content Style Sets Releasing Designs Module 10 Lab: Exercises #3 & # Manage Designs & Effectivity Capital Logic and Rules Printing Logic Diagrams Domains IX

12 Design Scope Design & Project Exports/Imports Capital Logic Bridges Module 10 Lab: Exercises #5 & # Module 11: Advanced Logic Effectivity Build Lists and Effectivity Module 11 Lab: Advanced Logic Module 12: Capital AutoView Assist for Logic (CAVAL) Logic Assist Generating Diagrams using Logic Assist Generated Diagrams Dialog Diagrams Tab Component Styling Layout Styling Autoview Query and Generate Bulk CAVAL Processing Module 12 Lab: Exercises #1, #2 & # Module 13: Creating Logical Designs Overview Design Flows Creating Logical Designs Adding Nets Converting Nets to Wires Module 13 Lab: Creating Logical Designs X

13 Appendix 1: Capital Logic's User Interface... A-1 Appendix 2: Object Naming... A-12 Appendix 3: Preferences... A-25 Appendix 4: Shared Objects... A-29 Appendix 5: Capital Bridges... A-38 Appendix 6: Capital Enterprise Reporter... A-40 Appendix 7: Block Diagrams... A-46 Appendix 8: Report Builder... A-48 Appendix 9: Effectivity... A-51 List of Capital Hot Keys (Shortcuts) XI