HyperLynx DDRx Interface Analysis. Student Workbook

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1 HyperLynx DDRx Interface Analysis Student Workbook 2017 Mentor Graphics Corporation All rights reserved. This document contains information that is trade secret and proprietary to Mentor Graphics Corporation or its licensors and is subject to license terms. No part of this document may be photocopied, reproduced, translated, distributed, disclosed or provided to third parties without the prior written consent of Mentor Graphics.

2 This document is for information and instruction purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made. The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever. MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. U.S. GOVERNMENT LICENSE RIGHTS: The software and documentation were developed entirely at private expense and are commercial computer software and commercial computer software documentation within the meaning of the applicable acquisition regulations. Accordingly, pursuant to FAR 48 CFR and DFARS 48 CFR , use, duplication and disclosure by or for the U.S. Government or a U.S. Government subcontractor is subject solely to the terms and conditions set forth in the license agreement provided with the software, except for provisions which are contrary to applicable mandatory federal laws. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the owner of the Mark, as applicable. The use herein of a third- party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. A current list of Mentor Graphics trademarks may be viewed at: The registered trademark Linux is used pursuant to a sublicense from LMI, the exclusive licensee of Linus Torvalds, owner of the mark on a world-wide basis. End-User License Agreement: You can print a copy of the End-User License Agreement from: Mentor Graphics Corporation 8005 S.W. Boeckman Road, Wilsonville, Oregon Telephone: Toll-Free Telephone: Website: SupportNet: supportnet.mentor.com/ Send Feedback on Documentation: supportnet.mentor.com/doc_feedback_form Part Number:

3 Module 1: DDR and HyperLynx Overview... Error! Bookmark not defined. DDRx Basics... Error! Bookmark not defined. Source Synchronous Bus... Error! Bookmark not defined. DRAM and DIMM... Error! Bookmark not defined. Unbuffered vs. Registered... Error! Bookmark not defined. Rank vs. Side... Error! Bookmark not defined. Example: DIMM Density of 1G... Error! Bookmark not defined. Slots and Ranks... Error! Bookmark not defined. Fly-By Topology (DDR3/DDR4)... Error! Bookmark not defined. DDR4 Specific Architecture... Error! Bookmark not defined. Frequency vs. Bandwidth... Error! Bookmark not defined. Data-rate vs. Frequency: Data... Error! Bookmark not defined. 1T vs. 2T Timing... Error! Bookmark not defined. 1T vs. 2T Timing Physical Implementation... Error! Bookmark not defined. Data-rate vs. Frequency: Add/Cmd/Ctl... Error! Bookmark not defined. DDRx Basics: Signal Grouping... Error! Bookmark not defined. Write and Read Cycles... Error! Bookmark not defined. AC and DC Thresholds... Error! Bookmark not defined. DDR3 vs. DDR4 (SSTL vs. POD) Current Flow... Error! Bookmark not defined. DDR3 vs. DDR4 Vcent Comparison... Error! Bookmark not defined. Input Threshold Comparison... Error! Bookmark not defined. Average Vref DDR4 Only... Error! Bookmark not defined. Slew Rate Derating... Error! Bookmark not defined. Write Leveling Clock/Strobe (DDR3/4)... Error! Bookmark not defined.

4 Read Leveling (DDR4)... Error! Bookmark not defined. On-Die Termination (ODT) DDR3... Error! Bookmark not defined. On-Die Termination (ODT) DDR4... Error! Bookmark not defined. On-Die Termination Settings DIMM Example (DDR3)... Error! Bookmark not defined. JEDEC Standard Topologies... Error! Bookmark not defined. Non-JEDEC Standard Topologies... Error! Bookmark not defined. Number of Memory Interfaces... Error! Bookmark not defined. JEDEC Specification Numbers... Error! Bookmark not defined. Help & SupportNet... Error! Bookmark not defined. DDRx Design Methodology Using HyperLynx... Error! Bookmark not defined. Fully Supported DDRx Topologies... Error! Bookmark not defined. Lab 1... Error! Bookmark not defined. Module 2 : Preparing for the DDRx Wizard... Error! Bookmark not defined. DDRx Wizard Overview - LineSim... Error! Bookmark not defined. Required Simulation for a DDRx Bus LineSim... Error! Bookmark not defined. Single-Board Scenario... Error! Bookmark not defined. Multi-board Scenario... Error! Bookmark not defined. DDRx Wizard Overview BoardSim... Error! Bookmark not defined. Required Simulation for a DDRx Bus BoardSim... Error! Bookmark not defined.

5 Lab 2... Error! Bookmark not defined. Module 3: Modeling DDRx Interfaces... Error! Bookmark not defined. Stackups in LineSim... Error! Bookmark not defined. Vias in LineSim... Error! Bookmark not defined. Physical Implementation... Error! Bookmark not defined. IBIS Models... Error! Bookmark not defined. IBIS Model Requirements... Error! Bookmark not defined. Power Aware IBIS Models... Error! Bookmark not defined. S-Parameters... Error! Bookmark not defined. S-Parameters: 2-Port Analytical Relationships... Error! Bookmark not defined. S-Parameters 2-Port Practical Perspective... Error! Bookmark not defined. S-Parameter Quality Metrics... Error! Bookmark not defined. Timing Models... Error! Bookmark not defined. DDR Data and Strobe Timing Parameters... Error! Bookmark not defined. tckactiming Spec to Timing Model Example (Read/Write)... Error! Bookmark not defined. tckctl Timing Spec to Timing Model Example (Read/Write)... Error! Bookmark not defined. tckdqs Timing Spec to Timing Model Example (Write)... Error! Bookmark not defined. tdqsdq Timing Spec to Timing Model Example (Write)... Error! Bookmark not defined.

6 tds/tdh Timing Spec to Timing Model Example (Read)... Error! Bookmark not defined. Completed Table... Error! Bookmark not defined. Lab 3... Error! Bookmark not defined. Module 4 : Verify Interface/Model Setup... Error! Bookmark not defined. Getting Ready for DDRx Wizard... Error! Bookmark not defined. LineSim: Know the Topologies of the Nets... Error! Bookmark not defined. LineSim: Verify the Stackup... Error! Bookmark not defined. LineSim: Verify the Schematic... Error! Bookmark not defined. Verify the Probing Location... Error! Bookmark not defined. BoardSim: Getting Ready for DDRx Wizard... Error! Bookmark not defined. BoardSim: Verify the Design Data... Error! Bookmark not defined. BoardSim: Verify the Stackup... Error! Bookmark not defined. Verify the Probing Location... Error! Bookmark not defined. Lab 4... Error! Bookmark not defined. Module 5: Running the DDRx Wizard... Error! Bookmark not defined. DDRx Wizard: Initialization... Error! Bookmark not defined. DDRx Wizard: Controller... Error! Bookmark not defined. DDRx Wizard: DRAMs... Error! Bookmark not defined. Simulating with Stacked Die DRAMs... Error! Bookmark not defined.

7 DDRx Wizard: IBIS Models... Error! Bookmark not defined. DDRx Wizard: Nets to Simulate... Error! Bookmark not defined. DDRx Wizard: DRAM Signals... Error! Bookmark not defined. DDRx Wizard: Data Strobes... Error! Bookmark not defined. DDRx Wizard: Data Nets... Error! Bookmark not defined. DDRx Wizard: Clock Nets... Error! Bookmark not defined. DDRx Wizard: Addr/Comm Nets... Error! Bookmark not defined. DDRx Wizard: Control Nets... Error! Bookmark not defined. DDRx Wizard: Disable Nets... Error! Bookmark not defined. DDRx Wizard: ODT Models... Error! Bookmark not defined. DDRx Wizard: ODT Behavior... Error! Bookmark not defined. DDRx Wizard: IBIS Model Selectors... Error! Bookmark not defined. DDRx Wizard: Timing Models... Error! Bookmark not defined. Custom Controller Model... Error! Bookmark not defined. Write Leveling (DDR3/4) DQS to CLK... Error! Bookmark not defined. Write Leveling Delay Calculation: DQS to CLK... Error! Bookmark not defined. Write/Read Leveling DQ to DQS... Error! Bookmark not defined. Write and Read Leveling Delay: DQ to DQS... Error! Bookmark not defined. Generating Write/Read Leveling Delay File... Error! Bookmark not defined. Using the " 卼 he table on this page" Option... Error! Bookmark not defined. Using the " the DDR3 Delays external file " Option... Error! Bookmark not defined. DDRx Wizard: Stimulus and Crosstalk... Error! Bookmark not defined. Crosstalk in DDRx Wizard... Error! Bookmark not defined.

8 DDRx Wizard: Simulation Options... Error! Bookmark not defined. AC Thresholds Support (DDR3)... Error! Bookmark not defined. DDRx Wizard: Quality Checks... Error! Bookmark not defined. DDRx Wizard: Report Options... Error! Bookmark not defined. DDR4 Timing and Voltage Verification... Error! Bookmark not defined. Vref and Vcent Values... Error! Bookmark not defined. In the DDR Wizard Eye Mask "Time" Calibration... Error! Bookmark not defined. In the DDR Wizard DRAM Vref ; "Voltage" Calibration... Error! Bookmark not defined. Vref for Controller (Read)... Error! Bookmark not defined. Vref for Controller (Read) (Contd)... Error! Bookmark not defined. Data Bus Inversion DDR4/LPDDR4... Error! Bookmark not defined. Data Bus Inversion DDR4/LPDDR4 Comparison... Error! Bookmark not defined. Power Aware IBIS Models, Why?... Error! Bookmark not defined. Power Aware IBIS Models... Error! Bookmark not defined. DDRx Wizard: Simulate... Error! Bookmark not defined. Common Setup Warnings Voltage Range... Error! Bookmark not defined. Common Setup Warnings Inconsistent Diff Pins... Error! Bookmark not defined. Common Setup Warnings Model Types... Error! Bookmark not defined. Common Setup Warnings Model Selector... Error! Bookmark not defined. Common Setup Warnings Receiver Thresholds... Error! Bookmark not defined. DDRx Wizard: Run Simulation... Error! Bookmark not defined.

9 DDRx Wizard Overview... Error! Bookmark not defined. DDRx Simulation Results Folder; xls: DDR/2/3... Error! Bookmark not defined. DDRx Simulation Results Folder; HTML: DDR/2/3... Error! Bookmark not defined. DDRx Simulation Results Folder; xls: DDR4... Error! Bookmark not defined. DDRx Simulation Results Folder; HTML: DDR4... Error! Bookmark not defined. Constraint Derivation; Design Exploration... Error! Bookmark not defined. Why Use the DDRx Batch Wizard in LineSim?... Error! Bookmark not defined. Creating LineSim Schematics for DDRx Wizard; Multi-Board... Error! Bookmark not defined. Setting up DDRx Wizard for Simulation in LineSim... Error! Bookmark not defined. Setting up DDRx Wizard for Simulation in LineSim... Error! Bookmark not defined. Lab 5 through Error! Bookmark not defined. HyperLynx ョ DDRx Interface Analysis... Error! Bookmark not defined. Quality Checks page... Error! Bookmark not defined. Overshoot and Undershoot ADD, CMD and CTL... Error! Bookmark not defined. Overshoot and Undershoot CLK, DQ, DQS, DM... Error! Bookmark not defined. Overshoot and Undershoot: (Report)... Error! Bookmark not defined. Monotonicity and VIH/L(AC/DC) Limit: (Report)... Error! Bookmark not defined. Slew Rate: (Report)... Error! Bookmark not defined. Differential SI Checks VIHDiff/VILDiff (AC & DC)... Error! Bookmark not defined. Differential SI Checks VIHDiff/VILDiff (AC & DC): (Report)... Error! Bookmark not defined.

10 Differential SI Checks Max VIX... Error! Bookmark not defined. Differential SI Checks Max VIX: (Report)... Error! Bookmark not defined. Differential SI Checks Min VSEH/VSEL... Error! Bookmark not defined. Differential SI Checks Min VSEH/VSEL: (Report)... Error! Bookmark not defined. Differential SI Checks tvac/tdvac... Error! Bookmark not defined. Differential SI Checks tvac/tdvac: (Report)... Error! Bookmark not defined. Differential SI Checks tvac/tdvac: (Report)... Error! Bookmark not defined. Check Round Trip Times Option... Error! Bookmark not defined. Round Trip Time Overview... Error! Bookmark not defined. Syntax for RTT_limits.txt... Error! Bookmark not defined. Round Trip Time: (Report)... Error! Bookmark not defined. Round Trip Time1: (Report)... Error! Bookmark not defined. Round Trip Time2: (Report)... Error! Bookmark not defined. Jitter... Error! Bookmark not defined. tjit... Error! Bookmark not defined. Total Jitter High/Low Pulse Abs Margin... Error! Bookmark not defined. Total Jitter High/Low Pulse Avg Margin... Error! Bookmark not defined. terr... Error! Bookmark not defined. terr: Report... Error! Bookmark not defined.

Constraint Manager for xpcb Layout. Table of Contents

Constraint Manager for xpcb Layout. Table of Contents Table of Contents 2014 Mentor Graphics Corporation All rights reserved. This document contains information that is trade secret and proprietary to Mentor Graphics Corporation or its licensors and is subject