CCICheck: Using µhb Graphs to Verify the Coherence-Consistency Interface
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1 CCICheck: Using µhb Graphs to Verify the Coherence-Consistency Interface Yatin A. Manerkar, Daniel Lustig, Michael Pellauer*, and Margaret Martonosi Princeton University *NVIDIA MICRO-48 1
2 Coherence and Consistency At a high level: Coherence Protocols: Propagation of writes to other cores Consistency Models: Ordering rules for visibility of reads and writes 2
3 Coherence and Consistency Coherence Verifiers Consistency Verifiers Arch. Level 3
4 Coherence and Consistency Coherence Verifiers Consistency Verifiers Arch. Level Coherence and consistency often interwoven µarch. Level 4
5 Coherence and Consistency Coherence Verifiers Ignore consistency even when protocol affects consistency! Consistency Verifiers Assume abstract coherence instead of protocol in use! Arch. Level Coherence and consistency often interwoven µarch. Level 5
6 Coherence and Consistency Coherence Verifiers Consistency Verifiers Ignore consistency even when protocol affects consistency! CCI Assume abstract coherence instead of protocol in use! Arch. Level Coherence and consistency often interwoven µarch. Level 6
7 Motivating Example Peekaboo 7
8 Motivating Example Peekaboo 1. Invalidation before use Repeated inv before use livelock [Kubiatowicz et al. ASPLOS 1992] 8
9 Motivating Example Peekaboo 1. Invalidation before use Repeated inv before use livelock [Kubiatowicz et al. ASPLOS 1992] 2. Livelock avoidance: allow destination core to perform one operation on data when it arrives, even if already invalidated [Sorin et al. Primer] Does not break coherence Sometimes intentionally returns stale data 9
10 Motivating Example Peekaboo 1. Invalidation before use Repeated inv before use livelock [Kubiatowicz et al. ASPLOS 1992] 2. Livelock avoidance: allow destination core to perform one operation on data when it arrives, even if already invalidated [Sorin et al. Primer] Does not break coherence Sometimes intentionally returns stale data 3. Prefetching 10
11 Motivating Example Peekaboo 1. Invalidation before use Repeated inv before use livelock [Kubiatowicz et al. ASPLOS 1992] 2. Livelock avoidance: allow destination core to Individual perform one operation Opt. on No data violation when it arrives, even if already invalidated [Sorin et al. Combination of Opts. Violation! Primer] Does not break coherence Sometimes intentionally returns stale data 3. Prefetching 11
12 Motivating Example Peekaboo Consider mp with the livelock-avoidance mechanism: Core 0 Core 1 x: Shared y: Modified x: Invalid y: Invalid [x] 1 [y] 1 r1 [y] r2 [x] 12
13 Motivating Example Peekaboo Consider mp with the livelock-avoidance mechanism: Core 0 Prefetch x Core 1 x: Shared y: Modified [x] 1 [y] 1 x: Invalid y: Invalid r1 [y] r2 [x] 13
14 Motivating Example Peekaboo Consider mp with the livelock-avoidance mechanism: Core 0 Prefetch x Core 1 Data (x = 0) x: Shared y: Modified [x] 1 [y] 1 x: Invalid y: Invalid r1 [y] r2 [x] 14
15 Motivating Example Peekaboo Consider mp with the livelock-avoidance mechanism: Core 0 Prefetch x Core 1 Data (x = 0) x: Shared y: Modified [x] 1 [y] 1 Inv x: Invalid y: Invalid r1 [y] r2 [x] 15
16 Motivating Example Peekaboo Consider mp with the livelock-avoidance mechanism: Core 0 Prefetch x Core 1 Data (x = 0) x: Shared y: Modified [x] 1 [y] 1 Inv Inv-Ack x: Invalid y: Invalid r1 [y] r2 [x] 16
17 Motivating Example Peekaboo Consider mp with the livelock-avoidance mechanism: Core 0 Prefetch x Core 1 Data (x = 0) x: Modified y: Modified [x] 1 [y] 1 Inv Inv-Ack x: Invalid y: Invalid r1 [y] r2 [x] 17
18 Motivating Example Peekaboo Consider mp with the livelock-avoidance mechanism: Core 0 Prefetch x Core 1 Data (x = 0) x: Modified y: Modified [x] 1 [y] 1 Inv Inv-Ack x: Invalid y: Invalid r1 [y] r2 [x] 18
19 Motivating Example Peekaboo Consider mp with the livelock-avoidance mechanism: Core 0 Prefetch x Core 1 Data (x = 0) x: Modified y: Modified [x] 1 [y] 1 Inv Inv-Ack Request y x: Invalid y: Invalid r1 [y] r2 [x] 19
20 Motivating Example Peekaboo Consider mp with the livelock-avoidance mechanism: Core 0 Prefetch x Core 1 Data (x = 0) x: Modified y: Shared [x] 1 [y] 1 Inv Inv-Ack Request y Data (y = 1) x: Invalid y: Shared r1 = 1 r2 [x] 20
21 Motivating Example Peekaboo Consider mp with the livelock-avoidance mechanism: Core 0 Prefetch x Core 1 Data (x = 0) x: Modified y: Shared [x] 1 [y] 1 Inv Inv-Ack Request y Data (y = 1) x: Invalid y: Shared r1 = 1 r2 [x] 21
22 Motivating Example Peekaboo Consider mp with the livelock-avoidance mechanism: Core 0 Prefetch x Core 1 Data (x = 0) x: Modified y: Shared [x] 1 [y] 1 Inv Inv-Ack Request y Data (y = 1) x: Invalid y: Shared r1 = 1 r2 = 0 22
23 The Coherence-Consistency Interface (CCI) SWMR, DVI, No Stale Data + Expected Coherence = Consistency CCI = guarantees that coherence protocol provides to rest of microarchitecture + memory ordering guarantees that rest of microarch. expects from coherence protocol 23
24 The Coherence-Consistency Interface (CCI) SWMR, DVI, No Stale Data + Expected Coherence = Consistency CCI = guarantees that coherence protocol provides to rest of microarchitecture + memory ordering guarantees that rest of microarch. expects from coherence protocol 24
25 The Coherence-Consistency Interface (CCI) SWMR, DVI, No Stale Data + Expected Coherence = Consistency CCI = guarantees that coherence protocol provides to rest of microarchitecture + memory ordering guarantees that rest of microarch. expects from coherence protocol 25
26 The Coherence-Consistency Interface (CCI) SWMR, DVI, No Stale Data + Expected Coherence = Consistency CCI = guarantees that coherence protocol provides to rest of microarchitecture + memory ordering guarantees that rest of microarch. expects from coherence protocol 26
27 The Coherence-Consistency Interface (CCI) SWMR, DVI, No Stale Data + Expected Coherence = Consistency CCI = guarantees that coherence protocol provides to rest of microarchitecture + memory ordering guarantees that rest of microarch. expects from coherence protocol 27
28 The Coherence-Consistency Interface (CCI) SWMR, DVI, No Livelock + Expected Coherence = Consistency CCI = guarantees that coherence protocol provides to rest of microarchitecture + memory ordering guarantees that rest of microarch. expects from coherence protocol 28
29 The Coherence-Consistency Interface (CCI) SWMR, DVI, No Livelock + Expected Coherence = Consistency CCI = guarantees that coherence protocol provides to rest of microarchitecture + memory ordering guarantees that rest of microarch. expects from coherence protocol 29
30 The Coherence-Consistency Interface (CCI) SWMR, DVI, No Livelock + Expected Coherence = CCI Mismatch Consistency Violation! CCI = guarantees that coherence protocol provides to rest of microarchitecture + memory ordering guarantees that rest of microarch. expects from coherence protocol 30
31 Our Work: CCICheck Static CCI-aware consistency verification Fetch Dec. Exec. SB Lds. SB Fetch Dec. Exec. Mem. L1 L1 Mem. WB L2 WB Coherence Orderings (SWMR, DVI, etc.) Microarch spec Litmus Test 31
32 Our Work: CCICheck Static CCI-aware consistency verification Fetch Dec. Exec. SB Lds. SB Fetch Dec. Exec. Mem. L1 L1 Mem. WB L2 WB Coherence Orderings (SWMR, DVI, etc.) Microarch spec Litmus Test Microarchitectural happensbefore (µhb) graph 32
33 Background: PipeCheck Litmus Test mp Exhaustive enumeration of executions using µhb graphs Cyclic graph forbidden by µarch Acyclic graph allowed by µarch [Lustig et al. MICRO-47] 33
34 Background: PipeCheck Litmus Test mp Exhaustive enumeration of executions using µhb graphs Cyclic graph forbidden by µarch Acyclic graph allowed by µarch [Lustig et al. MICRO-47] 34
35 Background: PipeCheck Exhaustive enumeration of executions using µhb graphs Prior techniques cannot model Litmus Test mp CCI events! Cyclic graph forbidden by µarch Acyclic graph allowed by µarch [Lustig et al. MICRO-47] 35
36 Modelling CCI Events Need to model per-cache occupancy Lazy coherence and partial incoherence (e.g. GPUs) Need to model coherence transitions that relate to consistency (e.g. Peekaboo) 36
37 Modelling CCI Events Need to model per-cache occupancy Lazy coherence and partial incoherence (e.g. GPUs) Need to model coherence transitions that relate to consistency (e.g. Peekaboo) 37
38 4-tuple: ViCL: Value in Cache Lifetime (cache_id, address, data_value, generation_id) cache_id and generation_id uniquely identify each cache line A ViCL 4-tuple maps on to the period of time over which the cache line serves the data value for the address ViCLs start at a ViCL Create event and end at a ViCL Expire event 38
39 4-tuple: ViCL: Value in Cache Lifetime (cache_id, address, data_value, generation_id) cache_id and generation_id uniquely identify each cache line A ViCL 4-tuple maps on to the period of time over which the cache line serves the data value for the address ViCLs start at a ViCL Create event and end at a ViCL Expire event 39
40 4-tuple: ViCL: Value in Cache Lifetime (cache_id, address, data_value, generation_id) cache_id and generation_id uniquely identify each cache line A ViCL 4-tuple maps on to the period of time over which the cache line serves the data value for the address ViCLs start at a ViCL Create event and end at a ViCL Expire event 40
41 4-tuple: ViCL: Value in Cache Lifetime (cache_id, address, data_value, generation_id) cache_id and generation_id uniquely identify each cache line A ViCL 4-tuple maps on to the period of time over which the cache line serves the data value for the address ViCLs start at a ViCL Create event and end at a ViCL Expire event 41
42 ViCL: Value in Cache Lifetime Conventional co-mp timeline (M = Modified, S = Shared) Litmus Test co-mp 42
43 ViCL: Value in Cache Lifetime Conventional co-mp timeline (M = Modified, S = Shared) Litmus Test co-mp 43
44 ViCL: Value in Cache Lifetime Conventional co-mp timeline (M = Modified, S = Shared) Litmus Test co-mp 44
45 ViCL: Value in Cache Lifetime Conventional co-mp timeline (M = Modified, S = Shared) Litmus Test co-mp 45
46 ViCL: Value in Cache Lifetime Conventional co-mp timeline (M = Modified, S = Shared) Litmus Test co-mp 46
47 ViCL: Value in Cache Lifetime Conventional co-mp timeline (M = Modified, S = Shared) Litmus Test co-mp 47
48 ViCL: Value in Cache Lifetime Now with ViCLs Litmus Test co-mp 48
49 ViCL: Value in Cache Lifetime Now with ViCLs Litmus Test co-mp 49
50 ViCL: Value in Cache Lifetime Now with ViCLs Litmus Test co-mp 50
51 ViCL: Value in Cache Lifetime Now with ViCLs Litmus Test co-mp 51
52 ViCL: Value in Cache Lifetime Can model requests, downgrades, etc. Litmus Test co-mp 52
53 ViCL: Value in Cache Lifetime Can model requests, downgrades, etc. Litmus Test co-mp 53
54 ViCLs in µhb Graphs Litmus Test co-mp Use pipeline model from PipeCheck, but add ViCL nodes and edges 54
55 ViCLs in µhb Graphs Litmus Test co-mp Use pipeline model from PipeCheck, but add ViCL nodes and edges 55
56 ViCLs in µhb Graphs Litmus Test co-mp Use pipeline model from PipeCheck, but add ViCL nodes and edges 56
57 ViCLs in µhb Graphs Litmus Test co-mp Use pipeline model from PipeCheck, but add ViCL nodes and edges 57
58 ViCLs in µhb Graphs Litmus Test co-mp Use pipeline model from PipeCheck, but add ViCL nodes and edges 58
59 ViCLs in µhb Graphs Litmus Test co-mp Use pipeline model from PipeCheck, but add ViCL nodes and edges 59
60 CCICheck Toolflow CCICheck µarch specification 1. Instruction Paths 2. Per-Stage Orderings 3. Constraints for Instr. Paths Litmus Tests Path Enum. Constraint Satisfaction Pruning (Cycle Checking) Compare CCICheck Pass/ Fail 60
61 CCICheck Toolflow CCICheck µarch specification 1. Instruction Paths 2. Per-Stage Orderings 3. Constraints for Instr. Paths Litmus Tests Path Enum. Constraint Satisfaction Pruning (Cycle Checking) Compare CCICheck Pass/ Fail 61
62 CCICheck Toolflow CCICheck µarch specification 1. Instruction Paths 2. Per-Stage Orderings 3. Constraints for Instr. Paths Litmus Tests Path Enum. Constraint Satisfaction Pruning (Cycle Checking) Compare CCICheck Pass/ Fail 62
63 CCICheck Toolflow CCICheck µarch specification 1. Instruction Paths 2. Per-Stage Orderings 3. Constraints for Instr. Paths Litmus Tests Path Enum. Constraint Satisfaction Pruning (Cycle Checking) Compare CCICheck Pass/ Fail 63
64 CCICheck Toolflow CCICheck µarch specification 1. Instruction Paths 2. Per-Stage Orderings 3. Constraints for Instr. Paths Litmus Tests Path Enum. Constraint Satisfaction Pruning (Cycle Checking) Compare CCICheck Pass/ Fail 64
65 Path Enumeration Constraint Satisfaction 65
66 Path Enumeration Constraint Satisfaction 66
67 Path Enumeration Constraint Satisfaction 67
68 Path Enumeration Constraint Satisfaction 68
69 Path Enumeration Constraint Satisfaction Unsatisfiable Constraint Invalid Scenario 69
70 Path Enumeration Constraint Satisfaction Unsatisfiable Constraint Invalid Scenario 70
71 Path Enumeration Constraint Satisfaction Unsatisfiable Constraint Invalid Scenario 71
72 Path Enumeration Constraint Satisfaction Unsatisfiable Constraint Invalid Scenario 72
73 Path Enumeration Constraint Satisfaction Cyclic Graph Prune Unsatisfiable Constraint Invalid Scenario 73
74 Case Studies and Results 74
75 Peekaboo Livelock prevention mechanism allows use of stale data Peekaboo edge completes cycle => outcome forbidden Consistency maintained 75
76 Peekaboo Livelock prevention mechanism allows use of stale data Peekaboo edge completes cycle => outcome forbidden Consistency maintained 76
77 Peekaboo Livelock prevention mechanism allows use of stale data Peekaboo edge completes cycle => outcome forbidden Consistency maintained 77
78 Peekaboo Livelock prevention mechanism allows use of stale data Peekaboo edge completes cycle => outcome forbidden Consistency maintained 78
79 Peekaboo Livelock prevention mechanism allows use of stale data Peekaboo edge completes cycle => outcome forbidden Consistency maintained 79
80 Partial Incoherence: GPUs e.g.: mp with membar fences [Alglave et al. ASPLOS15] If fence does not enforce InvCache ordering => no cycle 80
81 Partial Incoherence: GPUs e.g.: mp with membar fences [Alglave et al. ASPLOS15] If fence does not enforce InvCache ordering => no cycle 81
82 Partial Incoherence: GPUs e.g.: mp with membar fences [Alglave et al. ASPLOS15] If fence does not enforce InvCache ordering => no cycle 82
83 Verification Times Runtimes remain reasonable due to intelligent pruning and unsatisfiable constraint detection Subsequent research has used SMT solverbased techniques to run most tests in just seconds! [ASPLOS 2016] 83
84 Verification Times Runtimes remain reasonable due to intelligent pruning and unsatisfiable constraint detection Subsequent research has used SMT solverbased techniques to run most tests in just seconds! [ASPLOS 2016] 84
85 Conclusion CCI verification is critical to correct operation of complex parallel systems CCICheck: static CCI-aware microarchitectural consistency verification Partial incoherence (GPUs), lazy coherence, and more! µhb graphs, ViCLs, and constraint-based enumeration Comprehensive and intuitive µarch modelling Allows designers to build correct systems with greater ease and confidence 85
86 CCICheck: Using µhb Graphs to Verify the Coherence-Consistency Interface Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, and Margaret Martonosi Code available at 86
87 Lazy Coherence (TSO-CC) No eager invalidation of sharers, but InvCache edges model the invalidation of a core s private cache on an L1 miss Thus, TSO is maintained 87
88 Lazy Coherence (TSO-CC) No eager invalidation of sharers, but InvCache edges model the invalidation of a core s private cache on an L1 miss Thus, TSO is maintained 88
89 Constraint-Based Enumeration i3 needs a source for its value L1 ViCL with same address and data 89
90 Constraint-Based Enumeration i3 needs a source for its value L1 ViCL with same address and data 90
91 Constraint-Based Enumeration i3 needs a source for its value L1 ViCL with same address and data 91
92 Constraint-Based Enumeration i3 needs a source for its value L1 ViCL with same address and data => Two possibilities enumerated. 92
93 Constraint-Based Enumeration i3 needs a source for its value L1 ViCL with same address and data => Two possibilities enumerated. 93
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