SP02 to/from DT Interface Test

Transcription

1 1. Hardware SP to/from DT Interface Test 9U VME Track Finder Crate Clock and Control Board (CCB), running under the TTC clock of 4.79 MHz (otherwise the SP PLL will not lock to the CCB clock!) Sector Processor (SP) 9U VME Crate with Transition cage for 4 mm wide cards installed Transition Board (SP_TB) 1 (or ) 5 m cable assembly with angled and straight 68-pin SCSI- plugs (or 4) 5 m cable assemblies with straight 68-pin SCSI- plugs Cross (Test) Board (SP_CB) Other details on cable interconnections can be found at Firmware Use sp_46.evf and vm_fa_dd_46.evf firmware files Details on SP VME and CCB interfaces can be found at References to Tables in the text below are references to tables in the above document 3. DT Interface Loopback Test Test data injected into the LCT data-path from the ONT_FPGA test FIFO pass Local LUT, DT LUT, SP-to-TB backplane connector, and shows up at the output connectors of the Transition Board. External cable connections loop this data back to the Transition Board input connectors through a passive Cross Board. Test data goes through the TB-to- SP backplane connector and is registered in the SP_FPGA Spy FIFO. The above configuration allows validating only one pair of TB output connectors at a time, driving by either F1_FPGA or by F_FPGA. F1_FPGA signals are with S1 (ME1A), S (ME1B) and S3 (ME1C) identifiers, and F_FPGA signals are with S4 (ME1D), S5 (ME1E), and S6 (ME1F) identifiers. The Table test pattern is a so called Running 1 test pattern, when logical one runs from LSB to MSB of the _SFB first frame, making a 1-bit move on every RF clock. Then Running 1 moves through the _SFB second frame, the SP/M/_SFB first frame and finally through the SP/M/_SFB second frame. The DT-to-SP interface is specified only for 5 data lines plus clock, so 6 out of 3 bits in the _SFB format are always zeros. There are 7 zeros in the SP/M/_SFB data format, since second muon clock is used to latch data in the barrel spy FIFO for both M1 and M muons. Using the correspondence between ONT_FPGA test FIFO data and DT interface signals set in Table, the user can generate his own sets of test data, if needed. Page 1 of 6

2 R/w Register Data Comment 3.1 Make connections shown at U-SP_TB_Setup.pdf 3. Write VM/MA/CSR_FCC x1 Put SP under the VME control 3.3 Write FA/MA/CSR_FCC x4 Prepare FA for the DT Loopback test 3.4 Write SP/MA/CSR_FCC x4 Prepare SP for the DT Loopback test 3.5 Write F1/MA/_DT and F/MA/_DT From Table 1 Prepare DT LUTs for Running 1 test 3.6 Write FA/MA/ACT_X x Reset ONT_FPGA Test FIFOs 3.7 Write FA/MX/_TF From Table Prepare F1 and F Test FIFOs for Running 1 test by loading 18 data words from Table into M1, 18 words into M and 18 words into M Write FA/MA/CSR_TFC xa3f Configure ONT_FPGA Test FIFOs to inject data for Write SP/MA/CSR_TFC x Disable SP_FPGA Test FIFOs 3.1 Write VM/MA/CSR_SFC xa Enable spying on Inject Test Patterns 3.11 Write SP/MA/CSR_SFC x4f Configure SP_FPGA Spy FIFOs to record data for Write SP/MA/CSR_AFD x Set Additional DT Data Delay to zero 3.13 Write SP/MA/ACT_X x4 Reset SP_FPGA Spy FIFOs 3.14 Write VM/MA/ACT_FCC xbc Inject test pattern 3.15 Read CSR_SFB and SP/M/CSR_SFB 3.16 Read _SFB and SP/M/_SFB Expect xa Expect Data shown in last two columns of Table Check how many data words the Barrel Spy FIFO is holding Read back Spy FIFO data, number of readout words should be equal to the CSR_SFB data in the previous step Table 1: DT LUT data for Running 1 Loopback test. Address Range (hex) Addresses (dec) Data x - x7fff 3768 x x8 xffff 3768 x1 x1 x17fff 3768 x x18 x1ffff 3768 x4 x x7fff 3768 x8 x8 xffff 3768 x1 x3 x37fff 3768 x x38 x3ffff 3768 x4 Page of 6

3 x4 x47fff 3768 x8 x48 x4ffff 3768 x1 x5 x57fff 3768 x x58 x5ffff 3768 x4 x6 x67fff 3768 x8 x68 x7ffff 9834 x Total 5488 Table : ONT_FPGA Test Data and SP_FPGA Spy Data for Running 1 Loopback test. _TF _TF _TF _SFB SP/M/ _SFB ME_S MB1A x1 1 x CSC_ID= _PHI1 _Q ME_S MB1A x x3 CSC_ID=3 _PHI _Q1 ME_S MB1A x4 3 x4 CSC_ID=4 _PHI3 _Q x4 Q=8 ME_S1 MB1A x1 _ETA _PHIB 1 x8 Q=1 ME_S1 MB1A x _Q _PHIB1 1 x1 Q= ME_S1 MB1A x4 _Q1 _PHIB 1 x Q=4 ME_S1 MB1A x8 _Q _PHIB3 ME_S MB1A x1 x1 _PHI _PHIB4 ME_S MB1A x1 x5 CSC_ID=5 _PHI4 _FL ME_S MB1A x x6 CSC_ID=6 _PHI5 _CAL x1 _PHI _PHI x1 Page 3 of 6

4 _TF _TF _TF _SFB SP/M/ _SFB x CSC_ID= _PHI1 _PHI1 x x3 CSC_ID=3 _PHI _PHI x4 x4 CSC_ID=4 _PHI3 _PHI3 x8 x5 CSC_ID=5 _PHI4 _PHI4 x1 x6 CSC_ID=6 _PHI5 _PHI5 x x7 CSC_ID=7 _PHI6 _PHI6 x4 x8 CSC_ID=8 _PHI7 _PHI7 x8 x9 CSC_ID=9 _PHI8 _PHI8 x1 xa _PHI9 _PHI9 x xb 1 _PHI1 _PHI1 x4 xc _PHI11 _PHI11 x8 ME_S MB1A x7 CSC_ID=7 _PHI6 _ x1 ME_S MB1A x8 CSC_ID=8 _PHI7 _1 x ME_S MB1A x9 CSC_ID=9 _PHI8 _BC x4 ME_S MB1A xa _PHI9 _CLK x8 ME_S3 MB1D x1 xc _PHI11 _Q x4 Q=8 ME_S3 MB1D x _ETA _Q1 x8 Q=1 ME_S3 MB1D x4 _Q _Q x1 x7 CSC_ID=7 _PHI6 _PHIB Page 4 of 6

5 _TF _TF _TF _SFB SP/M/ _SFB x x8 CSC_ID=8 _PHI7 _PHIB1 x4 x9 CSC_ID=9 _PHI8 _PHIB ME_S3 MB1D x8 xa _PHI9 _PHIB3 ME_S3 MB1D x1 xb 1 _PHI1 _PHIB4 x1 Q= ME_S3 MB1D x1 _Q1 _FL x Q=4 ME_S3 MB1D x _Q _CAL ME_S MB1D xb 1 _PHI1 _PHI x1 ME_S MB1D xc _PHI11 _PHI1 x 1 x4 Q=8 ME_S MB1D _ETA _PHI x4 1 x8 Q=1 ME_S MB1D _Q _PHI3 x8 1 x1 Q= ME_S MB1D _Q1 _PHI4 x1 1 x Q=4 ME_S MB1D _Q _PHI5 x x1 _PHI _PHI6 x4 x CSC_ID= _PHI1 _PHI7 x8 x3 CSC_ID=3 _PHI _PHI8 x1 Page 5 of 6

6 _TF _TF _TF _SFB SP/M/ _SFB x4 CSC_ID=4 _PHI3 _PHI9 x x5 CSC_ID=5 _PHI4 _PHI1 x4 x6 CSC_ID=6 _PHI5 _PHI11 x8 ME_S1-3 MB1D x4 x1 ME_S1-3 MB1D x 1 _1 _1 x ME_S1-3 MB1D x8 BC _BC _BC x4 4. SP -> DT Test Inject LCTs A slight change in the SP configuration is required to generate LCT data. - Local PHI LUT should be loaded with real mapping table - Global DT LUT should be loaded with real mapping table - SP/MA/CSR_FCC should be loaded with x - depending on whether [:1] and BC timing bits are required by DT logic along with the LCT data, FA/MA/CSR_FCC either may stay at x4 or be reset to x. Page 6 of 6

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