LVL1 e/γ RoI Builder Prototype

Transcription

1 LVL e/γ RoI Builder Prototype RoI / s matching and zero suppression Receiver RoI VME Receiver RoI Control Receiver RoI S-Link Interface Receiver Output - LVL / Supervisor RoI Builder discussion - Verilog/VHDL model - Check with existing data sets Y.Ermoline 9 ATLAS Trigger/DAQ Workshop at Marseille

2 LVL e/γ RoI Data Collection Cluster processor crate # ROC LA Read-Out Merger ASICs (Interface to RoI Builder) Read-Out ASICs 3 ASIC3 s ASIC2 s ASIC s ASIC s ASIC RoI flags ASIC RoI flags #2 #3 #4 CTP ASIC3 RoI flags ASIC2 RoI flags no zero-suppression: 6x3 32-bit words (.6 MHz) RoI Builder ~5 32-bit words (.6 33 MHz) S-Link Crate//ASIC numbering (possible) RoI Builders CTP e/γ ASIC 24 Crate eta ASIC Crate 2 phi RoI Message Builder Crate 3 Crate 4 ASIC 5 RoI Processor ASIC 255 Y.Ermoline ATLAS Trigger/DAQ Workshop at Marseille

3 LVL e/γ Trigger Crate Layout (RoI Data) 4 Cluster processor crates RoI Data 6 CP modules (s) per crate Interface to RoI Builder 2 3 Cluster processor module (, 64 in total) 4 CP ASICs (256 in total) 4 x Trigger s ( 32-bit word) 4 x 6-bit RoI flags (2 32-bit words) Read-Out ASIC Read-Out ASIC (no zero-suppression, fixed number of words) 96 bits 3 x 32-bit words Pipeline RO I/F ASIC3 s ASIC2 s ASIC s 7 ASIC s ASIC RoI flags ASIC3 RoI flags ASIC RoI flags ASIC2 RoI flags Clock LA Control (zero-suppression, variable number of words) Possible format: bit Trigger - RoI flags ASIC s ASIC Address ASIC s ASIC Address RoI Address 2 RoI Address RoI Address 4 RoI Address 3 Y.Ermoline 7 ATLAS Trigger/DAQ Workshop at Marseille

4 Primary / Secondary RoI Algorithm Input: (2+)-bit list (RoI coordinates + Trigger s) CTP decision word after mask and prescaler CTP decision table (thresholds and multiplicity) LUT Output: (2+)-bit list (RoI coordinates + P/S flag) Algorithm: For each RoI For each Trigger if LUT is P/S flag = /* Primary RoI */ Possible implementation: RoI coordinate 2 Trigger s CTP decision word LUT bit-wise AND unary reduction OR CTP decision table RoI coordinate P/S flag Y.Ermoline 6 ATLAS Trigger/DAQ Workshop at Marseille

5 Trigger s RoI Flags ASIC255 ASIC24 ASIC24 ASIC255 ASIC3 ASIC5 ASIC6 ASIC ASIC6 ASIC ASIC3 ASIC ASIC # ASIC # Control 2 + RoI coordinates + Trigger s Y.Ermoline 5 ATLAS Trigger/DAQ Workshop at Marseille

6 Trigger hits / RoI flags matching Algorithm Input: Output: 6x6 -bit maps (Trigger s) or -bit lists (Trigger s coordinates) 64x64 -bit map (RoI flags) or 2-bit list (RoI flags coordinates) (2+)-bit list (RoI coordinates + Trigger s) Algorithm: 2 3 RoI flags For each -map For each 2x2 s window For each RoI flag if RoI flag within top-right 3x3 = else if RoI flag at the bottom edge = OR else if RoI flag at the left edge = OR 2 else (ROI flag in the corner) = OR OR 2 OR 3 Possible implementation: RoI flags 6 ASIC number 4 RoI coordinates, 2, 3 Control Trigger Possible parallelism: - -maps Trigger maps - 2x2 windows (or 6 RoI flags) 6 2x2 windows (circle in phi) Y.Ermoline 4 ATLAS Trigger/DAQ Workshop at Marseille

7 LVL e/γ Trigger hits / RoI flags matching Single RoI flag - unique RoI flag - Trigger s assignment Multiple RoI flags - ambiguous RoI flag - Trigger s assignment RoI flag (. x.) Trigger (.4 x.4) => Assign to each RoI flag all Trigger s All primary RoI are flagged as primary Secondary RoI may be flagged as primary (a few percent) Primary / Secondary RoI classification LVL Trigger Menu at L= 33 (example) LVL MU6 LVL EM LVL EM2I LVL EM5I + EM5I LVL TAU LVL J LVL J5 + J5 + J5 LVL ME CTP information - decision table (thresholds and multiplicity) - decision (after mask and prescaler) => Primary/Secondary flag to RoI Y.Ermoline 3 ATLAS Trigger/DAQ Workshop at Marseille

8 LVL e/γ Trigger and RoI eration LVL e/γ Trigger Window Algorithm Window Tower LVL e/γ RoI Window Algorithm RoI Tower.4 x.4 Em Cluster. x.2 Em Isolation Had Isolation.3 x.3 Local Maximum AND > RoI threshold Trigger/RoI Window Coexistence Trigger and RoI eration Within Cluster Processor (CP) ASICs CP ASIC processes 6 overlapping Trigger/RoI windows Inputs from a 7x7 trigger tower region sets of thresholds: cluster, em isolation, had isolation Output: Trigger s (one per threshold s set, 6 windows logical OR) (4 x 4) bit RoI flag s map Used for isolation only Used in clusters but not as RoI Used in clusters and as RoI: A single shower may produce Trigger and ROI flag in different ASICs Complete system (496 towers, 256 ASICs): 256 -bit Trigger s ( 6x6 -bit maps / 6x6 -bit map) 496 -bit RoI flags ( 64x64 -bit map) Y.Ermoline 2 ATLAS Trigger/DAQ Workshop at Marseille

9 LVL/LVL2 Interface LVL Muon CTP Calorimeter e/γ jets τ E T RoIs LVL2 6 sources: - Muon trigger to CTP interface - Central Trigger Processor (CTP) - Electron/photon trigger - Jets trigger - Hadron trigger - Missing E T trigger LVL provides RoI information to the LVL2 Primary RoIs - contributed to the LVL decision Secondary RoIs - did not contribute Ref.: ATLAS note DAQ-No-73 (A. Watson) Y.Ermoline ATLAS Trigger/DAQ Workshop at Marseille