Loop Filter Optimization

Transcription

1 Loop Filter Optimization Dean Banerjee Deborah Brown Khang Nguyen 1 This presentation is about PLL loop filter optimization. We will discuss different techniques that can be used to find the best theoretical optimal solution for the design of your loop filter. This is not to imply that there is no bench work involved, however. Obtaining the best results theoretically will minimize the amount of bench work that will be needed. If things are not optimized in theory, or they do not work in theory, then you can almost guarantee that they will not work in practice. If things work in theory, they may or may not work in practice. 1

2 Overview Introduction PLL Loop Filter Design Issues Common Method for Loop Filter Design and Optimization New Approach for Loop Filter Design and Optimization Page 2 We are going to discuss several loop filter design issues, how to pick out loop filter parameters, and two different approaches to design a loop filter The first approach to designing a loop filter is commonly used in the field. In this approach, you choose your filter parameters, design a loop filter, see if the design works, and then tweak your design by performing multiple iterations. The second approach is very similar to the first approach. However, we let software perform the iterations needed to tweak the design to reduce the amount of time spent in designing the loop filter that meets the performance criteria you want. 2

3 Loop Filter Design Issues Spur Level vs. Lock Time Tradeoff Loop bandwidth Phase margin Pole ratios Filter Order Page 3 The first loop filter design issue is the classical spur level vs. lock time tradeoff. Common design practices indicate that the loop bandwidth is the most relevant design parameter. In a second-order filter, for every two-fold increase in the loop bandwidth, you get a 12 decibel increase in the reference spur, but your lock time is reduced by half. So there is the classic tradeoff with this parameter. How do you consider this tradeoff in an optimal way? There is another parameter called the phase margin, which is probably more familiarly described as the damping factor. Phase margin relates to the damping factor. How do you choose the most optimal phase margin? We will talk about that a little bit later. Next, we consider pole ratios. A loop filter is derived from a transfer function and will have zeros and poles. By choosing the ratio of these poles, you have an idea of how much benefit you are getting from the filter. The fourth parameter we consider is filter order. Sometimes you may think that you are getting benefit from always using high order filters, but you are really just fooling yourself and putting out more components than are necessary. 3

4 Loop Bandwidth Smaller Larger Loop Bandwidth Loop Bandwidth Lower Spurious Noise Faster Lock Time Page 4 The classical issue with the loop bandwidth is that a smaller loop bandwidth implies that the reference spurs are smaller, yet a larger loop bandwidth implies a faster lock time. You always have to figure out how do you deal with this tradeoff. How do you pick loop bandwidth so that you have just the right balance? Loop bandwidth is a firstorder effect. There are parameters such as phase margin, pole ratios, and other factors that have a smaller effect. 4

5 Phase Margin Relates to stability of system Typically ranges from 40 to 55 degrees Higher phase margin results in more stable system, but if too high can cause increased lock time For minimum RMS phase error designs, 50 degrees is a good starting point Page 5 The phase margin relates to the stability of the system. A phase margin of zero degrees implies perfect instability. Consider a transfer function G/(1 + GH). With a phase margin of zero, the denominator of this transfer function becomes zero and the function becomes unstable. Choosing the phase margin that is too low does results in instability. Choose a higher phase margin results in less ringing in your system. However, at some point the higher phase margin will actually slow down your system. What is the right phase margin? Typically degrees is where that optimal phase margin lies. At this optimal point, the phase margin typically gives the fastest possible lock time for a given spur level. But again, the 40 or 55 degrees can depend on the application. This range can change depending on the application. Another thing to consider with the phase margins is RMS phase error. For minimum RMS phase error, 50 degrees is a good rule of thumb as a starting point. You are looking at how flat the loop filter is. You want something flat, but not too flat, or else you are going to make the lock time excessively long. 5

6 Pole Ratios T3/T1 ratio and T4/T3 ratio Higher pole ratios Less spurious noise Decreases value of highest order capacitor Watch out for VCO input capacitance Page 6 In this section, we talk about pole ratios. Application note 1001 refers to a parameter called attenuation. May older programs use this parameter. One often asked is, How come EasyPLL does not agree with these application notes? EasyPLL is National Semiconductor s free online PLL design and simulation software that can be accessed at wireless.national.com. By choosing just the attenuation value, you can really fool yourself. You can just say, Why don't I put a million decibels of attenuation?. What does that really mean? When you increase the value of this attenuation, you get a narrower loop bandwidth. You get a loop bandwidth different than what you designed for. In the case of EasyPLL, we use a parameter called pole ratio. The pole ratio gives you an idea of how close the poles are in. The pole T1 is always going to be in your filter. In a third-order filter we have a pole called T3 and in a fourth-order we have a pole called T4. For the lowest possible spurs, you want those poles right on top of each other, theoretically. However, if you do that, that implies that one of your resistors will approach infinity and the other will approach zero. The capacitor in front of the VCO will also approach zero. So you have this tradeoff. One question is How do I get a reasonable size of capacitor yet still get a reasonable amount of attenuation from my filter? And of course the other question is, Does it really do any good to do a third-order filter at all?. Now one other thing we should mention about these pole ratios is that when the resistor values in the loop filter get larger, they can contribute phase noise. Usually this happens at the point of the loop bandwidth or outside the loop bandwidth. In conclusion, the pole ratios are giving you an idea of the degree of attenuation of the loop filter. If the pole ratio in a loop filter is zero, you actually end up with a lower order filter. For instance, if I had a third-order filter and choose T3/T1 ratio equal to zero, it is actually a second-order filter. If I choose T3/T1 = 100%, then that is the maximum possible benefit I can get from that third order filter. 6

7 Filter Order Benefits of higher filter order Lower spur levels Drawbacks of higher filter order More passive components More resistor noise due to added resistors VCO capacitance more likely to cause distortion Page 7 So what are the benefits of the using a higher order loop filter? The main benefit is lower spur levels. If you consider the Bode plot, the transfer function rolls off at a faster rate for a higher-order loop filter resulting in lower spur levels. A higher order loop filter, however, has some drawbacks. First of all, it has more passive components. Secondly, the added resistors add noise at or outside the loop bandwidth. This may or may not be a big deal. Third of all, the VCO capacitance is likely to cause distortion. How does the VCO capacitance cause distortion? VCOs have input capacitance. This capacitance adds in parallel to the highest order capacitor in your loop filter. I have never seen a VCO where they have actually given guaranteed range for the input capacitance. Since you have no guarantee, you don't know how much the VCO input capacitance varies. It will certainly vary over frequency. Basically, the idea is you want to put a capacitor next to the VCO input capacitance such that the VCO input capacitance does not impact your loop filter. So if you have a VCO input capacitance of 10 picofarads and I put 200 picofarads next to it, then the VCO input capacitance is not going to have a large impact even if it varies. That is one of the reasons why you would not always want to use the highest order filter. The other reason is that the resistor noise increases with more components. And then you always have to ask the question, Is the higher order filter really providing any benefit at all, or is it half a decibel?. Is it really worth going through all this just for half a decibel of benefit? 7

8 PLL & VCO Selection PLL Selection Covers the frequency range Divide Ratios supported by N and R counters Why would I choose one part over another? VCO Selection VCO Gain VCO input capacitance Adds in parallel with highest order loop filter capacitor. Can cause problems if highest order loop filter capacitor is too small. Phase Noise vs. Tuning Range Tradeoff Page 8 The first thing you want to do when you design a PLL system is pick a PLL. The PLL is the most important part in your system. The main factor in deciding which PLL to use is whether it covers the appropriate frequency range. Obviously if the PLL does not operate in the frequency range you want, then it is no good. The other factor you want to consider are the counters -- the N counter and the R counter. You want to see if these counters can support the divide ratios. In almost all PLLs, the N counter has either a dual modulus or quadruple modulus prescaler. The counters do not support every possible divide ratio. Even if you select the PLL that supports the proper frequency range and has counters that will work the ratios you need, you still have to ask, Why would I pick one PLL over another? For instance, one selection rule that would make sense is if you have parts with similar features, you always should choose the lowest frequency part if it is from the same family or type of PLL. These are all things that the EasyPLL program is designed to help you with. In VCO selection, there are some important parameters. VCO gain is a very critical parameter. If you have a different VCO gain, the components in your loop filter would change in order to keep the same loop bandwidth. VCOs also have an input capacitance with them and you have to be aware of this. The third factor to consider is the phase noise vs. tuning range tradeoff. Some VCOs can tune a very large range. Many of them require 30 volts to do that and maybe you do not have 30 volts available. Most of the applications I have seen do not use active filters. However, in cases where you need a wide tuning range, you have to do one of two things -- supply more voltage to the VCO or sacrifice the phase noise. So if you have a VCO with a narrower tuning range, it typically has better phase noise performance. This is why VCOs tend to come in very application specific types of situations. VCOs typically may have 100 megahertz or 150 megahertz of tuning range. On the other hand, a PLL, for instance an LMX2330, can go all the way from 500 megahertz 8

9 Common Method for Loop Filter Design and Optimization Choose arbitrary values for filter parameters, calculate filter components, and then analyze. If loop filter does not meet lock time and spur requirements, then adjust filter parameter values and re-optimize. System Requirements Frequency Range Channel Spacing N Counter Value Part Selection Filter Components System Performance Filter Parameters Charge Pump Gain VCO Gain VCO Input Capacitance C1, C2, C3, C4 R2, R3, R4 Lock Time Spur Requirement Loop Bandwidth Phase Margin Pole Ratios Filter Order Page 9 In this section, we discuss the Common Method for loop filter design. To begin with, you have to decide a frequency range, channel spacing, and N counter value. First, you have to ask OK, what's my channel spacing and output frequency? Then you have to ask, What part am I going to use and what loop bandwidth do I choose? What phase margin, what pole ratio, and what filter order do I choose? The idea here is, in the past, a lot of people would say, "Oh, I just know 10 kilohertz is what I need for this application, or this is a good guess." There are many rules of thumb to pick loop bandwidth, phase margin, pole ratio, and filter order. These rules get you close but not exactly right. We are in the day now where computer speed is a dollar a megahertz or so. We really should be taking advantage of the high power of computers in our design. In the Common Method, you basically pick a loop bandwidth, phase margin, filter order, pole ratios, and then you go off to choose a charge pump gain. The highest charge pump gain is usually the best performance in terms of phase noise. The only reason you would not use the highest charge pump gain is if your capacitors became unrealistically large or you wanted to take advantage of a fast lock in the application. You then obtain the VCO gain and the VCO input capacitance. The VCO input capacitance is not really a critical design parameter with the filter -- it is more of a sanity check. You can subtract it away from your highest order capacitor, but the real idea is that you should not be putting your capacitor next to your VCO -- it should be much larger than the VCO input capacitance. From there, you calculate your filter components. Once you get your filter components, you say, OK, I'm going to the bench, I'm going to measure the lock time, reference spurs, and phase noise. Then you would have an idea on how your loop filter performs. After measuring the performance, you would say whoops, I got a different loop bandwidth than I want, or the spur level is not what I want. You then go back and you redesign, calculate another filter, go back and redesign that, calculate another filter, and eventually you get something reasonably close to what you want. 9

10 Disadvantages of Common Method Iterative Process Very time consuming Very tedious Based on trial and error Does not always achieve the optimal solution Page 10 The disadvantage of the Common Method is that it is an iterative process, very time consuming, very tedious, and based on trial and error. Of course, there will be some trial and error in loop filter design. However, we should try to minimize it as much as possible. The other problem with this iterative process is that it does not always achieve the optimal solution. You could go through these iterations two or three times and then decided that you the the loop filter that you want, but you are not going to go through it a hundred times. The disadvantage of the Common Method is that you are not taking your simulation results and feeding it back into your design because this takes a lot of work. Poll Question: How many times do you design your loop filter before you're satisfied? Answer: Three -- it looks like most people are saying about three times. 10

11 New Approach for Loop Filter Design and Optimization Give me the best loop filter that meets my lock time and spur level requirements. System Requirements Frequency Range Channel Spacing N Counter Value Part Selection Filter Parameters Filter Components System Requirements Charge Pump Gain VCO Gain VCO Input Capacitance Loop Bandwidth Phase Margin Pole Ratios Filter Order C1, C2, C3, C4 R2, R3, R4 Lock Time Spur Requirement Page 11 This section describes the New Approach to loop filter design and optimization. This new approach is actually internally very similar to the Old Method. The difference is that the new approach reduces the number of iterations you have to go through. Here, you give a frequency range and a channel spacing. The N counter value is the consequence of these two parameters. You then come up with system requirements, specifically lock time and spur gain. Spur gain relates to spur level. It is proportionate to the spur level but not exactly equal to the spur level. Once you have an idea of these requirements, you go and select your parts which include your PLL and VCO. Your charge pump gain and VCO gain will then be determined. The difference in the New Approach is that EasyPLL goes and designs the loop filter filter for you. It incorporates the lock time and spur requirements you have selected and interates hundreds of time using an intelligent algorithm to converge on the best solution. Then it comes out with filter components for you. Once you have these filter components, you can sit back and say, Theoretically this is the optimal solution. That is the difference. You may find out that after you build your loop filter, the VCO gain that you specified or the manufacturer specified is different from that of the actual VCO. There is typically a fair amount of variation there. The VCO gain tends to change at higher frequencies. But at least you know in theory that you have tackled this problem correctly. 11

12 Four Easy Steps Using the New Method System Requirements Filter Parameters Filter Components Analyze Define System Level Parameters Determine Loop Filter Design Parameters from System level parameters Determine Loop Filter Components from Loop Filter Design Parameters System Level Performance from Loop Filter Components Page 12 The four easy steps to using the new method, as described in the previous section are System Requirements, Filter Parameters, Components, and then Analyze. In System Requirements, you determine your lock time and spur performance requirements. In Filter Parameters, the loop filter parameters are chosen. In Filter Components, the loop filter components are calculated. In Analyze, you view the actual performance of the loop filter. 12

13 Introduction to EasyPLL Allows you to: Specify your PLL system requirements Choose the best parts that meet your requirements. Determine your Loop Filter Components Analyze the simulation results Examine various wave forms Change parameters in any order Order a Custom Eval Board when you are done. Page 13 In this section, we going to introduce you to EasyPLL. EasyPLL basically allows you to set your system requirements (i.e. lock time or spur requirement), determine your loop filter's components, and then do very good simulation. With the simulation, you can examine various types of waveforms. A nice feature is that you can also change the parameters around and have an idea of how the performance will change. A new feature we have here is you can actually order an evaluation board for the low, low price of $99.95 plus shipping, and we'll actually build a custom board for you. There are a limited number of PLLs and VCOs that we have available, but we're going to be expanding on those. With this custom board, you can compare your simulation results with the actual performance in the lab. 13

14 Get Loop Filter Parameters The old way was to just pick a phase margin and loop bandwidth by rules of thumb and experience EasyPLL picks all parameters in an optimal way to ensure that the system parameters are met EasyPLL picks which phase margin yields the fastest possible lock time Page 14 Again, the old way was that you picked a phase margin and loop bandwidth by rules of thumb and experience. EasyPLL picks all the parameters in an optimal way to ensure that the system parameters are met. EasyPLL also picks which phase margin yields the fastest possible lock time. A phase margin of 45 deg might be a good value in a certain application or maybe 50 deg in a different application. Somewhere in there is a good rule of thumb. But why settle for a rule of thumb when you can have a program tell you to the tenth of a degree what the optimal phase margin is? 14

15 Design Loop Filter EasyPLL chooses time constants in an optimal way that typically can result in up to a 30 % improvement in lock time EasyPLL exactly solves for all component values (except 4th order filters, for which it approximates) EasyPLL returns exactly what is specified Page 15 EasyPLL uses computer algorithms to choose the time constants in an optimal way. For a second order loop filter you are going to have one zero, one pole, and a constant that we call total capacitance. You are going to have three unknowns and then from those unknowns you solve for component values. In the case of the second order filter, you are specifying loop bandwidth and phase margin, but where does the other constraint come from? The other constraint is imposed by an old-fashioned rule of thumb, which is not necessarily a bad rule of thumb. In fact EasyPLL uses that rule of thumb as a first approximation. But then, it goes and tweaks this constraint around to choose it an optimal way for the fastest possible lock time. As a result, a 30% improvement in lock time, theoretically, is not uncommon, especially in the case of a third order filter. In a second order filter, the improvement may not be as much. EasyPLL solves exactly for component values, except in the case of the fourth order filter, which you have to approximate. In the case of a second order filter, you have one pole, one zero, and a total capacitance. You have three constraints and three unknowns, capacitor C1, capacitor C2, and resistor R2. The components are determined for you. But in the case of a third order filter, there are two poles, one zero, and a total capacitance. Even if you know the poles, there are four constraints and five components. It is very common to introduce some approximations to solve for the components. But why do that when you can actually solve explicitly for the components? Taking into account the VCO input capacitance, you now have yet another constraint, or you have the ability to enforce yet another constraint. In a third order filter, the capacitor C3 is the one sitting right in front of the VCO. You want this capacitor to be large relative to the VCO input capacitance. EasyPLL places a constraint such that the capacitor C3 is as large as possible and will not be swamped out by the VCO input capacitance. By choosing C3 as large as possible, you are also minimizing resistor R3. So you made some optimization in choosing your time constants and went from the time constraints to the components. You have also implied a constraint that gives you 15

16 Determine System Level Performance EasyPLL also simulates all results so that the design can be double checked The impact of rounding component values to standard values can be seen EasyPLL provides detailed and complete simulations Page 16 EasyPLL also simulates all the results, so you can double check and see what you got. We will show you some of the plots for phase noise and lock time. You can see the impact of rounding component values. You can also see that the simulations are fairly detailed and complete. The one thing that EasyPLL does not do is take into account bad dielectrics. It assumes that the capacitor dielectric is optimal -- not something with a lot of dielectric absorption. In practice, you should use the best dielectric available for the size of your capacitor. 16

17 Four Easy Steps in EasyPLL Page 17 Here are the four easy steps in creating a loop filter in EasyPLL -- Choose a Part, Create a Design, Analyze a Design, and Build It. In Choose a Part, you determine your system requirements and select parts that meet those requirements. In Create a Design, you determine the components for your Loop Filter. In Analyze a Design, you run simulations to verify the functionality of your Design. In Build It, you can actually have us build it. We will go through our distributor Avnet and they will ship that out in five days to you. They will actually test the board and see if it works before they ship it. All of these steps are explained in detail in wireless.national.com. 17

18 Choose a Part Enter System Requirements Page 18 Let's go to the "Choose a Part" section in EasyPLL. The first thing we do is specify a minimum output frequency, a maximum output frequency, and a comparison frequency. If you choose to use fractional N PLL, you could specify a fractional modulus and a channel spacing, but right now we have it set to integer PLL. Under the PLL selection option, you can select from a single PLL, dual PLL, or both single and dual PLL. There are various checks you can use to narrow down or expand the selection criteria. The Frequency Check will eliminate parts that do not meet the frequency range you specify. The Prescaler Check will ensure that the parts available meet the prescalers and that the counters are properly able to handle the ratios that are implied. The Automatically Narrow PLL Choices option will give you the best part in the field. For instance, using the LMX2330, we have the A family and then we have the L family. The L family is pin-out compatible, program compatible, newer, better, lower current, so EasyPLL will recommend this part to you if you have this option checked. It will eliminate older families of parts and replace it with the upgraded family. Then, within the family, it will show you what it feels is the best choice. Without this option, you would be overwhelmed with how many PLLs you'd have to choose from. There are quite a few PLLs, in most cases, that match the frequency and counter-values you want. 18

19 Choose a Part: Select a PLL and VCO Page 19 First of all, we have to select the PLL and VCO. We define our criteria and EasyPLL is gives us a list of PLLs and VCOs that meet our criteria. Notice, for instance, a 2326 recommended by EasyPLL. EasyPLL also recommends the It did not eliminate this part in favor of the 2326 because it is not pin-out compatible, even though I'd probably recommend the 2326 over From the recommended VCOs available, we have a MuRata VCO and two Zcomm VCOs. Let us go to the PLL field. Here you see a description that tells you basically what the PLL does, a maximum frequency, a minimum frequency, a prescaler, and a price. This is 1K pricing, just to give you a relative idea. Sometimes this can help you make your decision. The other field we have is evaluation board, which tells you if we can support an evaluation board with this part. You can get samples and buy the part if you wanted to from this link. From the VCO you have the part number, the maximum frequency, the minimum frequency, the gain. This is the maximum tuning voltage of the power out. Currently, EasyPLL does not use the maximum tuning voltage and power out in calculation, but it is for your benefit. The VCO information is based on information we get from our VCO manufacturer's web site. It gives you an idea of the phase noise, to 10 kilohertz. If the manufacturer does not specify a phase noise of 10 kilohertz, we try to normalize that. 19

20 Create a Design: Enter Performance Requirements -Phase Margin -Loop Bandwidth are set to AUTO 3 2 nd Order Filter 1 2 -Optimize for Lock Time and set constraints Page 20 This section describes Create a Design in the EasyPLL flow. We show the comparison frequency, which is ported over already from the Choose a Part screen. We also show the output frequency. In the example we gave, there was actually a range of frequencies. The output frequency is chosen to be the geometric mean of the minimum and maximum. This is the value such that the variation in loop bandwidth around the value design is minimized. The charge pump gain is automatically ported over. The charge pump gain can actually vary over voltage such that at 5 volts you might actually get a slightly higher gain than at 3 volts. The default value we put in here is the highest charge pump gain at 3 volts. There are parts with multiple gain in other things, but this is actually a valid gain to use and what we would recommend. The VCO gain and VCO input capacitance are ported over from the VCO that was chosen. The first loop filter parameter is the phase margin, which is set to 48 deg, which is a good starting point. However, we have actually set this parameter on AUTO. This implies that EasyPLL will consider all possible phase margins between 30 and 70 degrees and select the value it feels is best. The loop bandwidth is also set on Auto, so with the loop bandwidth. Thus, EasyPLL will select the best loop bandwidth based on the optimization constraints that will be described below. When choosing the best phase margin and loop bandwidth, EasyPLL will consider the lock time require that we set under the optimization constraints. Current, the maximum allowable lock time is set to 300us. The maximum spur gain is set to -5 db. Spur gain is not to be confused with spur level. The spur level is not -5 db. The spur gain tells you a relative level of spur noise for comparison with another filter -- something the spur level does not tell you. Thus, if the spur gain is -5 db for one filter and -10 db for another filter, then then filter with -10 db spur gain has 5 db better spur performance. 20

21 View Component Values: -Phase Margin chosen as 49.2 deg -Loop Bandwidth chosen as 8.7 KHz - Lock time achieved - Spur gain missed Page 21 After we have specified the required lock time and spur performance of the loop filter and set the loop filter parameters to AUTO, EasyPLL will choose the values of the loop bandwidth and phase margin for you and come out with a set of components C1, C2, and R2 for a 2nd order filter. On this slide we cut off the schematic part that shows you what components are where, but it does show you the location there. We have a standard value, an ideal value, the vendor, a part number, and size, like for instance 0603 or Then we tell you the percent difference between the standard and ideal component values. A common issue is with the dielectric. Even if you have the exact same value of capacitor, same tolerance of capacitor, the dielectric used in the capacitor can have an impact. In general the X7R dielectric can increase the lock time. It does not have much impact on phase noise or the spur, but can increase the lock times. This increase can be quite dramatic, perhaps from 200us to 300us. So the X7R dielectric is one you would prefer not to use, but in many cases maybe that's the only dielectric available. There are other dielectrics such as polypropylene or tantalum, although tantalum's not a very good dielectric to use either. With the components we picked in this database, we tried to pick values we thought would fit on the board. We always tried to pick the best possible dielectric that we had available in our components database. We are going to reiterate some things we talked about on the previous screen. The value of this is that you can change one of your parameters. You can see that under the loop filter optimization under the spur gain, you have an idea of the spur gain it is actually achieving. For instance, we are saying it is achieving 11.9 decibels and you want it -5, so we're missing our target spur gain by a good 17 decibels. If you look under the phase margin, we have set it to 48 degrees on AUTO. We also see something called adjusted value. EasyPLL says here that it feels 49.2 degrees is the optimal phase margin for the fastest possible lock time and sets the phase margin to this value. It also says, even though you set the loop bandwidth to 7 kilohertz, since you set it to auto, the loop bandwidth becomes 8.7 kilohertz to need to meet this lock time requirement. In this presentation we are showing a lot of the auto-everything, but 21

22 Increase to 3rd Order Filter -Phase Margin adjusted to 45.5 deg -Loop Bandwidth adjusted to 8.6 KHz Change to 3 rd Order Filter - Lock time achieved - Spur gain achieved Page 22 Since the 2nd order filter did not meet our spur gain requirements, let us increase the filter order to a third order filter. Remember that we were missing the spur gain by 17 decibels. After increasing the filter order, we still met the lock time requirement of 300 us. In fact, it is about the same as the second order. With the 3rd order filter, we have reduced the spur by a good 17 decibels, from a spur gain of about 12 to around -5, so this is giving you an idea of how the filter order affects the performance. EasyPLL also supports 4th order filters, although it does have to approximate component values, but not time constants. If you do not know which filter order to choose, set this parameter to AUTO and EasyPLL will choose the appropriate value for you. 22

23 Analyze a Design: Locktime Viewing the Lock time graph verifies that we met our Lock time requirement of <300uS Page 23 This section discusses Analyze a Design in EasyPLL. This image displays the lock time graph showing a lock time of 289.5us as we calculated in the Create a Design section. Here, you will see two faint gray lines, one on top and one on bottom, which represent the exponential envelope. There are several advantages in using the exponential envelope. First of all, it makes computer algorithms much faster. From a practical point of view, consider that the VCO gain and charge pump change, your lock time will always slightly change. In practice, the PLL will ring, and we must take this ringing into account. Take the case that if you have one loop filter that looks good, but then you do a change or a frequency jump a little bit, or charge pump gain from part to part changes just a little bit, and then you can get something drastically different. So it's at least my feeling that using the exponential envelope gives you a better idea of the lock time, although it is a more conservative estimate, it is sandbagging a little bit. 23

24 Analyze a Design: Spur Level Running the Spur Estimate simulation verifies our Spur Gain of -5 db at a 500 KHz offset and a corresponding Spur Level of -86 dbc. Page 24 This is the Spur Estimate screen. You can enter spur offsets to get the spur gain and an estimate of the spur level. We should note that predicting the spur is not an exact science. In fractional parts, spur level can be voltage dependent or depend on prescaler. You have to take this with a little bit of caution. The spur gain, on the other hand, is much more predictable because it is a relative number. On most of the boards that I've seen, the spur gain estimates tend to be reasonably good. It allows you to change the charge pump leakage. This diagram actually considers more than leakage. It actually considers the part itself, including some properties of the charge pump itself, the mismatch and the turn-on times, and other factors. It is interesting to note that you can change the charge pump leakage and have an idea if leakage is really the dominant factor or whether the dominate factor is something else. 24

25 Analyze a Design: Bode Plot The Bode Plot graph shows the Phase Margin and Loop Bandwidth that were calculated for you by EasyPLL. Page 25 The Bode plot tells you a lot about your design, including the phase margin and loop bandwidth. Notice that the phase margin is optimum or maximum at the loop bandwidth. This is a first order of that rule of thumb that was used. It is not the optimal rule, but it's close. The loop bandwidth is defined as the point where the open loop transfer function equals 0 decibals. The Bode plot screen gives you other information also. It gives you quite a few parameters and time constants. Most of the things that you would ever want to know and probably things that you would never care to know about your loop filter are given. Question: Have you ever used a Twin Tee or other type of notch filter to help the spur? Answer: The only experience I've had with that was that in the case where the spur is close to the loop bandwidth. This case is very difficult to obtain using a high order filter, so you might want to try and use a notch filter. The problem with a notch filter is that it's tricky to do without distorting the lock time. I tried it but it was not a very good experience. Question: Can you analyze the effect that it has on loop stability Answer: Yes, but EasyPLL does not do this. Sometimes people put an inductor and some kind of low-pass filter with inductor and capacitor to try and notch out one of the spurs. This kind of filter has one major problem even though it is effective. The inductor value becomes so large that the component values are not feasible. I have played around with different types of notch filters with not too much success. 25

26 Run the Design Check to make sure it s a good design Valuable tips on how to improve your design. Build It: Design Check Page 26 Here, we discuss the Design Check feature in the Build It section. The Design Check allows you to do a sanity check of your design as well as receive helpful hints on how to improve your design. The Design Check performs a series of checks on your design and gives you a result for each check. The results include Ok, Tip, Warning, and Fail. On any of these checks, if you fail a check, you can click on message to get a detailed explanation of you failed the check. For instance, the VCO Type Check makes sure that the VCO you selected is supported for a custom eval board. The VCO Capacitance Check is checking to see how big that capacitor is relative to the VCO input capacitance. The Voltage Check is something we've used for purposes of building the board. You do not have to build a board to use this tool, but if you want to build a board, you cannot fail any checks. The Design Check checks the output power just to make sure you're not putting too little power. Again, this is something we do when we build a board. So a lot of these checks are related to either the PLL or VCO supported for the custom evaluation board. The design check checks for other things also. It checks your capacitors and gives you a tip. For example, it says you're using the X7R dielectric. In this case there was really no choice. Maybe if I used an 0805 or larger footprint, I could get a better quality dielectric. The footprint is something that it's checking to see if it's supported by a board, but it also checks discrete sampling effects. EasyPLL does not really account for discrete sampling effects, but it does check that your loop bandwidth is sufficiently narrow. It is also checking for stability, giving you an idea how well it's optimized. Another check is called Low Order and High Order Filter Check. The Low Order Filter Check will say something like, "I feel that if you used the high order filter, you'd really get some benefit from that." Or the High Order Filter Check might say, "I think this high order filter really isn't doing much for you." It checks your phase margin and other attributes that are related to building the board. Question: Does EasyPLL cover active filters? 26

27 Build It: Order Custom Board Review the Bill of Materials Click on Order Custom Board Enter your credit card information Custom/tested board will be shipped within 5 business days. Page 27 This screen gives you the Build It page. In this page, you get a bill of materials of your design which includes the PLL, VCO, and loop filter components. It also shows you whether the parts are in stock from Avnet for a custom evaluation board order. If you wish to order a custom evaluation board for your design, simply click on the Order Custom Board Link, enter your payment and shipping information, and a custom/tested board will be shipped to you within 5 business days. You can click on the Design Check button or Design Summary to get a quick estimate of what your filter does. The Design Summary information is also available from the Create a Design section. 27

28 Final Result Page 28 As the final result if, you get a custom evaluation board built custom to your design. The custom evaluation board is built, tested (based on your simulation results in EasyPLL), and shipped to you in 5 business days for the low price of $ tax + shipping. It is a nice little elegant board. All you have to do is plug it in to test your design in the lab. 28

29 Conclusion New Approach for Loop Filter Design and Optimization Quicker design time Optimized loop filter designs No more guessing! Design your loop filter in minutes rather than days Page 29 The conclusion here is the new approach for loop filter design. This is what we're saying -- that we're really using the idea of computers to go and design and simulate, and then redesign and simulate, to get you the best possible optimized loop filter. It gives you quicker design time. Although in theory, you could get exactly the spur level or lock time you designed for, you most likely will not be able to get it in the real world. However, EasyPLL will reduce the number of design iterations, giving that idea of what order filter to use. It gives you a lot of clues. One issue that comes up frequently is does it really matter what type of dielectric I use? One way is to calculate the theoretical lock time and compare to what you actually measure. If what you actually measure is much larger, then you should go back and ask questions. Could it be related to my capacitor type? Maybe I specified a different VCO gain than I thought or whatever, but that gives you a good idea. It takes a lot of the guesswork out, at least. You are never going to solve everything on the bench and make zero bench time, but you can at least solve the problem theoretically. Basically, you can design your loop filter in minutes rather than days and reduce the number of iterations. One other feature I should mention also is that we have a share feature where you can take your design, save it here, share it with your friends or whoever you want. You don't have to have any sort of special software or anything. When you share a design with someone, the recipients will receive an . All they have to do is click on the link and the design will be copied into their account. If they do not have an account with National, one will be automatically created. This feature is available for Webench applications on the National web page. 29

30 Where to Find More Information WIRELESS.NATIONAL.COM home page Links to techonline server archive of this presentation Deans book PLL Performance, Simulation and Design Handbook, 2nd Edition! Page 30 30

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