Tutorial Introduction

Transcription

1 Tutorial Introduction PURPOSE: This tutorial provides a detailed description of the features and operations of the TouCAN bus. OBJECTIVES: Describe the CAN specification and layer architecture. Identify the different fields in the message buffer structure and the different frame formats (Data, Remote, Standard, Extended, InterFrame, Error). Distinguish between the different Error confinement states (Error Active, Error Passive, Bus Off). Describe bit timing and synchronization. Describe the bits in the TouCAN configuration, control, and status registers. Describe frame processing and filtering (transmit and receive). CONTENT: 38 PAGES 6 QUESTIONS LEARNING TIME: 45 MINUTES This tutorial describes the features and operations of the TouCAN bus. We begin with an overview of the CAN bus specification and architecture. Then, we will discuss the message buffer structure, message filtering, and identify the fields in the different frame formats. We will take a detailed look at error confinement, bit timing, and synchronization. We will also examine the various TouCAN registers, and discuss the processing steps for transmitting and receiving message frames. Please note that you can access a detailed view of the MPC500 and MPC565 block diagrams using the reference buttons at the top of the course page. 1

2 TouCAN Features TouCAN Modules 16 message buffers each Each buffer can transmit or receive 8 bytes of data Multimaster concept Open network architecture Programmable I/O modes Maskable interrupts Programmable loop-back for self test operation Independent of the transmission medium (external transceiver is assumed) High immunity to EMI Short latency time for high-priority messages Low power sleep mode, with programmable wake up on bus activity The Controller Area Network (CAN) is a serial communications protocol targeted for automotive and industrial applications that require a high level of data integrity. Some examples include automotive electronics, engine control units, sensors, and anti-skid breaking systems. These applications can be connected using the CAN bus with bit rates of up to 1Mbits/second. The CAN bus can also be used in vehicle body electronics, such as lamp cluster and electric windows, to reduce the amount of wire harness. The MPC565 has three CAN modules. A summary of the main features is provided here. Each module includes 16 message buffers. A message buffer can transmit or receive up to 8 bytes of data. A multimaster protocol utilizes non-destructive collision resolution to ensure the highest priority message is transmitted on to the bus. Flexible system configuration allows the user to create the network that best fits the application needs. 2

3 CAN Specification Latest revision (version 2.0) is divided into parts A and B Part A consists of the previous specification revision (1.2) Standard 11-bit identifier field No specification for message filtering Layered architecture description based on Bosch's internal model Part B outlines enhancements to the CAN protocol, including: Extended 29-bit identifier field Some message filtering requirements Layer description based on ISO/OSI reference model The latest CAN specification, version 2.0, is divided into two parts, A and B. The minimum CAN requirements include compatibility with specification Part A, which is the previous CAN specification, version 1.2. Most current industrial applications use the standard 11-bit identifier format. The CAN serial communications protocol was initially developed by Bosch for automotive multiplex wiring systems. With the CAN specification, message prioritization is defined by the user, with a guaranteed minimum latency for highest priority messages. The CAN protocol has built in error detection and error signaling features, along with automatic retransmission of corrupted messages. Distinction between temporary errors and permanent node failures prevents faulty nodes from causing long-term disruptions of network traffic. 3

4 CAN Layered Architecture DATA LINK LAYER LOGICAL LINK CONTROL (LLC) SUB-LAYER - Acceptance filtering - Overload notification - Recovery management MEDIUM ACCESS CONTROL (MAC) SUB-LAYER - Data encapsulation / decapsulation - Frame coding (bit stuffing / unstuffing) - Medium access management - Error detection / signaling - Acknowledgement - Serialization / deserialization PHYSICAL LAYER - Bit encoding / decoding - Bit timing - Synchronization The CAN specification, ISO, defines the data link layer and physical layer for a CAN network. The Logical Link Control sub-layer, or LLC, is concerned with message filtering, overload notification, and recovery management. The Medium Access Control sub-layer, or MAC, is responsible for message framing, arbitration, acknowledgment error detection, and signaling. The MAC sub-layer provides a self-checking mechanism, called fault confinement, that distinguishes between temporary and permanent errors. The Physical Layer deals with signal transmission, bit timing, bit encoding, and synchronization. The physical layer is not part of the TouCAN, meaning the user can define a custom physical layer based on an application s requirements. 4

5 CAN Physical Layer Requirements CAN protocol does not specify physical layer No specified transceiver User s network characteristics define transceiver requirements Acceptable physical media can include (though not limited to): Twisted pair, shielded or unshielded Single wire Fiber optic cable Transformer coupled to power lines As previously noted, the CAN specification does not define the physical layer and there is no specified transceiver. This means that the user s network characteristics define the transceiver requirements. Acceptable physical media can include a twisted pair (shielded or unshielded), a single wire, fiber optic cable, or a transformer coupled to power lines. Acceptable transmission rates range from 5K to 1M bits/sec. Most implementations use NRZ bit formatting over twisted pair bus. 5

6 Question Which of the following are defined in the Medium Access Control (MAC) sub-layer of the CAN 2.0 specification? Select all that apply and then click Done. Frame coding Error detection Synchronization Data encapsulation Acceptance filtering DONE Consider this question about the CAN 2.0 specification. The MAC sub-layer includes definitions for frame coding, error detection, and data encapsulation. Note that synchronization is defined in the Physical layer, and acceptance filtering is defined in the Logical Link Control sub-layer. 6

7 Message Buffer Structure $0 TIME STAMP CODE LENGTH CONTROL/STATUS EXTENDED ID $2 $4 ID[28:18] SRR IDE ID[17:15] ID[14:0] RTR ID_HIGH ID_LOW $6 $8 $A DATA BYTE 0 DATA BYTE 1 DATA BYTE 2 DATA BYTE 3 DATA BYTE 4 DATA BYTE 5 $C DATA BYTE 6 DATA BYTE 7 $E RESERVED STANDARD ID ID[28:18] RTR TIME STAMP ID_HIGH ID_LOW Let s continue with a look at the message buffer structure. The standard and extended formats are shown here. The TouCAN has 16 message buffers, any of which can be designated as a transmit (Tx) buffer or receive (Rx) buffer. Each message buffer is assigned an interrupt flag bit in the TouCAN IFLAG register, which is used to indicate successful transmission or reception to the CPU. Please note that the assignment of the message buffer for Tx or Rx is accomplished by writing the appropriate code field in the message buffer. 7

8 Rx and Tx Buffer Codes RX BUFF CODE BEFORE AFTER DESCRIPTION TX BUFF CODE BEFORE AFTER DESCRIPTION BUFF NOT READY TO TX BUFF NOT ACTIVE / 0110 BUFF IS FULL/OVERRUN BUFF ACTIVE & EMPTY OVERRUN SECOND FRAME WAS RECEIVED BEFORE CPU READ FIRST FRAME AN EMPTY BUFFER WAS FILLED A FULL/OVRN BUFFER WAS FILLED TX BUFF READY TO TX ONCE REMOTE FRAME WILL BE TRANSMITTED AND MESG BUFF BECOMES RX BUFF DATA FRAME WILL BE TRANSMITTED ONLY AS A RESPONSE TO REMOTE FRAME DATA FRAME TO BE TRANSMITTED ONCE THEN ONLY AS A RESPONCE TO REMOTE FRAME, ALWAYS These tables describe the receive and transmit message buffers codes. The message buffer default state is inactive out of reset. For a receive buffer to become active, the CPU writes the binary code field Once the buffer is filled with a message, the code field is automatically updated by the TouCAN module to binary 0010 to indicate successful reception and the buffer is full. For a transmit message buffer, the CPU writes the code field binary value 1100 to let the TouCAN module know that a transmit message buffer is ready to transmit. Once transmitted, the code field is updated automatically by the TouCAN module to prevent the buffer from participating in the transmission traffic. There are many other codes that are automatically updated by the CAN bus based on the condition and frame type on the bus. For more information, refer to the User s Manual. 8

9 Standard Format Frames Field Description Time Stamp ID(28:18) RTR RTR/SRR Bit Treatment The ID LOW word, which is not needed for standard format, is used in a standard format buffer to store the value of the free-running timer which is captured at the beginning of the identifier field of the frame on the CAN bus. Contains bits (28:18) of the identifier, located in the ID HIGH word of the message buffer. The four least significant bits in this register (corresponding to the IDE bit and ID(17:15) for an extended identifier message) must all be written as logic zeros to ensure proper operation of the TouCAN. This bit is located in the ID HIGH word of the message buffer; 0 = data frame, 1 = remote frame. If the TouCAN transmits this bit as a one and receives it as a zero, an arbitration loss is indicated. If the TouCAN transmits this bit as a zero and is receives it as a one, a bit error is indicated. If the TouCAN transmits a value and receives a matching response, a successful bit transmission is indicated. Here we see the fields for the Standard format frames. The message identifier, or ID, is used to define the message type, priority, and destination. The CAN bus protocol provides two types of identifiers: the first is called the standard format which consists of an 11-bit identifier; the other is the extended format, which uses a 29-bit identifier. The 11-bit Identifier is labeled ID28 to ID18 in CAN 2.0B. Please note that the selection of ID type may depend on compatibility with existing CAN installations. 9

10 Extended Format Frames Field Description Time Stamp Contains a copy of the high byte of the free running timer captured at the beginning of the identifier field of the buffer frame on CAN bus. ID[28:18]/[17:15] Contains 14 MS Bits of Extended identifier. Substitute Remote Request (SRR) Contains a fixed recessive bit, used only in extended format. It should be set to 1 for TX buffers. It will be stored as received in the RX buffers ID Extended (IDE) Should be set to 1 for extended formats, 0 otherwise. ID(14:0) Bits[14:0] of the extended identifier field. Remote Transmission Request (RTR) 0 = Data frame, 1 = Remote frame This is the structure of the Extended format frames. The larger identifier allows many more message types and addresses. 10

11 TouCAN Architecture All registers 16-bits CONTROL INT 16 Transmit/Receive Message Buffers Tx SERIAL BUFFERS BUFFERS 0-13 BUFFER 14 Rx *transparent to user GLOBAL MASK 29 bit BUFFER 15 DATA DATA LENGTH MASK 14 TIME STAMP MASK 15 ID This block diagram shows the message transmission and reception paths. When transmitting, the message with highest priority is transferred from a Tx buffer into the serial buffer. Then, it is shifted out one bit at a time. The received message is first assembled in the serial buffer, and the message ID is compared to the IDs of the message buffers using the Receive Mask Registers. Then, the message is filtered into the appropriate buffer having a matching ID. 11

12 Receive Global Mask Register RXGMSKHI (IDE) MID28 MID27 MID26 MID25 MID24 MID23 MID22 MID21 MID20 MID19 MID MID17 MID16 MID15 RST: RXGMSKL MID14 MID13 MID12 MID11 MID10 MID9 MID8 MID7 MID6 MID5 MID4 MID3 MID2 MID1 MID Applies to message buffers : Don t compare 1: Compare As shown in the block diagram on the previous page, the Receive Global Mask Register is a global acceptance mask for the frame ID s of message buffers The values of the 11 or 29 bit identifiers of all these buffers are compared bit-by-bit to the value in this register. A value of 1 forces a check of that bit against the corresponding bit of the incoming ID to see if a match exists, whereas a value of 0 accepts any value of the incoming ID bit. This allows the module to accept messages from a range of addresses. 12

13 Receive Buffer 14:15 Mask Registers RX14MSKHI MID28 MID27 MID26 MID25 MID24 MID23 MID22 MID21 MID20 MID19 MID MID17 MID16 MID15 RST: RX14MSKLO MID14 MID13 MID12 MID11 MID10 MID9 MID8 MID7 MID6 MID5 MID4 MID3 MID2 MID1 MID Applies to Rx Message Buffer 14 RX15MSKHI MID28 MID27 MID26 MID25 MID24 MID23 MID22 MID21 MID20 MID19 MID MID17 MID16 MID15 RST: RX15MSKLO MID14 MID13 MID12 MID11 MID10 MID9 MID8 MID7 MID6 MID5 MID4 MID3 MID2 MID1 MID Applies to Rx Message Buffer 15 0 = Don t compare 1 = Compare The Receive Mask Registers 14 and 15 have the same structure as the Global Mask Register, and are used to individually mask buffers 14 and 15 respectively. 13

14 Question Each TouCAN module has how many transmit and receive message buffers? Click on your choice. a) 2 transmit and 3 receive b) 3 transmit and 2 receive c) 8 transmit and 8 receive d) 16 total, each either receive or transmit Here s another question for you. Each TouCAN module contains sixteen message buffers, any of which may be configured as a receive or transmit buffer. 14

15 Data Frame Structure Interframe Space DATA FRAME Interframe Space Start of Frame (1 bit time) Arbitration Field (Standard ID - 12 bit times ) (Extended ID - 32 bit times) Control Field (6 bit times) Data Field (0-8 data bytes) CRC Field (16 bit times) ACK Field (2 bit times) End of Frame (7 bit times) Next, let s discuss the data frame structure. A data frame is used to transmit data onto the multiplex bus. This is the most commonly used frame in a CAN network. As shown here, a data frame is composed of seven different bit fields: Start of frame, Arbitration field, Control field, Data field, CRC field, Acknowledge field, and End of Frame. The data field contains the data being transmitted, and can contain from 0 to 8 bytes. Each byte contains 8 bits, of which most are transmitted with the MSB first. Let s take a closer look at some of the fields, beginning with the Control field. 15

16 CONTROL Field Arbitration Field CONTROL FIELD Data or CRC Field r1/ide r0 DLC3 DLC2 DLC1 DLC0 r0 - reserved, always dominant r1/ide - r1 in Can 2.0, Part A, r1/ide in Part B Data Length Code No. of data bytes Data Length Code DLC3 DLC2 DLC1 DLC The Control field consists of the six bits as shown here. The first two bits of the Control field are always dominant. The data Length Code is a 4-bit field that denotes the number of data bytes associated with the data frame. The difference between the Standard and Extended formats is in the r1/ide bit. In the Standard format this is the IDE bit, and in the Extended format this is the reserved bit r1. In both cases, this bit should be transmitted as a dominant bit. Please note that a recessive bit is defined as logic 1, and a dominant bit is defined as logic 0. 16

17 CRC and ACK Fields Data or Control Field CRC FIELD Ack Field End of Frame CRC Sequence (15 bit times) CRC Delimiter ACK Slot ACK Delimiter The CRC field is a 15-bit field followed by a 1-bit delimiter.the CRC code is generated by the CAN transmitter and checked by the receiver for data integrity. The Acknowledge field is a 2-bit field that indicates a message was received successfully and without errors. The Acknowledge field is the last field in a frame, and is asserted by the receivers as one dominant bit followed by one recessive bit. 17

18 Standard vs. Extended ID Format STANDARD IDENTIFIER FORMAT Interframe Space S O F ARBITRATION FIELD Identifier (11 Bits) CONTROL FIELD r 0 DLC (4 Bits) Data Field RTR r1/ide* EXTENDEDIDENTIFIERFORMAT * In CAN 2.0, Part A - r1 bit incan2.0,partb-idebit Interframe Space S O F Identifier (11 Bits) ARBITRATION FIELD Identifier (18 bits) r 1 CONTROL FIELD r DLC (4 Bits) 0 Data Field SRR IDE RTR The format of the Arbitration field is different for Standard format and Extended format frames. In the Standard format, the Arbitration field consists of an 11-bit identifier denoted ID-28:ID-18. The Remote Transmission Request, RTR, has to be a dominant bit for a data frame and a recessive bit for a Remote frame, which is a request for data. In the Extended format, the Arbitration field consists of a 29-bit field denoted ID-28:ID-0. The 11-bit ID is transmitted first, followed by the IDE and the Substitute Remote Request, SRR, bit. The Extended ID is transmitted after the SRR bit, which is a placeholder to allow compatibility with the Standard format messages. The ID part of a frame defines the priority of the message as well as the target address. If multiple nodes transmit simultaneously, the conflict is resolved using bit-wise non-destructive arbitration of the message IDs. If a transmitter loses arbitration during the ID transmission process, the transmitter automatically becomes a receiving node. Any loss of arbitration after the arbitration field will be interpreted as an error, and an error frame will be transmitted. 18

19 Interframe Space Remote Frame Structure REMOTE FRAME Interframe Space StartofFrame (1 bit time) Arbitration Field (Standard ID - 12 bit times ) (Extended ID - 32 bit times) Control Field (6 bit times) CRC Field (16 bit times) ACK Field (2 bit times) End of Frame (7 bit times) A Remote frame is similar to a Data frame, except that it does not contain a Data field and it has a lower priority than a Data frame. A Remote frame can be sent by a node requesting a data frame from another node. The transmitting node of a remote frame automatically internally sets up the same message buffer that transmitted the remote frame, to become a receive message buffer for the requested data. 19

20 InterFrame Space INTERFRAME SPACE - ERROR ACTIVE TRANSMITTER Frame INTERFRAME SPACE Frame Intermission (3 bit times) Bus Idle INTERFRAME SPACE - ERROR PASSIVE TRANSMITTER Frame INTERFRAME SPACE Frame Intermission (3 bit times) Bus Idle Suspend Transmission (8 bit times) An Error frame is transmitted by any node to indicate that an error has occurred during transmission or reception process. An Error frame causes the current transmitter to immediately abort transmission. The recovery time from error detection to the start of message retransmission is a maximum of 29-bit times. There are two Error flag formats, Error Active and Error Passive. The Error Active flag consists of six consecutive dominant bits. The Error Passive flag consists of six recessive bits, unless it is written by dominant bits from other nodes. 20

21 Fault Confinement Separate error counters for transmit and receive errors Error counters incremented by 1 or 8, decremented by 1 Three possible bus states: Error Active: Both error counts < 128 Transmits active error flag during error frame Bus waits for intermission period during interframe space Error Passive: Either transmit or receive error count > 128 Transmits passive error flag during error frame Must wait for "suspend transmission" period as well as intermission during interframe space Bus Off: Either transmit or receive error count > 255 Output drivers switched off Will not participate in bus traffic, only allowed to monitor bus Returns to Error Active status following detection of 128 consecutive periods of 11 recessive bits. Once error-free bus traffic resumes, nodes can recover from error states. Each node has two error counters, one for the receiver and one for the transmitter. The error counters are incremented by 1 or 8 when an error is detected, and decremented by 1 when the retransmission is successful. A node can transmit an Error Active flag or an Error Passive flag. In addition, there is a third state, Bus Off. Transmission from the node is determined by what state it is in. The Error Active state occurs when both error counts are < 128. In this case, a node transmits an Error Active flag during an Error frame. The node will only wait for an intermission period during interframe space before resuming transmission. Error Passive state occurs when one of the error counts is > 128. In this case, a node transmits an Error Passive flag during an Error frame. The node must wait for a suspended transmission period as well as intermission during interframe space before resuming transmission. The Bus Off state occurs when one of the error counts is > 255. In this state, the output drivers are switched off and do not participate in bus traffic, although bus monitoring is allowed. The Bus Off node will return to Error Active status following the detection of 128 consecutive periods of 11 recessive bits. Once error-free bus traffic resumes, nodes can recover from error states. 21

22 Question Which of the following bits are defined in the Extended Frame format? Select all that apply, and then click Done. r1 r0 SRR 11-bit ID 29-bit ID DONE Let s review the material presented so far with a couple of questions. Consider this question about the Extended frame format. Using the 29-bit ID, the Extended frame format also includes r1, r0, and SRR. 22

23 Question Which of the following characteristics describes the Error Passive fault confinement state? Select all that apply, and then click Done. Either transmit or receive error count > 256 Either transmit or receive error count > 128 Both transmit and receive error counts < 128 Wait period = intermission during interframe space Wait period = 128 consecutive periods of 11 recessive bits Wait period = suspension period + during interframe space DONE Consider this question about the fault confinement states. The Error Passive state occurs when either the transmit or receive error counts is > 128. In this state, node must wait for a suspended transmission period as well as intermission during interframe space before resuming transmission. 23

24 Bit Timing Nominal Bit Rate = # bits/sec transmitted by an ideal transmitter without resynchronization Nominal Bit Time = 1 / Nominal Bit Rate NOMINAL BIT TIME SYNC-SEG PROP-SEG PHASE-SEG1 PHASE-SEG2 Sample Point SYNC-SEG PROP-SEG PHASE-SEG1 PHASE-SEG2 1 time quantum 1 to 8 time quanta 1 to 8 time quanta 1 to 8 time quanta 1 Time Quantum = 1 Serial Clock Period Let s look next at how timing and synchronization is handled. The Nominal Bit Rate is the number of bits per second transmitted by an ideal transmitter in the absence of resynchronization. The Nominal Bit Time is 1/Nominal Bit Rate. As shown in the profile, the Nominal Bit Time can be thought of as a sequence of four non-overlapping time segments. The different segments represent the time for synchronization, propagation, and phase resynchronization. Also shown is the time for each segment. Note that a Time Quantum is a fixed unit of time derived from the system oscillator, where 1 Time Quantum = 1 Serial Clock Period. The first segment of the bit time, SYNC-SEG, is used to synchronize the various nodes on the bus. An edge is expected to lie within this segment. The second segment, PROP-SEG, is used to compensate for the physical delay times within the network. This segment is programmable, and should be twice the sum of the signal s propagation time on the bus line, the input comparator delay, and the output driver delay. The remaining time is the phase buffer segments, PHASE-SEG1, PHASE-SEG2. These segments of the bit time are used to compensate for the edge phase error. These segments are automatically lengthened or shortened by resynchronization. Note that the length of these segments is defined in the TouCAN Control Register 2. The Sample Point is the point in time at which the bus level is read. Its location is at the end of PHASE-SEG1. 24

25 Synchronization Rules Hard Synchronization Occurs when a recessive-to-dominant edge occurs during Bus Idle Internal bit time is started with SYNC-SEG Resynchronization Occurs on all other recessive-to-dominant edges (and optionally dominant-to-recessive edges) PHASE-SEG1 is lengthened or PHASE-SEG2 is shortened depending on the Phase Error Phase Error - e e = 0 if edge lies within SYNC-SEG e > 0 if edge lies before sample point e < 0 if edge lies after sample point of the previous bit Resynchronization Jump Width The maximum amount by which PHASE-SEG 1 may be lengthened or PHASE-SEG 2 may be shortened. Here we see the rules for hard synchronization and resynchronization. A Hard synchronization happens when a recessive-to-dominant edge occurs during Bus Idle. In this case, the internal bit time is started with SYNC-SEG. Resynchronization occurs on all other recessive-to-dominant edges, and optionally dominant-to-recessive edges. In this case, the buffer phase segment 1 is lengthened and buffer phase segment 2 is shortened depending on the value of the PHASE ERROR, e. The value of e is determined by where the edge occurs, either within SYNC_SEG, before the sample point, or after the sample point of the previous bit. The resynchronization jump width is the maximum amount by which the buffer phase segments can be adjusted. The jump width is defined in the TouCAN Control Register 2. 25

26 TouCAN Configuration Register (1 OF 2 ) TCNMCR - TouCAN Module Configuration Register NOT STOP WAKE SOFR FRZ FRZ R HALT SUPV SELF STOP RDY APS MSK RST ACK WAKE ACK RESERVED RST: STOP - Stops the system clock inside the TouCAN 0 = Normal mode 1 = Low power stop mode (DISABLE TouCAN CLOCKS) FRZ - Determines the TouCAN action when the Freeze line is asserted 0 = Ignores FREEZE signal 1 = Enters Debug Mode HALT - Halt TouCAN clocks - 0 = Normal operation - 1 = TouCAN Clocks stopped NOTRDY - TouCAN not ready - 0 = Normal operation - 1 = TouCAN In low Power mode or Debug mode WAKEMSK - Wakeup Interrupt mask - 0 = Wake up interrupt is disabled - 1 = Wake up interrupt is disabled FRZACK - Freeze Acknowledge -0 = The TouCAN has exited Debug Mode and prescaler enabled -1 = The TouCAN has entered Debug Mode and prescaler enabled SUPV - Indicates unrestricted or supervisor only access to TouCAN registers - 0 = User/Supervisor accesses allowed - 1 = Supervisor only accesses allowed Configuration, test and interrupt registers are unaffected, always supervisor only SELFWAKE - Self Wake Enable - 0 = Self Wake disabled - 1 = Self Wake enabled (The function allows TouCAN to wake up on bus activity after stop has been entered) APS - Auto Power save - 0 = Auto power save mode disabled, clock runs normally - 1 = Auto power save mode enabled; clocks stop and run as needed STOPACK - Stop Acknowledge -0 = The TouCAN is not in low power mode -1 = The TouCAN has entered low power mode and it s clocks stopped SOFTRST - Soft Reset (Reset internal state of TouCAN) - 0 = Soft Reset cycle is complete - 1 = Soft Reset cycle is initiated The TouCAN Module Configuration Register (TCNMCR) may be used to select the required CAN global configuration. Here we see the bit definitions for configuration register 1. The CPU sets the STOP bit to stop the TouCAN clocks. This bit is cleared by the CPU, or, if self wake bit is set, by the TouCAN module on bus activity. The wakeup interrupt mask allows the TouCAN to wakeup upon detection of bus traffic. The FRZ bit determines the TouCAN action when the Freeze line is asserted, for example, when the MCU enters debug mode. If this bit is set, the TouCAN will halt. When the HLT bit is set, the S-Clock is stopped. This bit is set to 1 after reset. Message buffer receive and transmit functions are rendered inactive, and access to certain registers and bits that are normally read-only is allowed. It should be cleared after initializing the message buffers and control registers. The TouCAN sets the FRZ ACK bit when it enters the debug mode. The NOT RDY bit is a read only bit that indicates the TouCAN is in low-power stop or debug mode. This bit is cleared automatically when exiting either mode. The TouCAN can exit these modes either by synchronization to the CAN bus or by the self wake mechanism. Setting the SOFTRST bit causes the TouCAN to reset as if the reset signal was asserted. 26

27 TouCAN Configuration Register (2 of 2) CANICR - TouCAN Interrupt Configuration Register Reserved IRL ILBS Reserved RST: IRL - Channel Interrupt Request Level 000 = Request Level = Request Level 7 ILBS - Interrupt Level Byte Select 00 = IRQ[0:7] is selected 01 = IRQ[8:15] is selected 10 = IRQ[16:23] is selected 11 = IRQ[24:31] is selected The user can assign the CAN an interrupt level by writing to the TOUCAN Interrupt Configuration Register fields IRL and ILBS. There are 32 interrupt levels, with 0 being the highest interrupt level and 31 lowest. 27

28 BOFF ERR MSK MSK TouCAN Control Register (1 of 2) CANCNTRL0 CANCNTRL Reserved RXMOD TXMOD SAMP LOOP TSYNC LBUF Res d PROPSEG RST: BOFFMSK - Bus Off Interrupt Mask 0 = Bus off interrupt disabled 1 = Bus off interrupt enabled SAMP - Sampling Mode 0 = One sample per bit 1 = Three samples per bit ERRMSK - Error Mask 0 = Error interrupt disabled 1 = Error interrupt enabled RXMOD - Receive Mode 0 X Logic 0 on CANRX1 pin interpreted as dominant bit CANRX1 and logic 1 interpreted as recessive bit 1 X Logic 1 on CANRX1 pin interpreted as dominant bit and logic 0 is interpreted as recessive bit CANRX0 X 0 Logic 0 on CANRX0 pin interpreted as dominant bit and logic 1 interpreted as recessive bit X 1 Logic 1 on CANRX0 pin interpreted as dominant bit and logic 0 is interpreted as recessive bit TXMOD - Transmit Mode 00 = Full CMOS; Positive Polarity (CANTX0 = 0, CANTX1 =1 is a dominant level 01 = Full CMOS; Negative Polarity (CANTX0 =1, CANTX1 =0 is a dominant level 1x = Open Drain; Positive Polarity TSYNC - Timer Synchronize Mode Synchronizes on messages received in message buffer 0. Allows for global network time sync by resetting Time Stamp. 0 = Timer synchronization disabled 1= Timer synchronization enabled LBUF - Lowest Buffer Transmitted First 0 = Buffer with lowest ID transmitted first 1 = Buffer with lowest number transmitted first PROPSEG[2:0] - Propagation segment time Determines length of propagation segment time. Propagation segment time = (PROPSEG+1)TQ. The CAN Control Register 1 and 2 gives the user further additional control as stated above. 28

29 TouCAN Control Register (2 of 2) PRESDIV CANCNTRL 2 PRESDIV RJW[1:0] PSEG1[2:0] PSEG2[2:0] PRESDIV: Prescalar Divide Factor Divides system clock to generate S-clock S-clock equates to the time quanta from the Bosch spec. LOWEST 8 BITS ALSO CALLED Control Register 2 RJW[1:0]: Resynchronization Jump Width Jump width = (value + 1) * time quanta F SYS S-clock = PRESDIV + 1 PSEG1[2:0]: Phase Buffer Segment 1 Length of phase segment 1 = (value + 1) * time quanta PSEG2[2:0]: Phase Buffer Segment 2 Length of phase segment 2 = (value + 1) * time quanta The TOUCAN Control Register 2 includes bits related to the bit timing. The Prescaler Divide Factor field determines the ratio between the system clock and the S-clock, as shown in the equation. The RJW field defines the resynchronization jump width described earlier. The remaining bits define the length of the two buffer phase segments, PHASE-SEG1 and PHASE-SEG2. 29

30 Question The HLT bit gets set to 1 after reset. What happens when the HLT bit is set to 1? Select all that apply and then click Done. Halts the S-Clock Initiates a soft reset Makes the message buffer functions inactive until cleared Allows access to certain registers/bits that are normally read-only Done Let s pause to check your understanding of TouCAN operations with a question. When the HLT bit is set to 1, this halts the S-Clock. This also makes the message buffer functions inactive until cleared, and allows access to certain registers/bits that are normally read-only. 30

31 TouCAN Interrupt Registers IMASK - Interrupt Mask Register MASKH IMASKL RST: bit per Tx/Rx buffer 0 = Interrupt is Masked 1 = Will generate interrupt on successful transmission/reception IFLAG - Interrupt Flag Register IFLAGH IFLAGL RST: bit per Tx/Rx buffer 0 = No interrupt is pending 1 = Interrupt is pending The Interrupt Mask Registers contain one interrupt mask bit per message buffer. It enables the CAN to generate interrupt request to the CPU upon successfully transmitting or receiving a message buffer. The Interrupt Flag Registers contain one interrupt flag bit per message buffer. Each successful message buffer transmission or reception sets the corresponding IFLAG bit and, if the corresponding interrupt mask bit is set, an interrupt is requested. 31

32 Error and Status Register (1 of 2) ESTAT BITERR[1:0] ACKERR CRCERR FORMERR STUFFERR TXWARN RXWARN IDLE TX/RX FCS[1:0] 0 BOFFINT ERRINT WAKEINT RST: THE ERROR CONDITIONS ARE THOSE SINCE THE LAST TIME THIS REGISTER WAS READ. A READ CLEARS ALL ERROR BITS. BITERR[1:0]: Transmit bit error Used to identify type of transmit errors 00 = No transmit bit error 01 = At least one bit sent as dominant; received as recessive 10 = At least one bit sent as recessive; received as dominant 11 = Not Used ACKERR: Acknowledge Error 0: No ACK error since last read 1: At least one ACK error since last read CRCERR: Cyclic Redundancy Check Error 0: No CRC error in last message 1: CRC error in last message FORMERR: Message Format Error 0: No format error in last message 1: Format error in last message STUFFERR: Bit Stuff Error 0: No bit errors in last message 1: Bit stuffing errors in last message TXWARN: Transmit Error Status Flag 0: Transmit error counter < 96 1: Transmit error counter > 96 RXWARN: Receive Error Status Flag 0: Receive error counter < 96 1: Receive error counter > 96 The last register we ll examine is the Error and Status Register. The low-byte of this register is the Error Register, which is used by the CAN bus to signal error information to the CPU when it detects an error. All errors are reported to CPU by setting the appropriate error status bit in these two registers. 32

33 Error and Status Register (2 of 2) ESTAT BITERR[1:0] ACKERR CRCERR FORMERR STUFFERR TXWARN RXWARN IDLE TX/RX FCS[1:0] 0 BOFFINT ERRINT WAKEINT RST: IDLE: Idle Status 0 = CAN bus is not idle 1 = CAN bus is idle TX/RX: Transmit/Receive Status 0 = TouCAN receiving message if IDLE=0 1 = TouCAN transmitting message if IDLE=0 FCS[1:0]: Fault Confinement State 00 = Error Active State 01 = Error Passive State 1X = Bus Off State BOFFINT: Bus Off Interrupt 0: No interrupt requested when entering Bus Off State 1: If BOFFMSK bit is set, then an interrupt request to the CPU is generated. ERRINT: Error Interrupt 0: No error interrupt requests 1: If ERRMSK is set, then generates an interrupt request to the CPU. WAKEINT: Wake Interrupt 0: No wake interrupt requests 1: If WAKEMSK bit is set, then generates an interrupt request to the CPU. The Status Register communicates general status of TOUCAN operations to the CPU. This includes Idle status, Transmit/Receive status, and Fault Confinement status. Other bits will generate an interrupt request if the appropriate bits are set in the configuration registers. 33

34 Rx/Tx Error Counters RXECTR TXECTR RST: Rx & Tx Error Counters are Read Only There are two 8-bit error counters in the TouCAN module, one for the transmitter and one for the receiver. These two counters are incremented by 8 for unsuccessful transmission/reception and decremented by 1 for successful transmission/reception. As noted earlier, these counts are used in fault confinement. 34

35 Transmit Sequence $0 TIME STAMP CODE LENGTH CONTROL/STATUS EXTENDED ID $2 $4 ID[28:18] SRR IDE ID[17:15] ID[14:0] RTR ID_HIGH ID_LOW $6 $8 $A $C $E DATA BYTE 0 DATA BYTE 1 DATA BYTE 2 DATA BYTE 3 DATA BYTE 4 DATA BYTE 5 DATA BYTE 6 DATA BYTE 7 RESERVED Typical Message Buffer STANDARD ID ID[28:18] RTR TIME STAMP ID_HIGH ID_LOW 1. Write Control/Status word to deactivate TX buffer (code = 1000) 2. Write ID High and Low 3. Write data to be transmitted into TX buffer 4. Write Control/Status word to activate buffer (code 1100), and TX length The last topic we ll discuss is the transmit/receive sequences. The sequence for transmitting a message buffer is provided here. First, the control/status word is updated to deactivate the transmit buffer. Then, the message buffer ID is updated and the data to be transmitted is written to the transmit buffer. Finally, the control/status word is updated to activate the transmit buffer and to identify the buffer length. After arbitration, the message is sent to the serial message buffer for transmission. After transmission, the value of the free-running timer is written into the Timestamp field, the CODE field is updated, and a status flag is set in the IFLAG register. 35

36 Receive Sequence $0 TIME STAMP CODE LENGTH CONTROL/STATUS EXTENDED ID $2 $4 ID[28:18] SRR IDE ID[17:15] ID[14:0] RTR ID_HIGH ID_LOW $6 $8 $A $C $E DATA BYTE 0 DATA BYTE 1 DATA BYTE 2 DATA BYTE 3 DATA BYTE 4 DATA BYTE 5 DATA BYTE 6 DATA BYTE 7 RESERVED Typical Message Buffer STANDARD ID ID[28:18] RTR TIME STAMP ID_HIGH ID_LOW 1. Write Control/Status word to deactivate RX buffer (code =0000) 2. Write ID High and Low 3. Write Control/Status word to activate RX buffer (code =0100) Comparatively, the receive sequence is more complex than the transmit sequence. The first few steps are shown here. First, the control/status word is updated to deactivate the transmit buffer. Then, the message buffer ID is updated. Next, activate the receive buffer. 36

37 Receive Sequence $0 TIME STAMP CODE LENGTH CONTROL/STATUS EXTENDED ID $2 $4 ID[28:18] SRR IDE ID[17:15] ID[14:0] RTR ID_HIGH ID_LOW $6 $8 $A $C $E DATA BYTE 0 DATA BYTE 1 DATA BYTE 2 DATA BYTE 3 DATA BYTE 4 DATA BYTE 5 DATA BYTE 6 DATA BYTE 7 RESERVED Typical Message Buffer STANDARD ID ID[28:18] RTR TIME STAMP ID_HIGH ID_LOW 4. Activation of RX buffer causes the following to occur upon a frame reception. Frame is transferred to the first (lowest entry) matching RX message buffer. Capture free running timer into the Time Stamp field at beginning of the Identifier. ID field, Data field(8 bytes at most), and receive length are stored. Code field is updated. Status flag is set in IFLAG register. When the message frame is received, it is transferred to the lowest entry matching receive buffer, and the Timestamp is updated with the value of the free running timer. Then, the ID field, Data field, and Data Length are stored. Then, the Code field is updated and the status flag is set. 37

38 Receive Sequence $0 TIME STAMP CODE LENGTH CONTROL/STATUS EXTENDED ID $2 $4 ID[28:18] SRR IDE ID[17:15] ID[14:0] RTR ID_HIGH ID_LOW $6 $8 $A $C $E DATA BYTE 0 DATA BYTE 1 DATA BYTE 2 DATA BYTE 3 DATA BYTE 4 DATA BYTE 5 DATA BYTE 6 DATA BYTE 7 RESERVED Typical Message Buffer STANDARD ID ID[28:18] RTR TIME STAMP ID_HIGH ID_LOW 5. The CPU reads a receive frame from the message buffer in the following order: Control/Status word (mandatory, as activates the internal lock for this buffer). ID (optional, since it is needed only if a mask was used). Data field Free-running timer (optional, it releases the internal lock mechanism). The CPU then reads the receive frame from the message buffer in the order shown. Note that some of the fields are mandatory, others are optional. 38

39 Question Which of the following registers is updated to signal the successful transmission or reception of a message? Click on your choice. a) Configuration Register b) Control Register c) Error and Status Register d) Interrupt Flag Register Consider this question about the TouCAN registers. The Interrupt Flag Registers contain one interrupt flag bit per message buffer. Each successful message buffer transmission or reception sets the corresponding IFLAG bit and, if the corresponding interrupt mask bit is set, an interrupt is requested. 39

40 Tutorial Completion CAN Specification 2.0 Layered architecture Logical Link Layer Physical Layer Message buffer structure and frame formats Data frames Remote frames Standard and Extended formats Error confinement states Error Active Error Passive Bus Off Bit timing and synchronization Hard synchronization Resynchronization TouCAN configuration, control, and status registers Frame processing Transmit sequence Receive sequence This concludes our tutorial on the features and operations of the TOUCAN bus. In this tutorial, we discussed the CAN bus specification and layered architecture. We examined the message buffer structure and the different frame formats. We identified the fields used in data frames and remote frames, and discussed the differences between the Standard and Extended frame formats. We took a detailed look at the three error confinement states: Error Active, Error Passive, and Bus Off. We discussed bit timing and synchronization. Finally, we examined the various TOUCAN registers, and discussed the processing sequence for transmitting and receiving message frames. 40