Control and Spy the TELL1. Cédric Potterat EPFL LPHE

Transcription

1 Control and Spy the TELL1 Cédric Potterat EPFL LPHE 1

2 outlines ECS control PVSS for TELL1 DIM, fwccpc, fwhw Status Recipes outlook 2

3 PVSS CERN Used for the slow control systems by all LHC experiments Open Architecture and Highly Distributed 3

4 LHCb Experiment Control System (ECS) ECS is in charge of the configuration, control and monitoring of all the components of the online system (all devices in DAQ, detector control, trigger, timing and the interaction with the outside world). 4

5 ECS FSM ECS INF DCS HV DAI DAQ L0 TFC HLT LHC VELOC VELOA VELOC DCS DCS VELOA VELOC HV HV VELOA VELOA VELOC VELOC LV TEMP LV TEMP VELOA VELOC DAI DAI VELOA VELOC DAQ DAQ VELOA VELOC FEE FEE The Finite State Machine which controls the ECS uses the State Management Interface (SMI++) SMI ++ gives the parallelism and actions can be triggered by logical conditions Commands VELOA Status & Alarms VELO VELOA VELOC TELL1 TELL1 5

6 TELL1 PVSS Project Some useful tools: Distributed Information Management System DIM (fwdim, fwccpc, ccserv) fwhw The third release: fwtell1 v1r3 6

7 DIM (1) Interface from ECS to hardware realized with the Distributed Information Management System (DIM) a portable lightweight communication layer: DIM server (ccserv) running on CCPC publishes services to DIM Name Server (DNS) from where the client (ECS) can subscribe to it. Data exchange peer to peer from server to client. Client sends commands (write/read) server updates services (data/status) Portability: Clients can be installed on any machine just specifying DNS node (no need to take care of connectivity) Robustness: If server crashes it can easily republish on DNS node 7

8 ~ 500 (commands) DIM (2) Register services Lphe1pc25 (windows) Request services >% dns & Client Name Server (DIM_DNS_NODE = lphe1pc25) lphe1pc7 ( linux) Subscirbe to service Commands lphe1tell4 Service info Server (ccserv) Service Data TCP/IP 8

9 fwhw Introduced a tool to model hardware as PVSS Datapoint: hides diversity and complexity of the various hardware/bus types takes care of the communication with the Tell1 (using DIM) framework function calls by register name e.g. for ST : 598 registers DP 9

10 Finite State Machine Further abstraction as finite state machines (SMI++): defined transition from one state of the board into another with possibility to autorecover Device Units: act on hardware (data points) state can be triggered by hardware Control Units: send commands to children (DU) state transition when children change Firmware can be downloaded to board in state NOT_READY Configuration of board (mainly writing registers) via recipes downloaded from Configuration Database (different settings for different run conditions) (Final Goal) 10

11 Tell1 Control Unit An example for a Tell1 CU panel states of children (DUs) define state of CU commands are propagated downwards partitioning of the system is a key feature (partitions can have their own trigger) clicking on device unit allows to open operator panels for the device (boards) 11

12 Tell1 Device Unit Screenshot of a Tell1 DU panel operator interface: identifies board type evaluates malfunctioning parts of the board quick overview of important counters and registers reconfiguration of refresh rate 12

13 Tell1 Device Unit registers (=data points) can be connected to callback functions which allow to evaluate the functionality of subcomponents (inside Ctrl script) error recovery or alerts can be implemented 13

14 Tell1 Device Unit these panels are built to replace the console_tell1 with the most user friendly display 14

15 Tell1 Device Unit From the configuration panel, the most used configs can be changed : Who send the trigger info If ECS: nb of trigger per DAQ Loop consecutive trigger number wait cycles btw trigger Who send the Dest Ip If ECS: MEP Factor Who send the Trigger Type If ECS: NZS or Physics Enable/Disable the data generator The bank class value Enable/Disable the error bank 15

16 Tell1 Device Unit GbE Panel: All the rates can be check and the GbE configuration can be changed:: Enable/Disable the GBE Port on the SL FPGA Dest/Src IP & Mac Addresses 16

17 Spying on the Data The User Specific Panel is different for every SubDetector. From here you have access to the user specific monitoring register of the ECS. For ST (from ECS Doc) : 12 PEDESTAL RAM 12 HIT_THRESHOLD RAM 12 CMS_THRESHOLD RAM 1 ST_AVERAGE_HISTOGRAM 1 ST_SLOPE_HISTOGRAM from the Data Mon Panel, you have access to the last 4 MEPs written in the MEP Buffer 17

18 Tell1 DU ST zero suppressed bank 31 MSB 8 bit LSB MSB 8 bit LSB MSB 8 bit LSB 8 Size in byte,16 Source ID,16 R,7 SO,1 Number of clusters,16 Cluster strip position, 12 ADC, 7 ISP,2 Event Banks 31 MSB MEP header #1 Zero suppressed data Event #n MEP Sub header Event #n+1 Transport Opaque Data Event #n+2 B ank body Section A Bank header #1 32 bit Cluster strip position,12 ISP,2 ADC, 7 Neighbouring strip sum, 8 EOC,1 1 Complete PP0 data 4x224 byte 31 MSB PP0 A[0..71] Section B PP0 B[0..71] Section C PP0 C[0..71] 32 bit LSB 0 31 MSB PP0 A[0] PP0 B[0] PP0 C[0] PP0 A[1] PP0 B[1] PP0 C[1] 32 bit LSB 0 Bank Header [0..1] the different banks in the MEP are decoded PP0 Data[ ] PP1 Data[ ] PP0 A[71] PP0 B[71] PP0 C[71] PP2 Data[ ] PP3 Data[ ] PP0 Event info [0..7] Event info ADC, 7 Complete Bank data 3592 byte LSB 0 Bank header #3 Error data ISP,2 Cluster size,1 Neighbouring strip sum, 8 Bank header #2 Non zero suppressed data Cluster strip position,12 SO,1 ADC, 7 Section A,B and C data MEP SO,1 Cluster size,1 EOC,1 1 Neighbouring strip sum, 8 EOC,1 1 Pading «00»,8 LSB 0 Type,8 PCN,8 Pading «0000»,16 EOC,1 0 8 bit Version,8 Error,1 Cluster size,1 7 MSB Magic pattern,16 0xCBCB PP0 Event info [0..7] Event #n+3 Error bank for «VELO and ST» Event information, 8 Bank list, 8 Detector ID,4 BCnt,12 L0 EvID, 32 Cluster data section length,16 Process info, 8 optional ADC data section length,16 PCN, 8 Number of cluster, 16 Error bank length, 16 0x8E 0x00 Cluster data section length,16 0x8E 0x01 ADC data section length,16 0x8E 0x02 Non zero suppressed bank length,16 0x8E 0x03 Pedestal bank length,16 0x8E 0x04 5 word PP FPGA info, 32 optional For PP3 PP0 ST case PP3 18

19 ST case ZS Data If there are more than one SEP in the MEP If the error bank is attached Zoom button If the NZS bank is attached evt Info If the pedestal bank is attached, the button appears 19

20 VELO case 20

21 FwTell1_v1r3 datapoint type (representation inside ECS) for common part (SiORx) as well as some complete subdetectors (VELO, OT, ST, MUON, L0DU) Control unit and device units provided (FSM) Plenty of panels to operate on board (including pop ups 63 panels!) Configuration with.cfg file and remote programming (.pof &.jam) 21

22 fwtell1 Are we ready and out of the PVSS fog? 22

23 Recipes: Recipes are holding the content of a defined group of registers. Content can be retrieved from cache or configuration DB and is applied to hardware when configuring. recipe type: defines what registers belong to recipe (e.g. Beetle regs) recipe: a type can have several recipes accomplishing different tasks (e.g. Beetle settings for cosmics, physics...) Status: Interface implemented in FwHw tool now also respecting masked operation (Note: mask is just sent with data when requested/applied!) Framework functions available (save, apply, read recipes) The download of the.cfg file still needed to create the recipes 23

24 The role of the.cfg file: To edit all the memory banks by hand (e.g. pedestals, etc.) would be quite time consuming! Download.cfg file and configure board.cfg file Read registers and save the values as recipes to be stored in configuration database 24

25 Recipes Panels Three type of Recipes will be (are already) created : CMN_CMN CMN_NET (inculuded the GbE part) SPCF (different for each sub det) 25

26 Conclusion Development finished at lower level except some slight modifications due to bugs etc. User requests received till end of April will be implemented immediately (later they might be put on a queue) Concerning recipes we might do again the specific part for one or two subdetectors (VELO/ST) Important to make tests (benchmarking) with the configuration of many boards Trying to understand the bigger picture and improving the FSM part to what it should look like by the end of the year 26

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28 Where are we now? 28

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