Project Overview. Chipcon Transceiver. Transceiver Overview (1) Transceiver Overview (2) EECS150 Spring 2006 Lab Lecture #8

Transcription

1 Project Overview Chipcon Transceiver EECS150 Spring 2006 Lab Lecture #8 David Lin N64 Controller User input to your game. Video Game output to the user. Chipcon Transceiver: the FUN Two-Week One! =) Bidirectional communication between games. Game Engine Drives game play. Glue logic. Handles communication handshaking. 3/10/2006 EECS150 Lab Lecture #8 1 3/10/2006 EECS150 Lab Lecture #8 2 Transceiver Overview (1) 3 rd party chip mounted on expansion board. Uses a PCB antenna. Take a look! IEEE standard support. Zigbee ready. Transmits on unlicensed 2.4 GHz spectrum. 16 communication channels. Overlaps with Wi-Fi. 250 kbps maximum data rate. We will only be using a very small percentage of this. Configure, send, receive, and issue commands to chip over SPI to CC2420 registers. Transceiver Overview (2) 33 configuration registers. We change 3 of them. 15 command strobe registers. We issue 6 of them. These change the state of the CC2420 internal FSM. 128-byte RX FIFO & 128-byte TX FIFO Accessed via 2 additional registers. Also accessible as RAM (i.e. by addressing). Only for debugging! Probably not necessary. 3/10/2006 EECS150 Lab Lecture #8 3 3/10/2006 EECS150 Lab Lecture #8 4

2 VREG_EN RF_RESET_ CC2420 Inputs & Outputs FPGA Single bit status signals. High level transceiver operation information. Initialization signals. Drive signals once and forget about it. SPI interface. Interface to rest of chip via CC2420 registers. Send, receive, configuration, detailed status. 3/10/2006 EECS150 Lab Lecture #8 5 Single Bit Status Indicators FIFO Goes high when there s received data in RX FIFO. FIFOP Goes high when # bytes received exceeds set threshold. CCA Indicates that the transmission medium (air) is clear. Only valid after 8 symbol periods in RX mode. SFD Goes high after SFD is transmitted & low after packet completely sent. 3/10/2006 EECS150 Lab Lecture #8 6 SPI Interface Serial interface with 4 wires: SClk Clock signal you generate. CS_ Active-low chip select. SI Output to the CC2420. SO Input from the CC2420. Described earlier in class lecture. Interface to the chip! Initialization, configuration, TX, RX, detailed status. Luckily for you, it s provided as a black box. 3/10/2006 EECS150 Lab Lecture #8 7 CC2420-specific SPI (1): First Byte 7 1 = RAM access (not used) 0 = register access Sent First 6 1 = read 0 = write Bit Position Sent Later 5:0 Address of register. Refer to p. 60 of the datasheet. First byte always has above format. Bit 7 Set to 0 for register access. Bit 6 Read/write control. Bits 5:0 Address of register. P. 60 of datasheet. Followed by data specific to register being accessed. 3/10/2006 EECS150 Lab Lecture #8 8

3 Sent on SI Received on SO CC2420-specific SPI (2): Writing to Configuration Reg. Sent First Byte Number Sent Later address byte, described above status byte First byte followed by 2 bytes of configuration data. Data on SO invalid here bits of data to be written to register 16 bx Transceiver replies when first byte is sent out with status byte. True for all SPI accesses. Not necessary to inspect, but can be helpful for debugging! 3/10/2006 EECS150 Lab Lecture # CC2420-specific SPI (3): Issuing Command Strobes Sent on SI Received on SO address byte, described above status byte Byte Number One byte only. Nothing follows. Address sent indicates the command strobe being issued. Note that 0x00 is NO OP. This is useful for explicitly retrieving status byte. 3/10/2006 EECS150 Lab Lecture # CC2420-specific SPI (4): Saving to TX FIFO CC2420-specific SPI (5): Receive from RX FIFO Sent on SI Received on SO Sent First Byte Number Sent Later 1 2 to n address byte, described above data bytes to be transmitted status byte Received First Byte Number Received Later 1 2 to n Sent on SI address byte, described above 8 bx Received on SO status byte data from the RX FIFO After first byte, send n bytes of data to transmit over wireless. SPI session only ends when CS_ is pulled high. CC2420 replies with a new status byte with each byte that s saved to FIFO. 3/10/2006 EECS150 Lab Lecture #8 11 After first byte, send a n bytes of don t care in order to receive data. During first byte, CC2420 replies with status. Subsequent bytes are data saved in FIFO. Must be careful not to request data from empty FIFO! SPI session only ends when CS_ is pulled high. Reading from a configuration register is the same. 3/10/2006 EECS150 Lab Lecture #8 12

4 Configuration Registers Command Strobe Registers Register MDMCTRL0 FSCTRL IOCFG0 Address 0x11 0x18 0x1C Bit(s) of Interest 11 9:0 6:0 Purpose Turn off automatic address recognition. You must set bit 11 to 1 b0. Channel changing. Changes the threshold of number of bytes in RX FIFO before FIFOP goes high. Defaults to 64. You may want to change this value. Register SNOP SXOSCON SRXON STXON SRFOFF SFLUSHRX Address 0x00 0x01 0x03 0x04 0x06 0x08 Purpose No operation. Turns on the crystal oscillator and will be used as part of the initialization process. Moves the CC2420 into the receive state and will be used as part of the initialization and channel changing process. Instructs the CC2420 to transmit the data contained in the TX FIFO. Turns off RX/TX and frequency synthesizer and will be used as part of channel changing. Flushes the RX FIFO. This command will be used a lot! 3/10/2006 EECS150 Lab Lecture #8 13 3/10/2006 EECS150 Lab Lecture #8 14 TX/RX FIFO Registers Initialization Wait a few ms. Register TXFIFO RXFIFO Address 0x3E 0x3F Purpose For saving bytes to transmit into the TX FIFO. You must not write data to the FIFO while a transmission is in progress. For retrieving bytes from the RX FIFO. Assert VREG_EN. Pulse RF_RESET_. Issue SXOSCON. Not running. Check if oscillator s running. Running. Issue SRXON to enter receive state. Lower FIFOP threshold (optional). Change to assigned channel. Turn off address recognition. 3/10/2006 EECS150 Lab Lecture #8 15 3/10/2006 EECS150 Lab Lecture #8 16

5 Transmit Receive (1) Save data into TX FIFO. Not clear. Check CCA signal. Clear. SFD low to high. SFD low to high. Issue STXON. Wait. Wait. At least 60 clock cycles. Return to Start state. 3/10/2006 EECS150 Lab Lecture #8 17 3/10/2006 EECS150 Lab Lecture #8 18 Receive (2) Packets are only received after CC2420 has spent 12 symbol periods in receive mode. There must be wait time between transmissions. Allows the transceiver to look for and receive data. Announcements Next week s lab lecture is Thursday 8-9P. Come with questions! Groups have been assigned channels and addresses. Check online grade book. 3/10/2006 EECS150 Lab Lecture #8 19 3/10/2006 EECS150 Lab Lecture #8 20

6 Design Structure (1) Design Structure (2) Transceiver Highest level block. 32-bit input/output, channel changing, addressing. SPI Abstraction Takes care of details of CC2420 SPI interface. Arbitrates between TX/RX. SPI (provided) Handles details of interface timing. SPIFifo (provided) Storage place for filtered, received data. 3/10/2006 EECS150 Lab Lecture #8 21 3/10/2006 EECS150 Lab Lecture #8 22 Packet Format Channel & Addresses Preamble 4 bytes 0x00 SFD 1 byte 0x7A Length 1 byte 0x08 Source 1 byte sender s addr. recipient s addr. or 0xFF for broadc ast 4 bytes On transmit, 0x00. On receive, bit 7 of the 2 nd byte is 1 when CRC ok, 0 otherwise. 3/10/2006 EECS150 Lab Lecture #8 23 Dest. 1 byte MPDU Payload data Frame Check Sequence (CRC) 2 bytes On transmit, only fill TX FIFO starting with length byte. Preamble & SFD automatically appended. Transmit all zeros for CRC. CC2420 will replace. There are 16 channels. Your group has been assigned a channel. You must be able to change channels without reset! Address are 8-bits wide 256 addresses. Zero is unused. 0xFF is reserved for broadcast. Your group has been assigned 2 addresses. 3/10/2006 EECS150 Lab Lecture #8 24

7 Interference & Debugging Roughly 2-3 groups per channel. Each group in a particular lab has distinct channel. Can also pick up data on neighboring channel. Very first goal is robust channel changing during initialization. Can pick up packets sometimes. Your module must recover gracefully. Your project interferes with Wi-Fi & vice versa. Handshaking: InRequest/Invalid SPI uses a variation of this. You may want to use this internally. 3/10/2006 EECS150 Lab Lecture #8 25 3/10/2006 EECS150 Lab Lecture #8 26 Handshaking: Ready/Start Debugging Tools Chipscope! We will be releasing some debugging utilities. Packet sniffer. Packet counter. Transceiver uses this interface for input & output. 3/10/2006 EECS150 Lab Lecture #8 27 3/10/2006 EECS150 Lab Lecture #8 28

8 Get Started! Don t count on spring break. This is meant to replace a ~50 hour (avg.) SDRAM checkpoint. There are many subtleties that you must address (e.g. when are RX flushes used?). I will monitor newsgroup over spring break, but less frequently. Next week s lab lecture is CP3 Q&A. Come with questions. Read the datasheet! 3/10/2006 EECS150 Lab Lecture #8 29