Structure (1A) Component

Transcription

1 Component

2 Copyright (c) 2012 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". Please send corrections (or suggestions) to youngwlim@hotmail.com. This document was produced by using OpenOffice and Octave.

3 Entity and Architecture ent_a arch_a entity ent_a is architecture arch_a of ent_a is end ent_a; end ent_a; Component 3

4 Many Architectures ent_a arch_a1 architecture arch_a1 of ent_a is end ent_a; entity ent_a is end ent_a; arch_a2 arch_a3 architecture arch_a2 of ent_a is end ent_a; architecture arch_a3 of ent_a is end ent_a; Component 4

5 Entity Architecture Binding ent_a arch_a1 ent_c ent_b arch_a2 arch_c1 arch_a3 arch_c2 arch_b1 arch_b2 Component 5

6 Hierarchical Component Entity Name ee Architecture Name aa U2:comp3 U3:comp2 U4:comp4 Component Declaration component comp1 is end comp1; component comp2 is end comp2; component comp3 is end comp3; component comp4 is end comp4; Only external view of a component Component Name comp1 comp2 comp3 comp4 Types and directions of a component ports Component 6

7 Componet Declaration Entity Name ee Architecture Name aa U2:comp3 U3:comp2 U4:comp4 Component Declaration component comp1 is end comp1; component comp2 is end comp2; component comp3 is end comp3; component comp4 is end comp4; Component 7 architecture aa of ee is begin end aa; Component Instantiation U1: comp1 port map ( ); U2: comp2 port map ( ); U3: comp3 port map ( ); U4: comp4 port map ( );

8 Component Instantiation Entity Name ee Architecture Name aa U2:comp3 U3:comp2 U4:comp4 Component Name architecture aa of ee is Instantiation Label begin Component Instantiation U1: comp1 port map ( ); U2: comp2 port map ( ); U3: comp3 port map ( ); U4: comp4 port map ( ); end aa; Component 8

9 Port Map Entity Name ee Architecture Name aa U2:comp3 U3:comp2 U4:comp4 Component Declaration component comp1 is end comp1; architecture aa of ee is begin Component Instantiation Local => Actual U1: comp1 port map ( ); U2: comp2 port map ( ); U3: comp3 port map ( ); U4: comp4 port map ( ); end aa; Component 9

10 Positional & Named Associations Entity Name ee Architecture Name aa U2:comp3 U3:comp2 U4:comp4 port (I0, I1; in std_logic; O; out std_logic); Local Port => Actual Signal Positional Association port map (A, B, TMP1); Named Association port map (I0=>A, I1=>B, O=>TMP1); architecture aa of ee is Component Declaration component comp1 is end comp1; begin Component Instantiation end aa; U1: comp1 port map ( ); U2: comp2 port map ( ); U3: comp3 port map ( ); U4: comp4 port map ( ); Component 10

11 Configuration Entity Name ee Configuration: Bind component instances to entities Also specify which architectures are used for those bound entities Architecture Name aa U2:comp3 U3:comp2 U4:comp4 ent_a arch_a1 architecture aa of ee is Component Declaration component comp1 is ent_b arch_a2 end comp1; begin Component Instantiation arch_b1 arch_b2 arch_a3 end aa; U1: comp1 port map ( ); U2: comp2 port map ( ); U3: comp3 port map ( ); U4: comp4 port map ( ); Component 11

12 References [1] [2] J. V. Spiegel, VHDL Tutorial, [3] J. R. Armstrong, F. G. Gray, Structured Logic Design with VHDL [4] Z. Navabi, VHDL Analysis and Modeling of Digital Systems [5] D. Smith, HDL Chip Design [6] [7] VHDL Tutorial - VHDL onlinewww.vhdl-online.de/tutorial/