HW / SW Implementation Overview (0A) Young Won Lim 7/16/16

Transcription

1 HW / SW Implementation

2 Copyright (c) Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". Please send corrections (or suggestions) to youngwlim@hotmail.com. This document was produced by using OpenOffice and Octave.

3 HW Implementation ASIC (Application Specific Integrated Circuit) RTL design clk) if (load) q = d; Logic Synthesis Gate netlist Physical Synthesis i s i1 U U 2 s b U 1 a a 1 U 3 z clk D Q mask GDS 3

4 NAND Gate A Transistor Level A Layout A Gate Level A Wafer processed 4

5 SW Implementation C++ / Java Code int i, s=; for(i=; i<1; ++i) s+= i; Compile Assembly Code addi $s1, $, add $s, $, $ addi $t, $, 1... Link with libraries ELF 5

6 OS Kernel Process Management Multitasking Interrupts Modes Memory Management Virtual Memory Disk access File System Device Drivers 6

7 Interrupt Asynchronous INT ISR2 ISR2 Hardware Interrupt User Mode Non-user Mode Synchronous Software Interrupt Instruction SWI ISR4 ISR4 INT x8... Software Interrupt User Mode Non-user Mode 7

8 Interrupt and Parallelism Asynchronous INT ISR2 ISR2 Hardware Interrupt User Mode Non-user Mode Two parallel threads of execution Simulate parallelism Time sharing 8

9 Timer & Interrupt Timer TRG_IncTick() INT TMR_Init() ISR CheckCallbacks() Hardware Interrupt void main(void) { TMR_Init(); TRG_Init(); EnableInterrupt(); callback(data) } TRG_SetTrigger( ); for ( ; ; ); Setting callback function & data 9

10 Multi-tasking Time Slice Time Sharing Round Robin Scheduling Context Switching Task A Thread Task B Thread Task C Thread timer tick interrupt A B C A B C 1

11 GPIO read from port address write to port address D Q write to port direction register D Q 11

12 HW (ASIC) & SW Implementations HW (ASIC) RTL design SW C++ / Java Code Logic Synthesis Compile Gate netlist Assembly Code GDS Physical Synthesis Parallelism is ensured by spatial allotment in a chip ELF Link with libraries Parallelism is ensured by temporal processing on a processor 12

13 FPGA Architecture A Logic Block FPGA (Field Programmable Gate Array) A Configurable Interconnection 13

14 Implementing Boolean Functions Memory Size : 2 3 x 1 x y z F A Logic Block address 3bits 1 index inputs output Data 1 bit A Truth Table LUT (Look up table) Combinational Logic 14

15 Configuring Logic Blocks A Logic Block LUT SRAM cells An 2-bit SRAM cell select 15

16 Configuring Interconnections An 1-bit SRAM cell An 1-bit SRAM cell 16

17 HW (FPGA) Implementations HW (FPGA) RTL design Logic Synthesis An 1-bit SRAM cell An 1-bit SRAM cell Gate netlist * LUTs, FF, etc Physical Synthesis Programming File FPGA configuration information An 2-bit SRAM cell select LUT SRAM cells 17

18 HW (FPGA) & SW Implementations HW (FPGA) RTL design Gate netlist Logic Synthesis SW C++ / Java Code Compile Assembly Code Physical Synthesis Link with libraries Programming File FPGA configuration information ELF FPGA configuration information Machine Instructions of a processor 18

19 References [1] [2] D.M. Harris, S. L. Harris, Digital Design and Computer Architecture