Control & Status Registers. Young Won Lim 4/22/16

Transcription

1 Control & Status Registers

2 Copyright (c) Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free ocumentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free ocumentation License". Please send corrections (or suggestions) to youngwlim@hotmail.com. This document was produced by using OpenOffice.

3 csrgen Based on Chuck Benz ASIC and FPGA esign csrgen - generate verilog RTL code for processor memory maps in ASIC/FPGA designs 3

4 Module Interface 4

5 Module Interface System BUS I/F clk reset_l up_din up_addr up_csl up_rwl status1 stickybit1 stickybit2 4 6 example_lp 12 2 up_dout up_dout_enl control1 control2 repeatingfield0 repeatingfield1 morerepeat Status info from the peri-device Control signal to the peri-device 5

6 Module Interface address bus data bus clk reset_l up_din up_addr up_csl up_rwl status1 stickybit1 stickybit2 4 6 example_lp 12 2 up_dout; up_dout_enl; control1; control2; repeatingfield0; repeatingfield1; morerepeat; addr rdata wdata Peripheral evice Processor 6

7 Memory Access Operations Memory CPU Memory CPU WR n-bit ata k-bit Address R n-bit ata k-bit Address 7

8 Memory R & WR Operations Input n-bit word Memory CPU k-bit address n-bit ata Bus WR Mem_En R/WR Memory Unit 2 k words n-bit per word k-bit Address Bus Memory CPU R Output n-bit word n-bit ata Bus k-bit Address Bus

9 Memory-mapped IO Operations Peri- evice Memory CPU WR ata Bus For normal memory address Address Bus Peri- evice Memory CPU R For I/O device address ata Bus Address Bus 9

10 System Bus Interface address bus data bus control bus clk reset_l up_din up_addr up_csl up_rwl status1 stickybit1 stickybit2 4 6 example_lp 12 2 up_dout; up_dout_enl; control1; control2; repeatingfield0; repeatingfield1; morerepeat; 10

11 System Bus Registers address bus data bus control bus up_din up_din up_dout_ up_dout up_addr up_addr up_dout_enl up_csl up_csl up_csl up_csl up_csl up_rwl up_rwl up_rwl 11

12 System Bus ata Registers address bus data bus control bus up_din up_din up_dout_ up_dout Control_Sig_ Control_Sig Status_Sig 12

13 Combinational Logic Block Sensitivity Lists default assignments Control_Sig <= Control_Sig_ <= up_din up_dout <= up_dout_ <= Status_Sig 13

14 Reg Signal 14

15 Control register input signals Control_Sig_ <= up_din up_din up_din Control_Sig_ Control_Sig 15

16 Address ecoder A0 A1 up_addr[2:0] A2 A3 A4 A5 A6 A7 16

17 From up_din to control register input signals (up_csl &!up_csl &!up_rwl) IE if (IE & A0) if (IE & A1) up_din[7:0] if (IE & A2) up_din[7:0] if (IE & A3) up_din[3:0] if (IE & A4) if (IE & A5) up_din[7] if (IE & A5) ((stickybit2s_ & ~up_din[6]) stickybit2) if (IE & A6) up_din[7] if (IE & A6) up_din[6] if (IE & A7) up_din[7] if (IE & A7) up_din[6] control1_[7:0] control2_[7:0] control2_[11:] stickybit1s_ stickybit2s_ repeatingfield0_ morerepeat_[0] repeatingfield1_ morerepeat_[1] 17

18 Control Register Input Condition (up_csl &!up_csl &!up_rwl) IE A0 A1 up_csl up_csl up_csl up_addr[2:0] A2 A3 A4 A5 A6 A7 up_csl up_csl Chip Select write up_csl up_rwl 1

19 Control Register Timing iagram up_csl up_csl Chip Select write up_csl up_rwl up_addr up_din up_din Control_Sig up_din up_din Control_Sig_ Control_Sig 19

20 FlipFlop with Enable if (IE & A0) AA_ AA AA_ IE A? EN AA EN 0 1 CK 20

21 Control Register Input from in (up_csl &!up_csl &!up_rwl) IE A0 A1 up_csl up_csl up_rwl IE up_addr[2:0] A2 A3 A4 A5 A6 A7 if (IE & A0) AA_ AA up_din up_din AA_ IE A? EN AA AA Control Register 21

22 Stickybit Registers up_din up_din[7] stickybit1s_ stickybit1s OE A5 IE A5 EN stickybit2s_ up_din up_din[6] stickybit2s stickybit2 IE A5 EN 22

23 Stickybit Registers Combinational Feedback Loop up_din[6] stickybit2s_ stickybit2 High stickybit2 from peri device turns on the feedback loop This H can only be turned off by H up_din[6] H pulse turns on the loop Stable Loop Stuck-At set_false_path STA command H pulse turns off the loop 0 23

24 Stickybit Registers related code segments 24

25 RepeatingField Registers related code segments 25

26 Write Registers clk reset_l up_din up_addr up_csl up_rwl status1 stickybit1 stickybit2 4 6 example_lp 12 2 up_dout; up_dout_enl; control1; control2; repeatingfield0; repeatingfield1; morerepeat; addr data Peripheral evice Processor control1_ control2_ 12 control1 control2 12 control1 control2 stickybit1s_ stickybit1s stickybit1s stickybit2s_ stickybit2s stickybit2s repeatingfield0_ repeatingfield0 repeatingfield0 repeatingfield1_ morerepeat_ 2 repeatingfield1 morerepeat 2 repeatingfield1 morerepeat 26

27 Output data register input signals up_dout_ <= Status_Sig Status_Sig up_dout_ up_dout 27

28 Input data to up_dout register (up_csl &!up_csl & up_rwl) OE if (OE & A0) {devicei, version} if (OE & A1) control1 if (OE & A2) control2[7:0] if (OE & A3) {4'b0000, control2[11:]} if (OE & A4) {2b00, status1} if (OE & A5) {stickybit1s, stickybit2s, 6'b000000} if (OE & A5) 0 if (OE & A6) {repeatingfield0, morerepeat[0], 6'b000000} if (OE & A7) {repeatingfield1, morerepeat[1], 6'b000000}; up_dout_[7:0] up_dout_[7:0] up_dout_[7:0] up_dout_[7:0] up_dout_[7:0] up_dout_[7:0] stickybit1s_ up_dout_[7:0] up_dout_[7:0] 2

29 Status Register Output Condition (up_csl &!up_csl & up_rwl) IE A0 A1 up_csl up_csl up_csl up_addr[2:0] A2 A3 A4 A5 A6 A7 up_csl Chip Select Read up_csl up_csl 29

30 Output ata Register Timing iagram up_csl up_csl Chip Select write up_csl up_rwl up_addr up_din Status_Sig up_dout up_dout_enl Status_Sig up_dout_ up_dout 30

31 From Status Signals to out (up_csl &!up_csl &!up_rwl) OE up_csl up_csl up_rwl OE up_addr[2:0] {devicei, version} control1 control2[7:0] {4'b0, control2[11:]} {2b0, status1} up_dout_[7:0] up_dout {stickybit1s, stickybit2s, 6'b0} 0 OE EN {rptfd0, mrpt[0], 6'b0} {rptfd1, mrpt[1], 6'b0}; 31

32 Read Status Registers clk reset_l up_din up_addr up_csl up_rwl status1 stickybit1 stickybit2 4 6 example_lp 12 2 up_dout; up_dout_enl; control1; control2; repeatingfield0; repeatingfield1; morerepeat; addr data Peripheral evice Processor {devicei, version} control1 control2[7:0] {4'b0, control2[11:]} {2b0, status1} {stickybit1s, stickybit2s, 6'b0} 0 {rptfd0, mrpt[0], 6'b0} {rptfd1, mrpt[1], 6'b0}; up_dout_[7:0] up_dout_[7:0] up_dout_[7:0] up_dout_[7:0] up_dout_[7:0] up_dout_[7:0] stickybit1s_ up_dout_[7:0] up_dout_[7:0] 32

33 FF Inference 33

34 34 Registers up_din up_addr up_csl up_csl up_rwl up_dout up_dout_enl version devicei control1 control2 stickybit1s stickybit2s repeatingfield0 repeatingfield1 morerepeat 12 2 up_din up_addr up_csl up_csl up_rwl up_dout_ (up_csl up_rwl) 0 1 control1_ control2_ stickybit1s_ stickybit2s_ repeatingfield0_ repeatingfield1_ morerepeat_

35 Module Skeleton (1) 35

36 Module Skeleton (2) 36

37 ocumentation 37

38 Properties of s (1) 3

39 Properties of s (2) 39

40 Properties of s (3) 40

41 References [1] [2] [3] [4]