Vivado Design Suite User Guide

Transcription

1 Vivado Design Suite User Guide Designing with IP

2 Notice of Disclaimer The information disclosed to you hereunder (the Materials ) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: Copyright Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date Version Revision 03/20/ Added new chapter on using the early release feature called IP integrator. Updated text and graphics to match new features introduced in release /19/ Re-organized the book structure. Updated text and graphics to match new features introduced in release Moved the content describing IP Integrator to a new document titled (UG994) Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator. 07/08/ Changed an AR Number in Other Simulators, page 14. Modified the list of files in Revision Control, page 17. Changed content from one appendix to four appendixes. Added AR Number in the Introduction of Chapter 3, Using IP in a Project. Removed Migrating Legacy IP. Vivado: Designing with IP 2

3 Table of Contents Revision History Chapter 1: IP-Centric Design Flow Overview Introduction Vivado IP Catalog Vivado IP Packager Chapter 2: Creating and Managing Reusable IP The Manage IP Flow Overview Starting the Flow Simulating the IP Vivado Simulator ModelSim/QuestaSim Other Simulators Netlist Simulation Xilinx IP with Third Party Synthesis Tools Revision Control Chapter 3: Using IP in a Project Introduction Using IP in RTL-Based Projects Creating an IP Instance from the IP Catalog Generating and Resetting IP Output Products Adding Existing IP IP States in Project IP Project Settings IP Board Flow Instantiating IP Synthesizing IP Simulating IP Simulating IP with the RTL Design Simulating with Other Simulators Constraining IP in a Design Using an IP Example Design Reporting IP Status and Upgrading IP Vivado: Designing with IP 3

4 Tcl Commands for Common IP Operations Chapter 4: Packaging IP IP Packaging Basics and Usage Flow IP Packaging Flow IP User Flow Repository Management IP Catalog IP Customization and Generation IP Packaging Verification IP Packager Inputs Input File Groups Minimum File Set Required for Packaged IP IP Packager Outputs IP Design File Output Package Organization Other Files Written to the Output Package IP Packaging Steps Package an Existing Vivado Project or Create a New Project Packaging the Project as IP Adding New IP to the IP Catalog Adding Non-HDL Files to the IP Package Appendix A: IP Files and Directory Structure Introduction IP Directory Common File Appendix B: Vivado IP Optimization Introduction Stand-Alone IP Characterization Methodology The Fmax Margin System Methodology Tool Options and Other Factors Appendix C: Vivado Design Suite IP vs ISE CORE Generator IP Introduction Using Fee-Based Licensed IP Appendix D: Additional Resources Xilinx Resources Solution Centers References Vivado: Designing with IP 4

5 Chapter 1 IP-Centric Design Flow Overview Introduction The Xilinx Vivado Integrated Design Environment (IDE) provides an IP-centric design flow that lets you add IP modules to your design from various design sources, as illustrated in Figure 1-1. X-Ref Target - Figure 1-1 The environment contains a central IP catalog repository that consolidates IP sources from the following: Vivado Design Suite IP Modules from System Generator for DSP designs (MATLAB/Simulink algorithms) and Vivado High-Level Synthesis designs (C/C++ algorithms) Third party IP Figure 1-1: User design packaged as IP using the Vivado IP packager Note: In some cases, third party providers offer IP as synthesized EDIF netlists. You can load these files into a Vivado IDE design using the Add Sources command. There are many ways to work with IP in a design: IP-Centric Design Flow Use the Managed IP Flow to customize IP and create output products, including a Synthesized Design Checkpoint (DCP). Vivado: Designing with IP 5

6 Vivado IP Catalog You can use IP in either Project or Non-Project flows by referencing the created.xci file, which is a recommended method for large projects with many team members. For details see Chapter 2, Creating and Managing Reusable IP. Creating and adding IP within a Vivado Project. Access the IP Catalog in a project to create and add IP to design. You can store the IP either inside the project or save it externally to the project, which is the recommended method for projects with small team sizes. For details see Chapter 3, Using IP in a Project. Vivado IP Catalog The Vivado IP Catalog (Figure 1-2) provides a central repository for Xilinx, third party and intra-company IP that can be shared across a design team, division or company in a manner that facilitates design reuse. X-Ref Target - Figure 1-2 Figure 1-2: Vivado IP Catalog Vivado: Designing with IP 6

7 Vivado IP Packager The key features of the Vivado IP Catalog include: Consistent, easy access to all Xilinx IP, including building blocks, wizards, connectivity, DSP, embedded, AXI infrastructure and video IP from a single common repository that can be accessed consistently regardless of the end application being developed. Support for multiple physical locations, including shared networked drives, allowing users or organizations to leverage a consistent IP deployment environment for third party or internally developed IP. Instant access to IP customization and generation using the Vivado Integrated Design Environment (IDE) or automated script-based flows using Tcl. On-demand delivery of optional IP output products such as instantiation templates, simulation models (HDL, C, or MATLAB software) and HDL example designs. Integrated IP example designs that provide capability to evaluate IP directly as an instantiated source in a Vivado project. Global RTL synthesis of IP with design with capability to use synthesizable RTL or behavioral simulation models of IP for simulation. Immediate access to version history details as recorded in the Change Log. A <major #.minor #> numbering scheme unifies the IP version numbers. Vivado IP Packager Figure 1-1, page 5 illustrates a unique design feature called IP packager, based on the IP-XACT (IEEE-1685) standard. After you have assembled you your Vivado IDE user design, the IP packager lets you turn your design into a reusable IP module you can add to the Vivado IP Catalog and others can use for design work. Vivado: Designing with IP 7

8 Chapter 2 Creating and Managing Reusable IP The Manage IP Flow Overview The Vivado IDE provides an easy-to-use flow for exploring IP in the IP Catalog, customizing IP, and managing a repository of configured IP. It creates an IP project named managed_ip_project on disk, which facilitates the generation of post synthesis design checkpoints for the IP created by the user. When working in teams, or if the design uses many Xilinx IP, it is recommended that you create and maintain your customized IP in a location outside of the Vivado project structure. This method makes revision control more straightforward and allows customized IP with others. RECOMMENDED: This is also the recommended methodology for working with IP in a non-project, script-based flow The main features of the Managed IP Flow are as follows: Simple IP project interface Quick access to the Xilinx IP Catalog Ability to customize multiple IP Separate, unique directories for each IP instantiation with all files for using the IP User selection to generate RTL or post synthesis design checkpoint (.dcp). A DCP file consists of both a netlist and constraints for the IP Vivado: Designing with IP 8

9 Starting the Flow Starting the Flow Invoke the Vivado IDE, and from the Getting Started page, select Manage IP (Figure 2-1). X-Ref Target - Figure 2-1 Figure 2-1: Invoking the Manage IP Flow When you select Manage IP, a dialog box gives you the following options: New IP Location: Opens a new IP Project at the location specified for exploring the IP Catalog and customizing IP, including generation of output products Recent Customized IP Locations: Lists recent locations from which to open the IP Project for management of existing IP and creation of new IP When you select the New IP Location option, the Open IP Catalog window (Figure 2-2) displays and informs you that a wizard will guide you through the creation of a new customized IP location. X-Ref Target - Figure 2-2 Figure 2-2: Manage IP Flow Start Screen Vivado: Designing with IP 9

10 Starting the Flow Select Next. The Open IP Catalog window (Figure 2-3) opens and asks you to enter the Part, Target language, Target simulator, and IP Location to save the IP Project and any IP that are created or customized. Setting the location has two effects. It does the following: Sets the location where the Vivado IDE creates the managed_ip_project directory Creates the directory to this location for any customized IP X-Ref Target - Figure 2-3 Figure 2-3: After entering this information, click OK. Setting Defaults for the IP Project Session Vivado: Designing with IP 10

11 Starting the Flow The IP Catalog displays, as shown in Figure 2-4. Now you can select and customize IP. The Manage IP option creates a directory for each IP that you customize. X-Ref Target - Figure 2-4 Figure 2-4: New Manage IP Project View of the IP Catalog As shown in Figure 2-5, page 12, if the specified location already contains an IP Project, then a window opens asking if you would like to open the existing project. Select Yes and the existing IP Project opens and shows any customized IP. Select No, and you return to the Open IP Catalog, shown in Figure 2-2 and you can specify a new location. Vivado: Designing with IP 11

12 Starting the Flow X-Ref Target - Figure 2-5 Figure 2-5: Dialog Box Displayed When the Location Already has an IP Project Access to the full Catalog is available, including access to IP Product Guides, Change Logs, Product web pages and Answer Records. After you customize an IP and add it to the IP Project, the Sources and Properties windows display, providing information about what IP is created so far in the project. Figure 2-6 shows a Manage IP Project window. X-Ref Target - Figure 2-6 Figure 2-6: Manage IP Project Window Containing Three IP Vivado: Designing with IP 12

13 Starting the Flow There are 5 main sections to an IP Project window: 1. IP Sources : This section lists the IP that are customized for the project. You can view the output products and manage the generation of additional output products from here. If the output products for an IP are generated (excluding the optional design checkpoint), a check appears on the IP icon. If no output products have been generated for an IP, then no check displays on the IP icon. Note: Besides the.xci file, the instantiation template (.veo or.vho) and BOM file (.xml) are always created for a customized IP. 2. IP Catalog: Lets you explore the entire IP Catalog and create customized IP to add to the IP Project. 3. Details: Displays the details of the selected IP. 4. IP Properties: Displays the detailed information for the selected IP. If IP has been generated this section provides the properties and general details. 5. Design Runs: If a synthesis design checkpoint (.dcp) output product was generated, a run for shows in this view. You can customize and manage multiple IP in this flow. Each IP has results in a directory that the Manage IP option creates at the specified IP location, and the IP directory contains the XCI file and any generated output products. You can view the IP are open or customized from the Vivado IDE Sources window (Figure 2-7). X-Ref Target - Figure 2-7 Figure 2-7: Sources with a Few IP Vivado: Designing with IP 13

14 Simulating the IP Simulating the IP A Manage IP Project is not a full RTL project and does not support simulation of IP directly. To simulate, you reference the customized IP from your design project and simulate within that project. Xilinx delivers the IP in the IP Catalog as RTL source. You can perform behavioral simulation using third party simulators also. For details on logic simulation and supported simulators see the Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 3]. Vivado Simulator The Vivado Design Suite includes a mixed language simulator (Vivado simulator) with direct support in the Vivado IDE. You can launch simulations from within your RTL project directly. Alternatively, to run simulations outside of Vivado simulation environment, use the xsim command. You can produce a run script using the launch_xsim command: launch_xsim scripts_only mode behavioral This produces a script for use with xsim command from the command line with all the file and library information required. For more details, refer to the document Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 3]. ModelSim/QuestaSim Vivado IDE supports ModelSim/QuestaSim for simulation. In the project setting change the simulator to be ModelSim/Questa. You can launch simulations from within an RTL project directly. Alternatively, to run simulations outside of Vivado with ModelSim/Questa you can produce a run script using the launch_modelsim command: launch_modelsim scripts_only mode behavioral This produces a script for use with ModelSim/QuestaSim with all the file and library information required. Other Simulators Xilinx encrypts the Vivado IDE IP using industry standard IEEE P1735 encryption; you can use simulators that support this encryption to do behavioral simulation. Behavioral simulation requires a list of simulation files and the libraries to which they belong. Vivado: Designing with IP 14

15 Simulating the IP The get_files command gets all files that an IP delivers for simulation: Where: get_files -compile_order sources -used_in simulation \ -of_objects [get_files <IP name>.xci] compile_order supports RTL sources only. used_in lets you specify files used in Vivado simulation or synthesis. of_objects takes the IP XCI file object from which all the files related to the IP can then be filtered. For VHDL, you must specify the library associated with each file also. When you use a Tcl script, you can determine this information quickly. The following script prints out each simulation file, and its file path, as well as the associated library: # Get the list of files required for simulation set ip_files [get_files -compile_order sources -used_in simulation \ -of_objects [get_files <IP name>.xci] # For each of these files, get the library information foreach file $ip_files { puts "[get_property LIBRARY $file] $file" } Answer Record [Ref 5] provides scripts for third party simulators from vendors such as Cadence, Synposys and Aldec. Note: Synopsys VCS does not support IEEE P1735 encrypted VHDL files. Many Xilinx IP deliver VHDL source. For these IP, you must generate a functional netlist. Netlist Simulation For netlist simulations, you need to create a structural simulation model for the IP, including the encrypted simulation sources. You might also need to create a structural simulation model to enable a single-language simulation of your design. To create a structural simulation model in a Managed IP project, you must first generate the synthesized design checkpoint output product. To do so: 1. In the IP Sources window, select the customized IP, right-click and select Generate Output Products. The Generate Output Products window opens. 2. Check the Generate Synthesized Design Checkpoint (.dcp) box as shown in Figure 2-8, page 16. Vivado: Designing with IP 15

16 Xilinx IP with Third Party Synthesis Tools X-Ref Target - Figure 2-8 Figure 2-8: Checking the Generate Synthesized Design Checkpoint Box Note: After you generate the DCP file, you can manually open a synthesis design run for an IP and write out a structural simulation netlist using the write_verilog command. Xilinx IP with Third Party Synthesis Tools Only Vivado synthesis supports the Xilinx IP available in the Vivado IDE; including the IP core and any example designs. Xilinx encrypts the HDL files delivered for the IP with the IEEE P1735 encryption and are readable only when using the Vivado IDE. You can use a third party synthesis tool for the user design and generate a netlist that Vivado implementation can use. As an example, when using Synopsys Synplify Pro with a design that has Xilinx IP the recommended flow is: Use the Managed IP Flow in Vivado to create and customize IP needed. Generate a Synthesis Design Checkpoint (DCP) for each IP. The Vivado IDE creates an <IP_NAME>_synplify_stub.v and an <IP_NAME>_synplify.vho file automatically. Vivado: Designing with IP 16

17 Revision Control Add the Verilog stub to the Synplify Pro project or add the VHDL component. The Verilog stub or VHDL component infer a black box for the Xilinx IP, and prevent the synthesis tool from adding I/O buffers. Generate a netlist with Synplify Pro Bring the netlist from Synplify Pro into a Vivado netlist project and add the DCP files for the IP (one DCP file per IP). If you are using a non-project script, you can alternatively use read_edif -verilog for the Synplify Pro netlist and use add_files for the IP DCPs, followed by the link_design command. Implement the entire design with Vivado. The <IP_NAME>_synplify_stub.v and <IP_NAME>_synplify.vho contain synthesis directives that instruct Synplify Pro to not infer I/O buffers for the IP if it connects to top-level ports. Change these directives as required for the third party synthesis tool. Vivado implementation adds any required I/O buffers if they are not already present in the DCP. Revision Control When working with revision control systems and Xilinx IP there are a few possible options. Full: Place the entire IP directory into revision control, including all output products. This is the recommend option as it gives the user the ability to decide when and if to upgrade the IP at a future point. The Vivado IDE only supports one version of an IP in the Catalog. If you upgrade the tool and the IP is no longer current it will be useable still. It will be locked and you will not be able to recustomize, but if all the output products are present it can still be used. Partial: Place the IP XCI file and Synthesis Design Checkpoint (DCP) into revision control. This way the customization of the IP is retained and the IP can be upgraded automatically if desired to the latest version. If you do not want to upgrade you can continue to use the DCP. Minimal: The IP XCI contains all the customization details for the IP and from this all the output products required for synthesis can be regenerated. If the IP is not the latest, it can be upgraded automatically. Scripts: To minimize the number of files committed to revision control you can enter the Tcl commands you use to create and customize the IP into a <IP_specific>.tcl script file. Vivado: Designing with IP 17

18 Revision Control Depending on whether the Synthesis Design Checkpoint (DCP) is produced, you can use Tcl to produce a list of the output products associated with the IP. If the DCP has not been generated, use the following command: get_files -all -of [get_files <IP_NAME>.xci] If the DCP has been generated, you must first set the synthesis run to the IP prior to using the get_files command. After the using the get_files to query the files reset the run: current_run <IP_NAME>_synth_1 get_files -all -of [get_files <IP_NAME>.xci] current_run synth_1 A few files are not returned with this query, you and must add them manually to the revision control: Synthesized Design Checkpoint (.dcp) BOM XCI file (.xml) Memory Interface Generator (MIG) Project file (.prj) Coefficient files (.coe) Synthesis stub files for black box inference (Verilog and VHDL) Vivado: Designing with IP 18

19 Chapter 3 Using IP in a Project Introduction The Vivado Design Suite lets you run the tools using different methods depending on your preference. You can elect to use a project-based method to manage your design process automatically, and design data, also known as Project Mode. When working in Project Mode, the Vivado IDE creates a directory structure on disk that manages design source files, IP, run results, and tracks project status. A runs infrastructure manages the automated synthesis and implementation process and to tracks the run status. You can run the entire design flow with a single click within the Vivado IDE, and the commands are fully scriptable. For more details on the design flows possible with the Vivado Design Suite, see the Vivado Design Suite User Guide: Design Flows Overview (UG892) [Ref 1]. The Answer Record [Ref 8] provides a script that gets all files necessary for source control. Using IP in RTL-Based Projects In RTL-based projects, you can add existing IP from outside the environment or browse the IP Catalog to generate and add IP core instances to your project. The common tasks involved in adding IP sources are as follows: Creating an IP Instance from the IP Catalog Generating and Resetting IP Output Products Adding Existing IP IP States in Project IP Board Flow Instantiating IP Synthesizing IP Vivado: Designing with IP 19

20 Using IP in RTL-Based Projects Simulating IP Constraining IP in a Design Using an IP Example Design Reporting IP Status and Upgrading IP Tcl Commands for Common IP Operations The following subsections describes each task. Creating an IP Instance from the IP Catalog When you create an IP instance from the IP Catalog, you can: Customize the IP for the design Modify an IP core Localize the IP instance The following subsections describe these actions. Customizing IP for the Design You can select an IP from the IP Catalog and customize the IP for use in your design by specifying values for the various parameters associated with the IP core. The Customize IP dialog box presents the parameters of the IP that let you customize the IP for use in your design. This IP interface varies, depending on the type of IP you select, and can include one or more tabs of parameters to enter. You can toggle through these different views by selecting the appropriate tab on the top of the Customize IP dialog box. The Customize IP dialog box also includes the IP symbol, and optionally, includes information such as: Frequency Response graph, Resource Estimates, and AXI4-Stream port structure, depending on the selected IP. The IP symbol supports zooming, resizing, and autofit options consistent with the schematic viewer canvas in Vivado IDE. Figure 3-1, page 21 shows the Customize IP interface for the FIFO Generator IP: Vivado: Designing with IP 20

21 Using IP in RTL-Based Projects X-Ref Target - Figure 3-1 Figure 3-1: Customize IP Dialog Box To customize an IP instance: 1. Select the IP to customize from the IP Catalog. 2. Double-click on the selected IP, or select the Customize IP command from the toolbar or popup menu. When you click Documentation > Product Guide, the supporting IP core documentation opens in your Web Browser. When you click Switch to Defaults, a window displays asking if you wish to reset all configuration options back to their default starting point. 3. After you finish entering the various parameters in the Customize IP interface, click OK. Vivado: Designing with IP 21

22 Using IP in RTL-Based Projects The Manage IP places the IP core along with an instantiation template into the project as a design source. You can then right-click the customized IP core in the Sources view and select Generate Output Products to create the output products for the IP core. The core is not synthesized at this time. After you add IP cores to your project and you run synthesis, the Vivado IDE synthesizes the IP automatically with the sources in the entire design. This lets you quickly instantiate multiple IP cores in your design without the need to synthesize each IP when you add it to the project. When the Vivado IDE adds IP cores to your project those cores display in the Sources view. You can select the IP cores in the IP Sources view to see the various files that make up the core, and to view the properties in the Source File Properties view. Modifying an IP Core To modify an IP core in the Sources view, use Re-customize IP to reopen the Customize IP dialog box, and change any of the parameters associated with the core for this project. You can also select the IP cores in the Sources view, and use Upgrade IP to update the customized IP core to the latest version from the Xilinx IP Catalog, and reapply any customization from the current IP core. After you finish entering the various parameters in the Customize IP interface, click OK. The Generate Output Products window opens as shown in Figure 3-2, page 23. Now, you can either generate the output products by pressing Generate or not generate the output products by pressing Skip. The output products generate automatically as need if they are not generated at this stage. Later you can manually generate output products by selecting the IP in the IP Sources or Hierarchy view and right-clicking and selecting Generate Output Products. Vivado: Designing with IP 22

23 Using IP in RTL-Based Projects X-Ref Target - Figure 3-2 Figure 3-2: Generatiing Output Products You can choose to generate a Synthesized Design Checkpoint (DCP) for the IP. Doing so results in the following: Creation of an IP Design Run for synthesizing the IP Launch of a Vivado synthesis run Inference of a black box when synthesizing the rest of the design Linking of any black boxes for any IP during implementation Using a DCP reduces the run time on synthesizing your design because you do not need to synthesize the IP every time you run synthesis during development. Figure 3-3, page 24 shows the IP in the Hierarchy view where a DCP is generated. The icon shows that a DCP is being used. Vivado: Designing with IP 23

24 Using IP in RTL-Based Projects X-Ref Target - Figure 3-3 Figure 3-3: Synthesized Design Checkpoint (DCP) for an IP in a Design If the DCP is not generated during customization then the core is not synthesized at this time. After you add IP cores to your project and run synthesis, the Vivado IDE synthesizes the IP with the sources in the entire design automatically. This lets you quickly instantiate multiple IP cores in your design without having to synthesize each one as you add it to the project. You can also customize IP with the create_ip Tcl command. For example: create_ip -name fifo_generator -version vendor xilinx.com -library ip -module_name fifo_gen Note: Executing the create_ip Tcl command creates the source files, but does not create any output targets. For information on IP that supports the Vivado Design Suite, see For information on specific IP, see or look at the IP Catalog. See for information on AXI IP. Vivado: Designing with IP 24

25 Generating and Resetting IP Output Products Localizing IP When customizing IP from the IP Catalog you can choose to save the IP directory (see IP Files and Directory Structure in Appendix A for more information on the IP directory) within the project structure (default) or set the location external to the project. You setting the location during the IP customization process using the IP Location, as shown in Figure 3-4. X-Ref Target - Figure 3-4 Figure 3-4: Changing the Location where the IP Directory is Stored Generating and Resetting IP Output Products If you did not generate the output products during customization, you can generate them manually using the Generate Output Products option in the right-click menu of a selected IP. Using this method, the only option is whether to also generate a Synthesis Design Checkpoint or not. The Manage IP feature generates all other output products by default for the IP. You do not need to generating output products because the Vivado synthesis process generates output products automatically when you synthesize the entire design. Using Tcl, you can manually generate various output products selectively (Example designs, Instantiation Template, Simulation, Synthesis) on demand. The Tcl command for this is generate_target. The following is an example of the command: generate_target {instantiation_template synthesis} [get_ips fifo_gen] Where fifo_gen is the name of an IP customization previously used for the module name. Vivado: Designing with IP 25

26 Adding Existing IP To reset the output products use the Reset Output Product option in the right-click menu of a selected IP. This removes all generated output products. If you create a DCP, resetting the output product removes the DCP as well as the associated run. Synthesizing IP, page 34 provides more information about this process. Adding Existing IP You can add previously generated CORE Generator IP (<core_name>.xco instance files) or previously generated Vivado IP (<core_name>.xci instance files) by using the Add Existing IP option in the Add Sources dialog box as shown in Figure 3-5. You can choose whether to point to the previously generated IP or to copy the generated source files into your project. See Chapter 2, Creating and Managing Reusable IP for details on creating IP using the Managed IP flow. X-Ref Target - Figure 3-5 Figure 3-5: Adding Pre-Generated IP Sources Vivado: Designing with IP 26

27 Adding Existing IP X-Ref Target - Figure 3-6 Figure 3-6: Add Existing IP Also, you can add existing IP using the import_ip Tcl command as shown in the following examples: import_ip -file C:/coregen_ip/aurora_8b10b_v7_1.xco -name aurora_8b10b_v7_1 import_ip -file C:/coregen_ip/blk_mem_gen_v6_1.xco -name blk_mem_gen_v6_1 Note: To remotely access an IP, use the read_ip command; this command does not copy IP into the project. The added IP cores display separately in the IP Sources view of the Sources window, as well as with other source files in the Hierarchy, Libraries, and Compile Order views. You can select these cores in the Sources window to see the files that make up the core, and to view the properties in the Source File Properties window. Note: You can also add EDIF, Verilog, or SystemVerilog netlists or NGC files for IP cores into either RTL or netlist-based projects. For more information, "Creating a Post-Synthesis Project" in Chapter 2 of the Vivado Design Suite User Guide: System-Level Design Entry (UG895) [Ref 6]. Vivado: Designing with IP 27

28 IP States in Project IP States in Project There are several states that an IP in a project can be in, depending if it is the current version in the catalog and if you have generated output products. When you add existing IP (either in the XCI or XCO form), if present, the output products (NGC, HDL, etc) are also added. The IP is shown in the Vivado IDE in one of the following states: The current version of the IP is present in Catalog The current version of the IP is present in Catalog and synthesis targets have been generated The IP is locked, with targets. The IP can be used, but it cannot be modified and new output products cannot be created. For example, simulation targets, cannot be created if they are missing The IP is locked with no targets. The IP cannot be used in its current state, errors will be encountered. The following possibilities exist: The IP can be upgraded to the current version in the IP Catalog. No upgrade option is available but IP is still in the Catalog. You must recreate the IP again with the current version or bring in the original output products. No upgrade option is available and the IP is no longer in the Catalog. You must bring in the original output products or the IP cannot be used. Note: For imported IP cores with versions that are not accessible from the Vivado IP Catalog, re-customizing, resetting, and regenerating the IP is not enabled. Vivado: Designing with IP 28

29 IP Project Settings IP Project Settings As shown in Figure 3-7, Global IP project settings are available to help you be more productive when customizing IP. X-Ref Target - Figure 3-7 Figure 3-7: IP Project Settings Vivado: Designing with IP 29

30 IP Board Flow The default settings include the following two major categories: Repository Manager: Specifies directories to add to the IP repositories list. IP can either be packaged by the user or acquired from a third party supplier. After you click Apply, you can see the IP within each repository. Packager: Sets default values for packaging new IP, including vendor, library, and taxonomy. This category also allows you to set the default behavior when opening the IP Packager and allows you to specify file extensions to be filtered automatically. Note: If necessary, you can change the default values for packaging IP during the IP packaging process. The IP Settings and the IP Catalog are only available when working with an RTL project or when using Manage IP from the Getting Started page. IP Board Flow The IP Board Flow feature is supported by some IP and gives you the ability to select board interfaces while customizing an IP. When you use this feature, the creation of physical constraints for the IP is automated by delivering additional XDC constraints in a special _board.xdc file. As shown in Figure 3-8, during the process of creating a new project, you select a board as the default part. X-Ref Target - Figure 3-8 Figure 3-8: Selecting a Board as the Default Part Vivado: Designing with IP 30

31 IP Board Flow Selecting one of the boards listed results in the IP that support the board flow to have a new tab visible during customization (Figure 3-9). X-Ref Target - Figure 3-9 Figure 3-9: Board Tap Visible in Supported IP Customization Figure 3-10 shows that by checking the feature Generate Board based IO Constraints, you are able to associate the IP interface to the available board interface. X-Ref Target - Figure 3-10 Figure 3-10: Associating the IP Interface with the Board Interface When the output products for the IP are generated in the IP Sources view, you see the <IP_name>_board.xdc file listed. This file contains physical constraints assigning ports of the IP to the package pins that connect to the related board connector or device such as a USB port, LED, button or switch. Vivado: Designing with IP 31

32 IP Board Flow Figure 3-11 shows the XDC constraints created for the GPIO IP when the GPI0 interface is connected to the board LCD interface and the GPIO2 interface is connected to the board push buttons. X-Ref Target - Figure 3-11 Figure 3-11: IP Board XCD File The IP that support the board flow are as follows: AXI GPIO AXI Ethernet Lite AXI EMC AXI UART (16550 and lite) AXI IIC Clocking Wizard Proc Sys Reset Vivado: Designing with IP 32

33 Instantiating IP Instantiating IP After you customize the IP and add it to your project, the IP instance displays in the Sources view under IP Sources. Expanding the IP instance in the Sources view displays the /instantiation_template folder and the VHO or VEO file containing the instantiation template that you can copy and paste into your RTL design. Figure 3-12 shows the instantiation template of the FIFO Generator core. X-Ref Target - Figure 3-12 Figure 3-12: To use the instantiation template in your design: Sources View - Instantiation IP RTL Code 1. In the Text Editor, open either the VEO or VHO template file for the IP core and the RTL design file by double-clicking on each source file in the Sources view, or by selecting the files and using the Open Files option. 2. Select the Instantiation Template in the VEO or VHO template file and copy it to the open RTL design at the appropriate location. 3. Edit the RTL to integrate the IP template into your design as needed. With the IP core properly instantiated into your design, you are ready to synthesize the IP core along with the rest of your design. Vivado: Designing with IP 33

34 Synthesizing IP Synthesizing IP By default, the Vivado IDE synthesizes IP along with the overall design. To avoid re-synthesizing IP every time your logic is modified, you can pre-synthesize the IP. You can generate a Synthesized Design Checkpoint (DCP) either when the IP is first customized and added to the project or later by generating a new output product. To do so after an IP is added to a project, in the Sources view, right-click on the IP and select the Generate Output Products, shown in Figure X-Ref Target - Figure 3-13 Figure 3-13: The Generate Output Product window opens. Creating a Synthesized Design Checkpoint for an IP Check Generate Synthesized Design Checkpoint (.dcp) checkbox, and press Generate as shown in Figure X-Ref Target - Figure 3-14 Figure 3-14: Generate Output Products with Synthesized Design Checkpoint Vivado: Designing with IP 34

35 Synthesizing IP Note: Alternatively you can select the IP XCI in the Hierarchy view, right-click and select Set As Out-Of-Context Module. However, this requires you to name the file set that is created for the synthesis run and to manually launch the synthesis run for the IP. This is the general mechanism for setting levels of hierarchy to be synthesized out-of-context. The recommended flow for pre-synthesizing IP is to use Generate Output Products flow. When you generate the DCP, the Vivado IDE does the following: Creates a new file set and copies in the IP synthesis output targets Sets up new synthesis run and launches the run for the IP Lowers the IP instance in the Hierarchy view (.xci) and adds new level as shown in Figure The symbol indicates that the a DCP is being used and a black box is inferred for synthesis of the whole design. X-Ref Target - Figure 3-15 Figure 3-15: Synthesized Design Checkpoint for IP in Hierarchy Window To change back to using RTL in place of the DCP you can either: Select the IP XCI in the Hierarchy view, right-click and select Reset Output Products Select the DCP in the Hierarchy view, right-click and select Unset Out-Of-Context Module Selecting the Unset Out-of-Context Module preserves the other generated output products where Reset Output Products removes all output products for the IP. Only IP that deliver an Out-Of-Context XDC file are recommended for this flow. The OOC XDC (_ooc.xdc) file provides default clocking information for the IP. Because the IP is done out-of-context, it does not receive any top-level clocking information. Most IP provide these default clocking definitions which synthesis uses for timing optimization. To check whether an IP has OOC XDC file, go to the IP Sources view in the /Synthesis folder and look for a file named <component_name>_ooc.xdc. You can also use the Out-Of-Context flow when using the Manage IP flow when customizing an IP as covered in the Chapter 2, Creating and Managing Reusable IP. Note: You can find a lab exercise that covers this flow in the Vivado Design Suite Tutorial: Designing with IP Tutorial (UG939) [Ref 7]. Vivado: Designing with IP 35

36 Simulating IP Simulating IP Simulating IP with the RTL Design In the Flow Navigator click Run Simulation to simulate the IP cores with the overall design. The Vivado IDE uses the simulation sources delivered by the IP to perform a functional simulation of the entire design. IP deliver one of the following: A behavioral model Plain text synthesizable source Encrypted synthesizable source as VHDL or Verilog simulation models For IP delivering encrypted files as simulation sources, the Vivado IDE manages the compilation of the simulation sources for the selected target simulator (Vivado simulator or ModelSim/QuestaSim). The Vivado IDE also sets up the project for mixed-mode simulation when IP simulation sources are not available in the project target language. See the document UG900 Vivado Design Suite: Logic Simulation [Ref 3] for more details on running simulations within the Vivado Design Suite. See Chapter 2, Creating and Managing Reusable IP for details on creating scripts for running simulation with the Vivado Simulator (xsim) and QuestaSim/ModelSim outside of the Vivado Design Suite using a terminal command line. Simulating with Other Simulators You can do either behavioral or netlist simulation of Xilinx IP delivered with the Vivado IDE using third party simulators. Most of the IP in Vivado IDE deliver HDL files encrypted using the industry standard IEEE P1735 that all major simulators support. Before doing behavioral simulation with a third party simulator, first determine the required simulation files as well as any associated libraries to which they belong. Similarly, before you can do post-synthesis simulation, create a structural simulation model (EDIF, Verilog, VHDL). For details on working with third party simulators and behavioral and netlist simulations, see the section Other Simulators in Chapter 2, Creating and Managing Reusable IP. Vivado: Designing with IP 36

37 Constraining IP in a Design Constraining IP in a Design The Vivado IDE manages user-defined XDC timing and physical constraints for the entire design, including IP. The Vivado IDE handles the association and the unification of constraints for design elements for Xilinx IP instantiated multiple times within a project. Most IP in the IP Catalog also deliver IP-specific XDC constraints based on user customization. During design synthesis and implementation, the Vivado IDE reads in the IP delivered XDC constraints before processing user defined XDC constraints. For a list of possible XDC files that an IP can deliver, see Appendix A, IP Files and Directory Structure. Note: For more detailed information on XDC constraints, including specifics about XDC constraints for IP, see Vivado Design Suite User Guide: Using Constraints (UG903) [Ref 2]. Using an IP Example Design An example design is one of the output products that are generated for IP cores that support the feature. Generating the output products results in RTL that you can explore. The RTL has the IP instanced in an example top-level design. As shown in Figure 3-16, you can open an example design in a new Vivado IDE session by either: Right-clicking the IP under IP Sources or in the Hierarchy view Selecting Open IP Example Design. The Open IP Example Design option is selectable only if the IP contains an example. It is not necessary to generate the output products prior to opening the example design. X-Ref Target - Figure 3-16 Figure 3-16: Open an IP Example Design Vivado: Designing with IP 37

38 Using an IP Example Design When you select this option, a pop-up menu opens that lets you specify the location for the example_design directory (Figure 3-17) where the example design project is saved. Each IP example design is put in its own directory; for example, if the IP is called char_fifo the directory is called char_fifo_example. X-Ref Target - Figure 3-17 Figure 3-17: Open IP Example Design Dialog Box A new session of the Vivado IDE opens that shows the example design in the Design Sources window (Figure 3-18). Notice that the IP is instantiated in the example design with an example XDC constraint file to enable further evaluation of the IP. X-Ref Target - Figure 3-18 Figure 3-18: IP Example Design Instance with Constraint File Vivado: Designing with IP 38

39 Reporting IP Status and Upgrading IP Reporting IP Status and Upgrading IP IP can be upgraded to the latest version by: Using the Upgrade IP option in the right-click menu of the selected IP Using the Report IP Status command You can report the status of all the IP in a project using the Tools > Report > Report IP Status pull-down menu (Figure 3-19, page 39). You can specify a name for the result and optionally output the report to a text file. If a report has not been generated before for the project, then the Open in a new tab option is automatically checked and greyed out. X-Ref Target - Figure 3-19 Figure 3-19: Generating an IP Status Report After you click OK, a new tab titled IP Status is created and the report results displayed. Multiple runs cause additional reports to appear in this tab (Figure 3-20). If the Open in a new tab option is checked (Figure 3-19), a unique name is generated for the Results Name. To overwrite a report, uncheck this box and enter the same name. If the name exists already, is overwritten. X-Ref Target - Figure 3-20 Figure 3-20: Report IP Status View in GUI Vivado: Designing with IP 39

40 Reporting IP Status and Upgrading IP From here you can selectively upgrade IP. By right-clicking an IP you can view the change log (or press the More Info hyperlink) or product guide for an IP. This report can also be generated using the command line with the Tcl command report_ip_status, you can optionally use the -file <file_name> option to create a text file. When you bring in older projects that contain IP, the tool prompts you to open the IP Status Report to review the status of the IP in the design. For IP that supports the Upgrade IP feature, the IP can be upgraded by right-clicking the IP instance in the IP Sources window (or in the Hierarchy view) and selecting Upgrade IP as shown Figure X-Ref Target - Figure 3-21 The upgrade steps can also be performed by using the Tcl command upgrade_ip as shown here: upgrade_ip [get_ips clk_core] Figure 3-21: Upgrading IP If no argument is given, the command upgrades all IP in the project to the latest version, if an upgrade path exists. Vivado: Designing with IP 40

41 Tcl Commands for Common IP Operations Tcl Commands for Common IP Operations Within the Vivado IDE, the Vivado IP Catalog can be accessed from the Vivado IDE and the Tcl design environment. To accommodate batch scripting mode users, every IP Catalog action such as IP creation, re-customization, output product generation, and so forth, which is performed in the GUI issues an equivalent Tcl command; consequently, anything that can be done in the GUI can be scripted. The Vivado IP Catalog provides direct access to IP parameter customization from the integrated Vivado IDE Tcl Console so you can set individual IP parameters directly from the Tcl Console. For example, to create an instance of the accumulator IP: create_ip -name c_accum -version vendor xilinx.com -library ip -module_name c_accum_0 To change customization parameter such as input and output widths: set_property -dict [list CONFIG.Input_Width {10} CONFIG.Output_Width {10}] [get_ips c_accum_0] To generate selective output products: generate_target {synthesis instantiation_template simulation} [get_ips c_accum_0] To reset any output products generated: reset_target all [get_ips c_accum_0] You can use a Tcl script to list the user configuration parameters that are available for an IP you can use either the list_property or report_property command and reference the created IP. The difference between these commands is: list_property returns a list of objects which can be processed with Tcl script easily as a list. report_property returns a text report giving the current value for each parameter, its type, and other parameters. To get a list of all properties which apply to an IP: list_property [get_ips fifo_generator_0] To get an alphabetized list of just the customization parameters you can augment this further: lsearch -all -inline [ list_property [ get_ips fifo_generator_0 ] ] CONFIG.* Vivado: Designing with IP 41

42 Tcl Commands for Common IP Operations To create a report listing all the properties for an IP, including the configuration parameters: report_property [get_ips fifo_generator_0] For more information on the supported IP Tcl commands type, help -category IPFlow in the Tcl Console as shown in Figure X-Ref Target - Figure 3-22 Figure 3-22: Getting Help on IP Tcl Commands Note: The Vivado Design Suite Tutorial: Designing with IP (UG939) [Ref 4] contains labs that cover scripting of both project and non-project flows with IP. They include examples of generating output products as well as selectively upgrading IP. Vivado: Designing with IP 42

43 Chapter 4 Packaging IP IP Packaging Basics and Usage Flow The Vivado IP packager enables Vivado IDE users and third party IP developers prepare an Intellectual Property (IP) design for use in the Vivado IP Catalog. The IP user can then instantiate this third party IP into their design in the Vivado Design Suite. When IP developers use the Vivado Design Suite IP packaging flow, the IP user has a consistent user experience whether using Xilinx IP, third party IP, or customer developed IP. Figure 4-1 shows the flow in the IP packaging and usage model. The IP developer uses the IP packager feature to package IP files and associated data into a ZIP file. The IP user receives this generated ZIP file, and installs the IP into the Vivado Design Suite IP Catalog. The IP user then customizes the IP through parameter selections and generates an instance of the IP. RECOMMENDED: To verify the proper packaging of the IP before a handoff to an IP user, Xilinx recommends that the IP developer run each IP module completely through the IP user flow to validate that the IP is ready for use. X-Ref Target - Figure 4-1 Figure 4-1: IP Packaging and Usage Flow Vivado: Designing with IP 43

44 IP Packaging Basics and Usage Flow IP Packaging Flow Step 1: IP Packaging The output of IP packager is primarily an IP-XACT component file that can include default GUI files incorporated into a ZIP file, along with report and regeneration files. The IP developer can either: Package a design from an already populated Vivado Design Suite project. Create a new Vivado Design Suite project file, and use the Package IP Wizard to import the IP source files and associated data. To invoke IP packager, select Tools > Package IP. Alternatively, you can drive IP packager in batch mode using the Vivado Design Suite Tcl command line interface. Step 2: Secure IP Delivery The IP developer is responsible for securely delivering IP to the IP end-user. IP User Flow Step 1: Updating the IP Catalog After receiving IP from a third-party IP developer or an inter-company IP developer, the IP user starts the Vivado IDE and adds IP to the Vivado IP Catalog. Step 2: Installing the IP License (Optional) Optionally, the user can acquire a FlexNet license from the third party provider and install it. Step 3: Third-Party IP Usage Using the Vivado Design Suite, the IP user can start designing with the third party IP cores. Vivado: Designing with IP 44

45 IP Packaging Basics and Usage Flow Repository Management The Vivado IP Catalog contains built-in repository management features that let you add IP from another party. To make the third party IP visible, you must place the IP must be placed in a location visible from your machine. Then launch the Vivado Design Suite and run the IP Settings functions from the IP Catalog to register the new user repository location and include the new IP in the Catalog. As shown in Figure 4-2, there are two different types of repositories: standard Xilinx repositories and configured user repositories. Standard Xilinx repositories are shipped as part of the Vivado Design Suite, are always enabled, and are unchangeable by the user. User repositories are locations visible from the you machine that contain one or more IP. Xilinx or third party IP providers can deliver IP updates to the Catalog through patches. X-Ref Target - Figure 4-2 Figure 4-2: Repository Types The Repository Manager lets you add or remove user repositories and establish precedence between repositories. IP is distinguished through a unique ordered list of elements corresponding to the Vendor, Library, Name, and Version (VLNV). If multiple repositories are referenced and have the same IP that occur in multiple locations, the Vivado IDE displays the IP that appears in the repository with highest precedence. The Xilinx IP repositories are always enabled and always have lowest precedence. Any changes to the repository setup for a project are stored with the project so the repository changes are visible whenever the project is re-opened on any machine (assuming the repository paths are also available). Note: User repositories can be made available to newly-created projects using options in Tools >Project Settings/IP. Vivado: Designing with IP 45

46 IP Packaging Basics and Usage Flow IP Catalog The Vivado Design Suite IP Catalog is a unified repository lets you search, review detailed information, and view associated documentation for the IP. After you add third party or customer IP to the Vivado Design Suite IP Catalog (Figure 4-3), you can access the IP through the Vivado Design Suite flows. X-Ref Target - Figure 4-3 Figure 4-3: Repositories and the IP Catalog IP Customization and Generation To parameterize and generate output products of the IP, from the IP Catalog open the Vivado Design Suite IP customization GUI. Vivado: Designing with IP 46

47 IP Packager Inputs After specifying valid parameter combinations in the IP GUI, click Generate to produce the IP specified output products in the Vivado Design Suite project directory. Output products can include customization options, netlists, HDL synthesis and simulation files, test benches, example designs, and more. IP Packaging Verification The following are recommended tests to run after successfully packaging the IP using IP packager: Add the IP to the Vivado Design Suite IP repository and ensure that the IP appears correctly in the Vivado Design Suite IP Catalog GUI. Parameterize the IP using the customization dialog in the Vivado Design Suite IP Catalog and generate output products of the IP. Instantiate the IP in a design and run the design through the Vivado Design Suite flows. Generate the example project (if an example was packaged with the IP) and verify that the example functions properly with the Vivado Design Suite. IP Packager Inputs Input File Groups IP packager supports input file groups, which include: HDL synthesis HDL simulation Documentation HDL test bench Example design Implementation files (including constraint and structural netlist files) Minimum File Set Required for Packaged IP IP can designate as many or as few file groups as is appropriate to the IP. There is no hard requirement for a minimum set of file groups; however, the IP packager IP File Groups page presents a typical set of file groups, including logic synthesis, simulation, and documentation. If any of these file groups are empty, the final Review and Package page warns the IP developer that file content has not been provided. Vivado: Designing with IP 47

48 IP Packager Outputs IP Packager Outputs The following subsections describe the organization of the IP design file output package, and other files that are written to the output package. IP Design File Output Package Organization The design files in the output package are organized into sub-folders identical to the organization of the input directory. They are not reorganized physically to match the logical groupings specified in the IP File Groups page. Other Files Written to the Output Package In addition to the IP design files and the IP-XACT XML file, the GUI folder is included in the output package. It contains files that help Xilinx tools display customization and other presentation GUIs for IP. IP Packaging Steps The following are generalized procedures that describe how to use the Package IP wizard to package IP. These procedures use an example IP design called my_complex_mult. The Vivado Design Suite Tutorial: Designing with IP (UG939) [Ref 4] contains explicit instructions along with design data in a lab exercise format. Package an Existing Vivado Project or Create a New Project You can invoke the IP packager on an existing Vivado project or create a new Vivado project for IP you want to package. To create a new project, do the following: 1. In the Vivado IDE, click Create New Project. 2. Name the project my_complex_mult, verify the project location, and click Next (Figure 4-4, page 49). Vivado: Designing with IP 48

49 IP Packaging Steps X-Ref Target - Figure In the Design Source page, verify that RTL Project is selected, then click Next. 4. In the Add Sources page, do the following: a. Add the three RTL subdirectories named cmpy_v3_1, mult_gen_v11_2, and xbip_utils_v2_0. b. Rename the Library field for the three subdirectories as shown in Figure 4-5, page 50. c. Add the top-level VHDL file named my_complex_mult_rtl.vhd. d. Deselect Copy Sources into Project, which is normally used by IP developers to preserve an established directory structure. e. Select VHDL as the target language. f. Click Next. Figure 4-4: New Project Dialog Box, Project Name Page Vivado: Designing with IP 49

50 IP Packaging Steps X-Ref Target - Figure 4-5 Figure 4-5: 5. Click through the remaining wizard panes, and click Finish. Packaging the Project as IP To package a Vivado project as IP, do the following: 1. With the Vivado project open, select Tools > Package IP. 2. In the Welcome to the IP Packager page, click Next. 3. In the Begin IP Creation Page, click Finish. The IP packager gathers Information about the project automatically, and creates a basic IP package in a staging area. 4. In the IP Packager Summary page, click OK. New Project Dialog Box, Add Sources Page 5. Fill in the fields shown in Figure 4-6, page 51 and then click Next. Vivado: Designing with IP 50

51 IP Packaging Steps X-Ref Target - Figure 4-6 Figure 4-6: IP Identification 6. Click Review and Package as shown in Figure 4-7, page 52. Vivado: Designing with IP 51

52 IP Packaging Steps X-Ref Target - Figure 4-7 Figure 4-7: Review and Package Note: The IP packager lists possible missing information that should be included. You can ignore this for now because you add the missing IP documentation as part of the procedure in the Adding Non-HDL Files to the IP Package section. 7. Click the Package IP button to create an IP package ZIP file that you can send to an IP user. 8. In the Package IP dialog box, do the following: a. Verify that the name of the ZIP file is IPwizards_ip_my_complex_mult_3.0.zip, as shown in Figure 4-8. b. Change the Output Directory to: C:\my_complex_mult. c. Click OK. X-Ref Target - Figure 4-8 Figure 4-8: Package IP Vivado: Designing with IP 52

53 IP Packaging Steps 9. Check the C:\my_complex_mult folder to make sure that the new ZIP file was added. Adding New IP to the IP Catalog The following procedure explains how to add packaged IP to the IP Catalog. 1. In the Project Manager area of the Flow Navigator (left side of the main window), click IP Catalog. 2. In the IP Catalog window, right-click and select IP Settings (Figure 4-9). X-Ref Target - Figure 4-9 Figure 4-9: IP Settings Command 3. In the IP Settings dialog box, click Add Directories, select C:/third_party_ip as the IP Repository search path, and click Apply (Figure 4-10). This search path leaf must contain the component.xml file or the packaged ZIP file for the IP. Vivado: Designing with IP 53

54 IP Packaging Steps X-Ref Target - Figure 4-10 Figure 4-10: 4. Select the user repository and click Add IP. IP Repository Search Path 5. Select the my_complex mult ZIP file and click OK. 6. In the IP Catalog window, type My Complex in the Search window to verify that your IP named My Complex Multiplier was added to the IP Catalog. Also verify that the metadata you entered is correctly displayed in the Details window, as shown in Figure 4-11, page 55. Vivado: Designing with IP 54

55 IP Packaging Steps X-Ref Target - Figure 4-11 Figure 4-11: IP Catalog Window Adding Non-HDL Files to the IP Package The following procedure explains how to add non-hdl files to a package already created by IP packager. 1. In the IP Packager tab, select IP Files Groups in the left frame, right-click on the Data Sheet category in the right frame and select Add Files (Data Sheet), as shown in Figure 4-12, page 56. Vivado: Designing with IP 55

56 IP Packaging Steps X-Ref Target - Figure 4-12 Figure 4-12: Add a Data Sheet File to the Package 2. Click the Add Files button in the popup dialog box, navigate to the directory C:/my_complex_mult/doc and select All Files in the Files of type: entry line. You should now see two documentation files in the popup dialog window. 3. Select the file my_complex_mult_data_sheet.pdf and click OK. Click OK again in the Add IP Files (Data Sheet) dialog box. 4. Expand the Data Sheet (1 file) category, as shown in Figure 4-13, page 57, and see that the PDF file is added to the package. Vivado: Designing with IP 56

57 IP Packaging Steps X-Ref Target - Figure 4-13 Figure 4-13: Verify that the Data Sheet was Added 5. Repeat steps 1-4 to add the file named my_complex_mult_release_notes.txt to the Readme category. 6. Click Review and Package, then click the Package IP button to re-package your IP with the new documentation files. Vivado: Designing with IP 57

58 IP Packaging Steps Vivado: Designing with IP 58

59 Appendix A IP Files and Directory Structure Introduction When customizing an IP using the IP Catalog, either directly in a project or using the Managed IP Flow, a unique directory is created for each IP. The unique directory is named by the component that is used when the IP is customized. In this directory there are a number of files and additional directories. There is no common structure for the organization of the HDL that each IP delivers, but there are some common files that each IP delivers. IP Directory Common File Here is a list of the common files found in an IP directory, the files are called <component_name> with the following extensions:.xci file: Contains the IP customization information. You can generate the output products from this file. If an upgrade path exists for the IP in the Catalog, you can upgrade from this file to the latest version..veo or.vho file: Verilog (VEO) or VHDL (VHO) instantiation template. You would use one of these files to instance the IP created inside of you design..xml: Keeps track of the current state of the IP, including generated files, computed parameters and interface information. dcp: The Synthesized Design Checkpoint (DCP) file contains a netlist and constraints for an IP. The Managed IP Flow creates this file as an output product. synplify_stub.v: Port declaration module for IP for use in a 3rd party synthesis tool with Verilog to infer a black box. synplify.vho: Component declaration for IP for use in a 3rd party synthesis tool with VHDL to infer with a blackb box. Vivado: Designing with IP 59

60 IP Directory Common File Other files that can be delivered by an IP include the following: Encrypted HDL for the IP Example designs XDC constraints Core XDC: Timing and physical constraints _clocks.xdc: Constraints with a clock dependency _board.xdc: Constraints used in a board flow _ooc.xdc: Default clock definitions for use in a Managed IP flow or IP netlists. Vivado: Designing with IP 60

61 Appendix B Vivado IP Optimization Introduction This appendix describes the methods used by Xilinx to determine the maximum frequency (Fmax) of IP operation within a system design. The method also enables realistic performance reporting for any Xilinx FPGA architecture. The maximum frequency of a design is the maximum frequency at which the overall system can be run without encountering functional issues. With the current trend toward implementing more complex systems in FPGAs, the Fmax frequency of each included IP is an important factor. Stand-Alone IP Characterization Methodology There are several factors to consider in determining how fast an IP runs. First and foremost is the HDL coding style of the IP. For example, the IP designer can achieve higher performance by pipelining the design to run at higher frequencies. There are also other tradeoffs that can be made at the micro-architecture level to share resources that affect the frequency. Another factor in determining the overall performance is the option settings used in the implementation tools. By choosing appropriate options, the IP designer can achieve the desired design goals. A design can be constrained for area (minimum resource usage) or performance (highest achievable frequency). Different options in the design tools also provide additional control over how a design is synthesized and implemented. For example, the designer might choose to replicate logic, do register re-timing, share resources, and/or provide proper constraints to achieve higher performance. For stand-alone IP characterization, Xilinx uses the default design tool settings. As shown in the following figure, the methodology involves instantiating the stand-alone IP design Design Under Test (DUT) and then wrapping the design in a scan-register wrapper to limit the use of I/Os. Vivado: Designing with IP 61

62 The Fmax Margin System Methodology X-Ref Target - Figure E-1 Figure B-1: Standalone IP Characterization In addition to saving on I/Os, the wrapper logic also ensures that the design maps effectively on a large device. It also ensures that spreading the design within a large device is not an issue and validates that the IP is ready for use. The stand-alone IP characterization methodology helps determine the maximum frequency at which the IP can be run using only the default system constraints. Because this is stand-alone IP, there are no resource constraints competing for placement and routing resources. Additionally, no IO constraints and the presence of the wrapper ensures that IOs are directly driven or sampled by flip-flops (in the wrapper). Note: The stand-alone IP performance numbers are based on a full implementation run of the design through Xilinx tools including synthesis, placement and routing. The Fmax Margin System Methodology While stand-alone IP characterization helps to determine the maximum limit of IP performance, it s important to determine the IP performance in the context of a user system. In the case of embedded systems, the system typically includes the following items: MicroBlaze Processor or Processor System 7 (PS7) Caches (IC and DC) One or more levels of Interconnect Memory controller (MIG) Direct Memory Access (DMA) Controller On-chip BRAM controller Peripherals (such as UART, Timer, GPIO, Interrupt Controller) The IP under test (such as DUT) Vivado: Designing with IP 62

63 The Fmax Margin System Methodology Determining the Fmax of an Embedded IP with these components provides a more realistic performance target. In addition, the user system can fill up the device with up to 70-80% logic. The Fmax Margin system methodology stitches the IP in a basic embedded system and fills the rest of the device with available LUTs, BRAMs and I/Os to ensure that 70-80% of the device is full. X-Ref Target - Figure E-1 Figure B-2: Fmax Margin System for 7 Series The embedded system shown in the figure above has the following two types of AXI Interconnect: AXI4-Lite which is typically used for peripheral command and control. In general, this interconnect runs at a much lower frequency and is designed for minimum area. AXI4 is typically used for heavy-duty data-motion-type applications. In general, this interconnect runs at optimum speed and is designed for maximum performance. For Fmax Margin System Analysis, the AXI4-Lite Interconnect clock frequency is fixed to 150 MHz. The AXI4 Interconnect and the rest of the logic is incremented from 150 MHz up to the maximum frequency where the system breaks with timing violations (Worst Case Negative slack). The maximum frequency at which AXI4 runs determines the Fmax of the overall system. Vivado: Designing with IP 63

64 Tool Options and Other Factors The following block diagram is the Fmax Margin System for the Zynq-7000 AP SoC processor. X-Ref Target - Figure E-1 Figure B-3 Fmax Margin System for Zynq Tool Options and Other Factors Xilinx tools offer a number of options and settings that provide a trade-off between design performance, resource usage, implementation run time, and memory foot print. The settings that produce the best results for one design may not necessarily work for another design. For the purpose of the Fmax Margin System Analysis, the IP design is characterized with default settings without specific constraints (other than the clocking constraint). The clocking constraint is increased in steps starting from 150 MHz until the system fails with timing violations (Worst Case Negative slack). This analysis is done with different FPGA architectures and speed grades. The results are reported in the individual IP Product Guide for the IP core. Vivado: Designing with IP 64

65 Appendix C Vivado Design Suite IP vs ISE CORE Generator IP Introduction IP delivered with the Vivado Design Suite have the following characteristics over IP delivered in the ISE Design Suite CORE Generator tool: Are accessible in a single unified IP Catalog Are delivered as HDL and are usable for both simulation and synthesis/implementation Use the new Xilinx Design Constraints (XDC file) for physical and timing constraints which are applied automatically A synthesis design checkpoint (.dcp file) replaces the.ngc file as the container for both the IP netlist and scoped constraints Each IP (.xci file) needs to be in its own directory (see the documentation on the Managed IP Flow and In Project Flow) No longer uses the XilinxCoreLib for simulation (unless using older IP) as each IP delivers its own simulation sources as an output product Using Fee-Based Licensed IP The Vivado IP Catalog displays either Included or Purchase under the License column in the IP Catalog. The following definitions apply to IP offered by Xilinx: Included: The Xilinx End User License Agreement applies to Xilinx LogiCORE IP cores that are licensed within the Xilinx Vivado Design Suite software tools at no additional charge. Purchase: The Core License Agreement applies to fee-based Xilinx LogiCORE IP cores, and the Core Evaluation License Agreement applies to the evaluation of fee-based Xilinx LogiCORE IP cores. Vivado: Designing with IP 65

66 Using Fee-Based Licensed IP For more information on how to obtain IP licenses, visit the Xilinx Licensing site at For fee-based IP, the OK button on the Customize IP dialog box is disabled until an evaluation or a paid license is found as shown in the figures below. X-Ref Target - Figure E-1 Figure C-1: Fee-Based IP OK Button Disabled while Checking for License X-Ref Target - Figure E-1 Figure C-2: Fee-Based IP OK Button Enabled after License Found Vivado: Designing with IP 66