KC705 PCIe Design Creation with Vivado August 2012

Transcription

1 KC705 PCIe Design Creation with Vivado August 2012 XTP197

2 Revision History Date Version Description 08/20/ Initial version. Added AR Copyright 2012 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. NOTICE OF DISCLAIMER: The information disclosed to you hereunder (the Information ) is provided AS-IS with no warranty of any kind, express or implied. Xilinx does not assume any liability arising from your use of the Information. You are responsible for obtaining any rights you may require for your use of this Information. Xilinx reserves the right to make changes, at any time, to the Information without notice and at its sole discretion. Xilinx assumes no obligation to correct any errors contained in the Information or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE INFORMATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

3 Note: This presentation applies to the KC705 Overview Kintex-7 PCIe x8 Gen 2 Capability Xilinx KC705 Board Software Requirements KC705 Setup Compile PCIe Cores Generate x8 Gen 2 PCIe Core and MCS File Program KC705 Flash with PCIe Design Running the PCIe x8 Gen 2 Design References IP Release Notes Guide XTP025

4 Kintex-7 PCIe x8 Gen 2 Capability KC705 Supports PCIe Gen 1 and Gen 2 Capability x8, x4, x2, or x1 Gen 1 and Gen 2 lane width x8 Gen 2 not supported in -1 parts See DS821 for details LogiCORE PIO Example Design RDF0187.zip Available through LogiCORE Integrated Block for PCI Express See UG477 for details

5 Kintex-7 PCIe x8 Gen 2 Capability Integrated Block for PCI Express PCI Express Base 2.0 Specification Configurable for Endpoint or Root Port Applications KC705 configured for Endpoint Applications GTX Transceivers implement a fully compliant PHY Large range of maximum payload size 128 / 256 / 512 / 1024 bytes Configurable BAR spaces Up to 6 x 32 bit, 3 x 64 bit, or a combination Memory or IO BAR and ID filtering Management and Statistics Interface

6 Xilinx KC705 Board Note: Presentation applies to the KC705

7 ISE Software Requirements Xilinx Vivado software Apply AR50886

8 PciTree Software Requirement PciTree Bus Viewer Free download HLP.SYS must be copied to C:\WINDOWS\system32\drivers directory

9 Generate x8 Gen 2 PCIe Core Open Vivado Start All Programs Xilinx Design Tools Vivado Vivado Select Create New Project

10 Generate x8 Gen 2 PCIe Core Click Next

11 Generate x8 Gen 2 PCIe Core Set the Project name and location to kc705_pcie_vivado and C:\ Check Create Project Subdirectory

12 Generate x8 Gen 2 PCIe Core Select RTL Project Select Do not specify sources at this time

13 Generate x8 Gen 2 PCIe Core Select the KC705 Board

14 Generate x8 Gen 2 PCIe Core Click Finish

15 Generate x8 Gen 2 PCIe Core Click on IP Catalog

16 Generate x8 Gen 2 PCIe Core Select 7 Series PCIe Version 1.6 under Standard Bus Interfaces

17 Generate x8 Gen 2 PCIe Core Right click on 7 Series PCIe Version 1.6 Select Customize IP

18 Note: Pre-built design, RDF0187, available through Generate x8 Gen 2 PCIe Core Under the Page 1 tab, set the Component name to kc705_pcie_x8_ gen2 Set the lane Width to X8 Set the Link Speed to 5 GT/s Set the Frequency to 250 MHz Click on Page 2

19 Generate x8 Gen 2 PCIe Core Under the Page 2 tab, BAR 0 Set to 1 Megabytes Click on Page 3

20 Generate x8 Gen 2 PCIe Core Under the Page 3 tab, note ID Initial Values Vendor ID = 10EE Device ID = 7028 Revision ID = 00 Subsystem Vendor ID = 10EE Subsystem ID = 0007 Click on Page 11

21 Generate x8 Gen 2 PCIe Core Under the Page 11 tab Select KC705 REVC Click on Page 13

22 Generate x8 Gen 2 PCIe Core On Page 13 Set the Reference Clock Freq: 100 MHz Set the Silicon Revision to General ES Click OK

23 Generate x8 Gen 2 PCIe Core PCIe design appears in Design Sources The PCIe IP is already checked but still needs to be generated

24 Compile Example Design Right-click on kc705_pcie_x8_gen2 and select Generate

25 Compile Example Design Select Synthesis, Examples, and Instantiation Template as the targets to generate

26 Compile Example Design Once the Generate step is complete, a check (re)appears on the IP

27 Modify PCIe Core As per AR44635, the design must be modified Open the file: <design path>/<design name>.srcs\sources_1\ip\ kc705_pcie_x8_gen2\kc705_pcie_x8_gen2\example_design\ xilinx_pcie_2_1_ep_7x.v Add this line: input emcclk,

28 Modify PCIe Core As per AR44635, the design must be modified Open the UCF file (name may vary): <design path>/<design name>.srcs\sources_1\ip\kc705_pcie_x8_gen2\kc705_pcie_x8_gen2\ example_design\ xilinx_pcie_2_1_ep_7x_8_lane_gen2_xc7k325t-ffg900-2_kc705_revc.xdc Add these lines: set_property IOSTANDARD LVCMOS25 [get_ports emcclk] set_property LOC R24 [get_ports emcclk]

29 Modify PCIe Core As per UG470, UG628, and P30 Flash specifications In the XDC file, xilinx_pcie_2_1_ep_7x_8_lane_gen2_xc7k325t-ffg900-2_kc705_revc.xdc, add these lines: set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2 [current_design] set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-2 [current_design] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

30 Modify PCIe Core Details on the bitgen command: P30T Maximum Frequency: 52 MHz; KC705 EMCCLK Frequency: 66 MHz BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-2: Sets the EMCCLK in the FPGA to divide by 2, which meets the P30T Maximum Frequency specification BITSTREAM.CONFIG.BPI_SYNC_MODE Type2: For Numonyx P30 Family BITSTREAM.GENERAL.COMPRESS TRUE: Further shrinks the bitstream size

31 Compile Example Design Click Add Sources:

32 Compile Example Design Select Add or Create Design Sources

33 Compile Example Design Add kc705_pcie_x8_gen2_pipe_clock.v

34 Compile Example Design Click Add Directories

35 Compile Example Design Add the example_design directory from the PCIe source files

36 Compile Example Design Click Finish

37 Compile Example Design Click Add Sources again

38 Compile Example Design Select Add or Create Constraints

39 Compile Example Design Add xilinx_pcie_2_1_ep_7x_8_lane_gen2_xc7k325t-ffg900-2_kc705_revc.xdc

40 Compile Example Design Click Finish

41 Compile Example Design Click on Generate Bitstream

42 Compile Example Design The completed design appears in GUI

43 Hardware Setup Set S13 to (1 = on, Position 1 Position 5) This enables Master BPI configuration from Slot #1 Flash A25, A24 = 00 FPGA mode pins M[2:0] = 010

44 KC705 Setup Connect a USB Type-A to Micro-B cable to the USB JTAG (Digilent) connector on the KC705 board Connect this cable to your PC Power on the KC705 board

45 Generate x8 Gen 2 PCIe MCS File

46 Generate PCIe MCS File Click on Launch impact

47 Generate PCIe MCS File Under impact Flows, double click on Create a PROM File

48 Generate PCIe MCS File To generate a PROM file for the BPI Flash, select: BPI Configure Single FPGA

49 Generate PCIe MCS File Select Virtex7 Add 128M Storage Device

50 Generate PCIe MCS File Click on Output File Location, create a ready_for_download directory, set the file name, set Data Width to 16, and click OK

51 Generate PCIe MCS File Add xilinx_pcie_2_1_ep_7x.bit from the <design path>\kc705_pcie_vivado.runs\impl_1 directory

52 Generate PCIe MCS File Click OK on this dialog

53 Generate PCIe MCS File From the impact menu, select Operations Generate File

54 Program BPI Flash with PCIe Design After generation completes, click on the Boundary Scan tab

55 Program BPI Flash with PCIe Design Right click on the SPI/BPI? and select Add SPI/BPI Flash Add <design path>\ready_for_download\kc705_pcie_x8_gen2.mcs

56 Program BPI Flash with PCIe Design Make the following settings Select 28F00AP30 Set the RS Pins to 25:24

57 Note: Programming takes about 2 minutes Program BPI Flash with PCIe Design Right click on the Flash and select Program Use default settings to Erase and Verify device

58 Program BPI Flash with PCIe Design Erase Before Programming must be selected

59 Hardware Setup Insert the KC705 Board into a PCIe slot (x16 shown) Use the included PC Power adapter; turn on Power Switch

60 Hardware Setup Do not use the PCIe connector from the PC power supply

61 Running the PCIe x8 Gen 2 Design Power on the PC Start PciTree

62 Running the PCIe x8 Gen 2 Design Set Number of Configuration Registers to 64 Click on Refresh dump

63 Running the PCIe x8 Gen 2 Design Locate the Xilinx Device Vendor ID is 0x10EE The x8 Gen 2 configuration will have a Device ID of 0x7028

64 Running the PCIe x8 Gen 2 Design Navigate the linked list in configuration space to locate the PCIe Capabilities Structure See UG477 for details With the Xilinx device selected, select Register 0x40 Register 0x40 points to the next structure 0x48 is the address of the next structure

65 Running the PCIe x8 Gen 2 Design Select Register 0x48 Register 0x48 points to the next structure 0x60 is the address of the next structure

66 Running the PCIe x8 Gen 2 Design Register 0x60 0x60 is a type 0x10, indicating PCIe Capabilities Structure Last Structure

67 Running the PCIe x8 Gen 2 Design 1 Register 0x6C Link Capabilities Register Indicates the maximum number of lanes and speed (Gen 1, Gen 2) for device The value 0x82 shows this is an x8 Gen 2 device (1) Link Status Register 0x70 Shows the current link status This design, in a Gen 2 chassis, trained to x8 Gen 2 (2) 2

68 Running the PCIe x8 Gen 2 Design Double-click on BAR 0 BAR 0 Address is machine dependent Click Yes on the Dialog box seen below

69 Running the PCIe x8 Gen 2 Design Select auto read memory

70 Running the PCIe x8 Gen 2 Design Click on the first memory location Type <Shift-End> to select 1024 Bytes

71 Running the PCIe x8 Gen 2 Design Write Memory Select count Click Write Memory Click refr view View results counting up to FF

72 Running the PCIe x8 Gen 2 Design Restore Memory Deselect count Click Write Memory Click refr view Memory is reset to zeros Turn off PCIe chassis and remove KC705 board

73 References

74 References PCIe Base Specification PCI SIG Web Site Kintex-7 PCIe PCIe Product Overview 7_SERIES_PCI_Express_Block.htm 7 Series FPGAs Integrated Block for PCI Express User Guide UG477 pcie_7x/v1_4/ug477_7series_intblock_pcie.pdf 7 Series FPGAs Integrated Block for PCI Express Data Sheet DS821 pcie_7x/v1_4/ds821_7series_pcie.pdf IP Release Notes Guide

75 Documentation

76 Documentation Kintex-7 Kintex-7 FPGA Family KC705 Documentation Kintex-7 FPGA KC705 Evaluation Kit KC705 Getting Started Guide ug883_k7_kc705_eval_kit.pdf KC705 User Guide ug810_kc705_eval_bd.pdf KC705 Reference Design User Guide ug845_ref_design.pdf