Fast Communications Controller

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1 Fast Communications Controller Purpose: The Fast Communications Controller HDLC Protocol module describes the use of the FCC when used in HDLC mode. Objectives: This will provide you with an understanding of the transmit/receive flow of HDLC protocol thru the FCCs and provide you with a detailed explanation of the various FCC registers. Contents: The HDLC basics followed by the data flow thru the FCC with links to supplemental Register explanations. Learning Time: There are 12 pages and 20 reference pages that will take approximately 28 minutes. The purpose of this module and the FCC sections that follow are to highlight individual protocol management. This one covers the HDLC Protocol describes the use of the FCC when used in HDLC mode. The objective of this module is to provide you with an understanding of the transmit/receive flow of HDLC protocol thru the FCCs and provide you with a detailed explanation of the various FCC registers. The contents of this module include the HDLC basics followed by the data flow thru the FCC with links to supplemental Register explanations. There are 12 pages and 20 reference pages that will take approximately 28 minutes.

2 FCC HDLC Controller The FCC is in HDLC mode when the GFMR[28:31] is set to 0b0000. This setting provides the Layer 2 functions of the OSI model. In this mode, the variables are available to handle HDLC protocol and provide the required control features. This section describes the variables. Reference Manual Chapter 31 HDLC mode of operation is selected with the GFMR mode bits set to zero. This makes it the default mode. The controller provides the layer two functions of the OSI model. When this mode is selected the variables are available to handle the protocol, along with the necessary control features

3 FCC HDLC Features Flexible data buffers with multiple buffers per frame Separate interrupts for frames and buffers Received frames threshold to reduce interrupt overhead Four address comparison registers with mask Maintenance of four 16-bit error counters Flag/abort/idle generation/detection Zero insertion/deletion 16/32-bit CRC-CCITT generation/detection Detection of non-octet aligned frames and frame too long Programmable number of flags between successive frames These are the basic features of the controller in HDLC mode. Flexible data buffers with the ability to have multiple buffers per frame. Separate Interrupts available for frames as well as buffers. Each time a buffer is closed an event is generated which can create an interrupt to the core. There is a similar event generated when a frame is completed. Received frames threshold to reduce interrupt overhead. If a large number of frames are expected that could result in an unacceptable interrupt overhead the interrupt can be generated based on multiple frames instead of each one. Four address comparison registers with a mask. At least four separate addresses can be recognized and accepted for received frames. The mask enables user defined bits of the address to be ignored resulting in each address register to become an block address. Maintenance of 16-bit error counters. These simply count the defined errors giving the user statistics for errors. Flag, abort and idle, generation and detection. Transmitted frames have the start and end flags automatically added to the frame before transmission, and the abort and idle line states generated as necessary. The receiver automatically recognizes and strips off the flags, and recognizes abort and idle states on the line. Zero insertion and deletion. Because it is necessary to have a predefined flag at the start and end of a frame to enable the controller to recognize it, it s not possible to have data within the frame that mimics a flag. However, it is not desirable to have a situation where any desired character cannot be used for data. This is handled by a process commonly called bit stuffing. An HDLC flag is six ones with a leading and trailing zero, value hex seven E. To ensure that value within the data cannot be confused with a flag, if the transmitter sees a zero followed by five ones in the data stream it automatically adds a zero into the stream. At the receiver, if a zero that is followed by five ones is received, the controller deletes the following bit stripping the zero insertion. 16- or 32-bit CRC generation and detection, giving the user the ability to select which size is appropriate for the application. As data is transmitted, a CRC calculation is performed on the data and when the end of the frame is reached, the CRC value is attached to the end of the frame. Similarly, as data is received the same calculation is performed and when the end of the frame is recognized, the value at the end of the frame is compared to that calculated by the receiver. If they do not match, a CRC error indication is generated. Detection of non-octet aligned frames and frames that are too long. As the serial stream of bits is received they are accumulated into bytes. If for some reason there is a number of bits that are not divisible by eight then an event is generated to alert the user. There is also a parameter to define the maximum length allowed for a frame and if a frame is received longer than that value an event is generated. Programmable number of flags between successive frames. If a continuous stream of frames is transmitted, is it desirable to have them directly adjacent to each other? In other words, the end flag immediately next to the start flag of the next frame. If it is desirable to introduce a delay between frames, perhaps due to timing constraints, then the user can select to automatically introduce up to 15 flags between successive frames

4 HDLC Frame Flag Address Control Information CRC Flag 8 bits 16 bits 8 bits N bits 16/32 bits 8 bits Handled automatically by both receiver and transmitter Handled automatically by Receiver only Flag = ' '... Frame Boundary Zero Insertion and Deletion. A binary zero is inserted by the transmitter after any succession of five 'ones' within a frame (between Flags). This eliminates the possibility of confusing data with Flags. The receiver deletes all zeros that are separated by five ones to reproduce the original data. Abort. The transmitter aborts a frame by sending between 7 and 14 consecutive ones. Idle. Out of frame period indicated by continuous (more than 14) ones. This is the format of an HDLC frame. The start of a frame is indicated by the start flag which is a fixed 8-bit value of a The next 16-bits following the start flag is the destination address that the frame is intended for. Following that is an 8-bit control value used by the user for higher level control functions. Next is the data, which theoretically can be any number of bits. At the end of the frame comes the CRC value, which is appended to the frame by the transmitter and based on a calculation on the data. This can be either 16- or 32- bit depending on the requirements of the application. To delineate the end of the frame a flag is appended to the end of the frame and has the same value as the start flag. The transmitter automatically attaches the start and end flag as well as the CRC value. All the rest of the information to be transmitted must be provided by the application and so must be in the transmit buffer before transmission starts. The receiver automatically recognizes the start and end flag and removes them from the data stream. The 16-bits following the start flag are automatically compared to the address registers and if there is a match, then the frame is received. If not, then it is ignored. The address mask enables less than 16-bits of the address to be utilized. The CRC value at the end of the frame is compared to the receiver calculation and if they do not match then an error is reported. However, the attached CRC value continues with the data and is transferred to a buffer.

5 Receiver Flow-part 1 Line Idle - Wait for Flag Line Not Idle - Check for Flag Flag Received - Discard Flag first 16-bits Match HADDRn/ HMASK No Increment NMARC if Frame Is Error Free Wait for Idle line Receive Data Here s the first part of the flow chart for how the receiver handles incoming data. Here it can be seen that the address is compared to the HADDR registers where the lower case n refers to the fact that there are four of them and the register H mask is also used to define how many of the address bits to match. In the case of a mismatch, an error counter for non matching address is incremented and the controller goes back to waiting for an idle line.

6 Flow cont d Receive Data BD ready? No Set SCCE/BSY Error Data Lost Route Data to Buffer Buffer Full? No End of Frame? No BD/I Set? No Set SCCE/RxF Set SCCE/RxB Check CRC Increment BD Pointer Next Frame When data is being received the controller checks to see if a buffer is ready by checking the appropriate bit in the buffer descriptor. If there is not a buffer ready, then the data is lost and the event is registered in the event register. If a buffer is ready, then the data is transferred to the buffer using DMA. Once data is transferred and the buffer is not full, the controller checks for an end of frame and if so, sets the event and checks the CRC for data errors. If the buffer becomes full, then it checks to see if an event is needed to be generated in the event register, defined by a bit in the BD, then increments the buffer descriptor pointer and repeats the process.

7 Memory Structure External memory Rx Buffer Descriptions Descriptors Internal RAM Parameter RAM Rx Buffer Descriptors Tx Rx Buffer Descriptions Descriptors Common Parameters SCC SCC SCC HDLC Parameters Tx Buffer Descriptors Rx Buffer Data Descriptions Buffer Rx SCC SCC SCC Tx Data Buffer Tx To control the process the CP needs parameters for run time variables, buffer descriptors to control the buffers and buffers for handling data. The parameters are in dual port ram at pre defined, fixed locations. They are organized as two separate blocks, with the top portion being the common parameters, which are basically the same regardless of the protocol in use, followed by the HDLC protocol specific parameters. These are in the same location as those for other protocols but have different purposes depending on the protocol in use. The common parameters are described in the FCC basic section leading into this module. Buffer descriptors must be located in external memory. To examine the HDLC parameters and buffer descriptors click on the block of interest.

8 Registers (One for each FCC) 0 FPSMR 31 FCC Protocol-Specific Mode Register - Configures the FCC for the specific protocol chosen 0 FCC Event Register - Reports events specific to the protocol in use 0 FCC Mask Register - Enables events to be reported to the interrupt controller 0 7 FCCS FCCE FCC Status Register - Monitors real-time status conditions on the received data line 0 FCCM GFMR General FCC Mode Register - Defines all options common to the FCC 0 15 FDSR FCC Data Synchronization Register Register - Defines the sync pattern for synchronous protocols 0 15 FTODR FCC Transmit-on-Demand Register - Requests CP processing without normal polling of the buffer descriptor These are the registers required to set up the FCC and select the features required. FPSMR is the protocol specific mode register which is used to select the HDLC specific features on how frames are handled. FCCE is the event register where all events are recorded if enabled. Any bits set in this register can result in an interrupt to the core if not masked. This is protocol specific, although, many events are similar to those for other protocols. FCCM is the partner to the event register that enables events to generate interrupts. Bits set in the mask register enable bits set in the event register in the equivalent location to generate a request to the interrupt controller. FCCS is a real time status register that monitors the line. GFMR is a common register for all protocols and is used to select the protocol to be used. FDSR is used to select the sync pattern to be used. It s default value is the HDLC sync pattern. FTODR enables the user to transmit on demand, in which case the controller is redirected from its normal schedule. This must be used with care since it will affect other functions. To view any of these registers in detail click on the one of interest.

9 Example of Receiver Buffer/Buffer Descriptor Activity Receiver input: I F A A C D D D D D D D D D D D D D å å F I F A A C AB/I MRBLR = 8 Buffer Descriptors E L F AB BD $0008 Pointer BD $0008 Pointer BD $0012 Pointer BD $0003 Pointer BD $0000 Pointer Buffers A A C D D D D D D D D D D D D D å å x x x x x x A A C x x x x x x x x x x x x x Legend I = Idle F = Flag A = Address C = Control D = Data å = CRC AB = Abort This shows a very simple example of how data is transferred from the receiver to buffers, and the buffer descriptor activity in the process. At the top of the screen is an indication of the bytes received from the receiver in order from the left and the line state in between. The maximum receive buffer length is eight bytes. The assumption is that all the buffer descriptors initially indicate that the buffer associated with it is empty and ready to receive data. For this example, only the bits in the buffer descriptor directly associated with the data transfer are shown, those being the empty, last, first and abort bit. Initially, the line is idle and then a flag is received followed by a 16-bit address and a control byte. The frame consists of 13 bytes of data, followed by a 16-bit CRC value and then the last flag and then the line goes idle. The first frame is described before moving on to the next. The address is compared to the address registers and in this example, it is assumed that there is a match and the frame is received. The controller uses the first buffer descriptor, finds the buffer ready, or empty and starts transferring the data to the location starting at the address defined by the pointer in the buffer descriptor. Since MRBLR is eight and eight bytes have transferred to the buffer, it will automatically be closed by clearing the empty bit in the BD. As this is the first buffer of the frame, the first bit, F, is set and the byte count indicated as eight. As you can see, the address and control byte have been transferred to the buffer followed by five bytes of data. The controller switches to the next buffer descriptor, which was indicating the buffer empty and continues to transfer data starting at the location indicated by the pointer. Again, when the MRBLR value is reached, the buffer closes. At that time the buffer contains neither the start or end of the frame so neither F or L are set and the byte count shown is eight. Once more the controller switches to the next BD, which indicated empty, and further data is transferred to the associated buffer. In this case, the end flag is reached and so the buffer is closed, not because it reached MRBLR but because it is the end of the frame. This time the L bit is set to indicate that this buffer contains the end of the frame. Only two bytes have been transferred to the buffer but the byte count is shown as hex twelve which is decimal eighteen. That is the total byte count for the frame. At this point the line is idle and so the controller waits for a flag. Once a flag is received, the above procedure repeats, but in this case there is a situation where the line goes idle before an end flag arrives. In other words, the frame has been aborted. The controller accesses the next buffer descriptor and starts transferring data to the buffer but then gets an indication from the receiver that the message was aborted and so the abort bit is set, the F bit is also set and the byte count is shown as three. The controller now switches to the next BD, ready for any future data to arrive and in this case, the E bit is shown as set to indicate that the buffer is empty and ready to receive data. There are a few issues worth consideration here. The last situation is effectively an error in that a frame has aborted and so is incomplete. The controller does nothing about this although the problem is recorded by the abort bit in the buffer descriptor. Software must handle the situation however required by the application. It could be that a message must be sent back to the transmitter indicating the problem and request a resend. The other consideration is that the address, control byte and CRC value are in the buffer, which may not be what you expected. Again, this must be handled by software, if needed. It might be that this message is to be transferred on to some other serial controller, in which case it may be necessary to have these values present in the buffer. If the control byte is used to perform specific functions, then it s up to software to find it and deal with it as required, which is where the F bit in the buffer descriptor is useful indicating the first buffer of the frame. The L bit is useful to find the CRC value as well as knowing that that buffer is the last to be serviced for the frame.

10 RTS, CTS and CD RTS and CTS are handshake signals for the FCCs. FCC CTS RTS Examples CD and CTS should be used synchronously when CTS must also serve as data framing (defining byte boundaries) [ GFMR/CTSS = 1 or GFMR/CDS = 1 ] e.g. transparent mode - used to define byte boundary. CD should be used asynchronously when it indicates where to start searching for the beginning of a frame. [ GFMR/CDS = 0 ] CTS should be used asynchronously when it does not matter to the external hardware which specific clock the transmitter starts to drive data because some other method is used to determine the data framing. [ GFMR/CTSS = 0 ] RTS and CTS are active low handshake signals for the controller indicating that the transmitter is ready to send data to the receiver, and the receiver is clear to have data sent to it. CD is the carrier detect signal indicating that valid data is on the line. There are some options on how these signals can be used controlled by the GFMR register. These allow the user to select whether the CTS and CD signals are to be used synchronously or asynchronously. This slide simply identifies some of the applications of these options. For some examples of the relative signal timing, click on the example button.

11 Connections and Routing To connect the FCC to the outside world the connections must be made as indicated in this table. The ports must be configured as defined by the port configuration controls. If multiplexed outputs are required, then the signal routing must be defined in the CMX registers. Signals RxD(0) RxD(1) RxD(2) RxD(3) TxD(0) TxD(1) TxD(2) TxD(3) RTS CD CTS Pin Connections FCC1 FCC2 FCC3 PA17 PA16 PA15 PA14 PA18 PA19 PA20 PA21 PA30 PC6 PC7 PB21 PB20 PB19 PB18 PB22 PB23 PB24 PB25 PB28 PC4 PC5 PB8 PB9 PB10 PB11 PB7 PB6 PB5 PB4 PD4 PC2 PC3 Ref. Pin configuration tool - Pin_Mux An extremely important consideration for the controller is that the external pin connections must be selected. Following reset of the PowerQUICC II, none of the external connections are connected to the controller. The controller must be connected via one of the parallel ports and so the appropriate pin functions must be initialized as required. It s important to be aware that only the pin functions necessary need be programmed, any not needed can still be used for the alternative function provided by the parallel port. This chart indicates the signal associated with the controller and the parallel port pins used for each of the FCCs. There is a software pin configuration tool to help with this process called the Pin Mux tool which can be found on the PowerQUICC II web site.

12 Initialization Procedure Load the Common Registers Generally default values required. GFMR can be initialized last. Load HDLC Registers: FPSMR FCCM zero FCCE Load HDLC Parameters: C_MASK C_PRES MFLR RFTHR HMASK HADDR1-4 zero DISFC CRCEC ABTSC NMARC INIT via CPCR Load Common Parameters as described in the FCC common section Load Rx Buffer Descriptors Load Tx Buffer Descriptors Clear Buffers Enable Rx and Tx in GFMR (ENR/ENT = 1) This chart indicates the requirements for initializing the controller for HDLC mode. Links are available to each part to see all the details required.

FCC in HDLC Mode. What you will learn 2-1

FCC in HDLC Mode. What you will learn 2-1 FCC in HDLC Mode What you will learn What is an FCC? What are the FCC pins? How an FCC operates What is FCC parameter RAM What is FCC protocol specific parameter RAM How to select and configure the clocks