FCC in HDLC Mode. What you will learn 2-1

Transcription

1 FCC in HDLC Mode What you will learn What is an FCC? What are the FCC pins? How an FCC operates What is FCC parameter RAM What is FCC protocol specific parameter RAM How to select and configure the clocks How an FCC transmits and receives in HDLC How to initialize an FCC for HDLC 2-1

2 What is HDLC? Definition HDLC is a synchronous protocol that transfers data in frames. Often used to transmit and receive data. Example Flag Addr Cntrl Data CRC Flag Stored in transmit buffer Stored in receive buffer Flag: The opening and closing octet of a frame. Equal to 0x7E Addr: The destination address of the frame. 8 or 16 bits. Cntrl: The control field. Not used by the HDLC controller. 8 or 16 bits. CRC: Error calculation. 16 or 32 bits. FCC-HDLC Features Buffer descriptors in external memory Transfers data up to T3 rate Time stamp mode for receive frames Nibble mode selectable SCC & FCC Features Flag/abort/idle generation/detection Zero insertion/deletion 16 or 32 bit CRC generation and checking Multiple buffers per frame possible Separate interrupts for receive frame and receive buffer Receive frames interrupt threshold Four address comparison registers with mask Maintains four 16-bit error counters: - Number of frames discarded due to lack of buffers - Number of frames with CRC error - Number of frames aborted - Number of frames with non-matching address Programmable number of flags between frames,

3 What is an FCC? Definition An FCC is a high-speed communication device capable transferring data in HDLC, Ethernet or ATM. Example FCCx Rx FIFO SDMA BTM DPR AM3 Tx FIFO Request Prioritizer SDMA CPM RISC External Memory Description Receive Operation 1. Buffer descriptors and buffers reside in external memory, either on 60x bus or local bus. 2. The BTM (Block Transfer Module) moves data between dual-port RAM and FIFO. The BTM removes the burden from the CP of transferring datato/from the FIFOs 3. The FIFOs are 192 bytes deep. 1. Data is received in the Rx FIFO. 2. FCCx requests service from CPM RISC. 3. CPM RISC checks the address. If the address is for this FCC, the CPM RISC directs the BTM to transfer the FIFO data to dual-port RAM. 4. The SDMA transfers data from the dual port RAM to current buffer in memory. Transmit Operation 1. Space is available in the transmit FIFO. 2. FCCx requests service from CPM RISC. 3. CPM RISC directs the BTM to transfer data from dual-port RAM to the transmit FIFO. 4. The SDMA transfers data from the current buffer in memory to dual-port RAM. 2-3

4 What are the FCC pins? Introduction The following diagram summarizes the FCC pins for HDLC and transparent. FCC Pin Summary FCCx:TXD - transmit pins FCCx:RXD - receive pins FCCx:CD - carrier detect pins FCCx:CTS - clear-to-send pins FCCx:RTS - request-to-send pins FCC1 Pin Example PA[17]/FCC1:RxD[0]:RxD[7]:RxD[15] PA[16]/FCC1:RxD[1]:RxD[6]:RxD[14] PA[15]/FCC1:RxD[2]:RxD[5]:RxD[13] PA[14]/FCC1:RxD[3]:RxD[4]:RxD[12] PA[18]/FCC1:TxD[0]:TxD[7]:TxD[15] PA[19]/FCC1:TxD[1]:TxD[6]:TxD[14] PA[20]/FCC1:TxD[2]:TxD[5]:TxD[13] PA[21]/FCC1:TxD[3]:TxD[4]:TxD[12] PA[30]/FCC1:RTS:TxClav:CRS PC[6]/FCC1:CD:RxAddr[2]:RxClav[1]/FCC2:RxAddr[2]/ TDM_C1:L1CLKO PC[7]/FCC1:CTS:TxAddr[2]:TxClav[1]/FCC2:TxAddr[2]/ TDM_C1:L1RQ Description 1. Each FCC has five pin types available in HDLC: transmit, receive, carrier detect, clear-to-send, and request-to-send. 2. If the FCC-HDLC controller is programmed for nibble mode, then 4 transmit and 4 receive pins are available. If nibble mode is not selected, then only RxD[0] and TxD[0] are available. 2-4

5 Programming Model (1 of 5) GFMRx - General FCC Mode Register P TR TT CD CT CD CT DIAG TCI - X X P SP S SS RT RE EN EN SYNL RENC TENC TCRC MODE SM VD R T FDSRx - FCC Data Synchronization Register P SYN2 SYN1 FTODRx - FCC Transmit-on-Demand Register P TO D - 2-5

6 Programming Model (2 of 5) FPSMRx - HDLC Mode Register P FS MF NOF - TS - E F NI - CRC - B FCCEx/FCCMx - HDLC Event/Mask Register P GR TX RX BS TX RX - - A E F Y B B FL ID - - G L FCCSx - FCC Status Register P FG - ID Description 1. FPSMRx - TS enables the time stamp feature. When a frame is received, the time stamp is the first 4 bytes copied to the receive buffer. NIB enables the nibble mode. 2. FCCEx/FCCMx - FLG sets when the FG bit in SCCS changes state. 3. FCCSx - FG sets when flags are detected. 2-6

7 Programming Model (3 of 5) FCCx Parameter RAM P Address Name Width Description FCC Base + 00 RIPTR halfword Pointer to temp. Rx 32 byte buffer FCC Base + 02 TIPTR halfword Pointer to temp. Tx 32 byte buffer FCC Base + 04 halfword reserved FCC Base + 06 MRBLR halfword Max. Rx Buffer Length FCC Base + 08 R(FCR)State word Function codes & Rx Internal state FCC Base + 0C RBASE word Base pointer to Buffer descriptors FCC Base + 10 RBDSTAT halfword RISC RxBD status & control FCC Base + 12 RBDLEN halfword RxBD data length - down count FCC Base + 14 RDPTR word next Rx buffer FCC Base + 18 T(FCR)State word Function codes & Tx Internal state FCC Base + 1C TBASE word Base pointer to Buffer descriptors FCC Base + 20 TBDSTAT halfword RISC TxBD status & control FCC Base + 22 TBDLEN halfword TxBD data length - down count FCC Base + 24 TDPTR word next Tx buffer FCC Base + 28 RBPTR word next/current RxBD to use FCC Base + 2C TBPTR word next/current TxBD to use FCC Base + 30 RCRC word Temp Rx CRC FCC Base + 34 TCRC word Temp Tx CRC FCC Base + 38 First word of Protocol specific Area Description 1. Bolded items must be initialized by the user. 2. The function codes are the most significant byte in TSTATE and RSTATE. 2-7

8 Programming Model (4 of 5) FCRx - Function Code Register P GB TC DT BD - BO L 2 B B RxBD - HDLC Receive Buffer Descriptor P E - W I L F CM - LG NO AB CR OV CD Data Length Rx Data Buffer Pointer TxBD - HDLC Transmit Buffer Descriptor P R - W I L TC CM - UN CT Data Length Tx Data Buffer Pointer Description of FCRx 1. GBL - global:if set, the GBL pin will be asserted to indicate to other bus masters that a shared area is being accessed. 2. BO - byte order:indicates either big-endian or PPC little-endian. 3. TC2 - transfer code pin 2 is driven with this value when this FCC is the source of the access. 4. DTB - indicates if the data buffers are on local or 60x bus. 5. BDB - indicates if interrupt queues and free buffers are on local bus or 60x bus. 2-8

9 FCCx HDLC Parameter RAM P Address Name Width Description FCC Base + 0x44 FCC Base + 0x48 FCC Base + 0x4C FCC Base + 0x4E FCC Base + 0x50 FCC Base + 0x52 FCC Base + 0x54 FCC Base + 0x58 FCC Base + 0x5A FCC Base + 0x5C FCC Base + 0x5E FCC Base + 0x60 FCC Base + 0x62 FCC Base + 0x64 FCC Base + 0x66 Programming Model (5 of 5) C_MASK C_PRES DISFC CRCEC ABTSC NMARC MAX_CNT MFLR RFTHR RFCNT HMASK HADDR1 HADDR2 HADDR3 HADDR4 words halfwords word halfwords CRC constant CRC preset Discarded frame count CRC error count Abort sequence count Nonmatching address Rx count Max_length down counter Max. frame length Received frames threshold Received frames count (down) User-defined frame address mask User-defined frame address User-defined frame address User-defined frame address User-defined frame address 2-9

10 How the FCC-HDLC Controller Transmits Data Introduction The following state diagram shows the basic operation of the FCC-HDLC transmitter. State Diagram GFMRx[ENT]=1 Restart Transmit Flag appended & FCCEx[GRA]=0 graceful stop xmit enabled TxBD[R]=1 & CTS*=0 xmit TxB sent & TxBD[L]=1 End frame Flag appended & FCCEx[GRA]=1 TxBD[R]=1 TxB sent & TxBD[L]=0 Stop Transmit Abort Close buffer Restart Transmit Description of States 1. Xmit Enabled - transmits idles or flags depending on GFMRx[RTSM]. 2. Xmit - transmits additional flags if necessary to meet the minimum; then transmits from the data buffer. 3. Close Buffer - clears TxBD[R] (unless TxBD[CM] is set); if TxBD[I] is set, FCCEx[TxB] is set. FCCx[TBPTR] is incremented to the next buffer descriptor. 4. End Frame - if TxBD[TC]=1, the CRC is appended. Clears TxBD[R] (unless TxBD[CM] is set); if TxBD[I] is set, FCCEx[TxB] is set. FCCx[TBPTR] is incremented to the next buffer descriptor. 5. Graceful Stop - transmits idles or flags depending on GFMRx[RTSM]. 6. Abort - transmits no more than 64 bits, flushes the transmit FIFO, and transmits the abort sequence, 0x7F. Then transmit flags or idles depending on GFMRx[RTSM]. CTS lost & Underrun 1. If CTS* becomes high or if a transmit underrun occurs, transmit will not begin again until a restart transmit command is executed. 2-10

11 How the FCC-HDLC Controller Receives Data Introduction The following state diagram shows the basic operation of the FCC-HDLC receiver. State Diagram GFMRx[ENR]=1 Flag received recv hunt Non-flag occurs address check Match & RxBD[E]=1 recv Flag received end frame no match RxBD[E]=1 RxB full 1 Flag recv d Close buffer frame too long 1. Frame length > FCCx[MFLR] Description of States Errors 1. Recv Hunt - waits for a flag followed by a non-flag. 2. Address Check - determines if the address of the frame matches one of the four address registers, FCCx[MASKy], combined with the mask, FCCx[HMASK]. 3. Recv - moves incoming data to the current receive buffer. 4. Close Buffer - clears RxBD[E] (unless TxBD[CM] is set); if RxBD[I] is set, FCCEx[RxB] is set. FCCx[RBPTR] is incremented to the next buffer descriptor. 5. End Frame - checks the CRC; if error, sets RxBD[CR] and increments CRCEC. Writes the frame length to the data length field. RxBD[L] is set. Clears RxBD[E] (unless TxBD[CM] is set); if RxBD[I] is set, FCCEx[RxB] is set. FCCx[RBPTR] is incremented to the next buffer descriptor. Decrements FCCx[RFCNT]; if zero, FCCEx[RxF] is set. If frame was too long, RxBD[LG] is set. 6. Frame Too Long - no more data is received, but the octet count continues. 1. If a non-octet aligned frame is received, RxBD[NO] is set. 2. If the abort sequence, 0x7F, is received, RxBD[AB] is set, RxBD[E] is cleared, and FCCx[ABTSC] is incremented. The receiver then goes to recv hunt. 3. If a CRC error occurs, RxBD[CR] is set, and FCCx[CRCEC] is incremented. 4. If an overrun error occurs, RxBD[OV] is set, and the buffer is closed. 5. If a CD lost error occurs, RxBD[CD] is set, and the buffer is closed. 2-11

12 How to Provide the FCC Clocks Introduction The following diagram describes how to connect a clock source to an FCC. Programming Model Example CMXFCR - FCC Clock Route Register P FC FC - RF1CS TF1CS - RF2CS TF2CS FC - RF3CS TF3CS - 3 The FCCs on an 8260 are to have the following connections: FCC NMSI Y Y N Recv CLK CLK9 BRG8 - Xmit CLK BRG6 CLK14 - Write the initialization value for CMXFCR. pimm->cmxfcr = 0x211D4000; Description 1. Clock sources are connected to the FCCs by way of the CMXFCR. 2. Each FCC has one byte to connect the clocks. Each byte has a field as follows: - FCx - connects the FCC to either its NMSI pins or to the TSA. - RFxCS - connects the receiver to one of eight clock sources. - TFxCS - connects the transmitter to one of eight clock sources. 2-12

13 How to Initialize a Baud Rate Generator Introduction The following diagram describes how to initialize a baud rate generator for a particular bit rate. Programming Model Example BRGCx - BRG Configuration Register P RS - EN T DIV EXTC AB CD 16 BRG 4 is to be configured to generate 500Kbps bit rate. The input clock is CLK15 which is 33MHz. Write the initialization value for BRGC4. CD = (ClkFreq/(bit rate * DIV16)) - 1 = (33 * 10 6 /(.5 * 10 6 * [1 or 16])) - 1 = (33/.5) - 1 = 66-1 = 65 pimm->brgc4 = 1<<16 + 2<< <<1; Description 1. Eight baud rate generators are available to be used as internal clock sources to the FCCs. 2. The output bit rate of a BRG is determined by the clock input frequency divided by BRGx[DIV16], 1 or 16, and divided by a count value in BRGx[CD]. 3. Also, a clock input must be selected in BRGx[EXTC] and the baud rate generator must be enabled in BRGx[EN]. 2-13

14 How to Initialize an 8260 FCC for HDLC (1 of 6) Assumption Hard reset conditions exist. Steps in the Initialization Procedure Step Action Example Configure ports as required pimm->pdira=0x3c00; 1 pimm->ppara=0xfc00; 2 3 If an internally generated clock is to be used, initialize Baud Rate Configuration Reg, BRGCn CD:clock divider DIV16: prescalar EXTC:clock source select EN: enable BRG RST: reset BRG (16-2) Initialize the FCC Clock Route Reg, CMXFCR FCn:select NMSI or TDM RFnCS:recv clock select TFnCS:xmit clock select (15-12) pimm->brgc4=0x14330; pimm->cmxfcr=0x211d00; 2-14

15 How to Initialize an 8260 FCC for HDLC (2 of 6) Steps in the Initialization Procedure Step Action Example Initialize the General FCC Mode pimm->gfmr=0x2000; Reg, GFMR 4 DIAG:normal,loopback, or echo TCI:transmit clock invert CTSP:CTS pulse or envelope CDS:CD sampl sync or async CTSS:CTS sampl sync or async RTSM:idles or flags RENC:NRZ or NRZI TENC:NRZ or NRZI MODE:select HDLC (28-3) 2-15

16 How to Initialize an 8260 FCC for HDLC (3 of 6) Steps in the Initialization Procedure Step Action Example Initialize the FCC HDLC Mode pimm->fpsmr=0x ; Reg, FPSMR 5 6 NOF:no. of flags between frms FSE:flag sharing enable MFF:multiple frames in FIFO TS:time stamp NBL:nibble mode CRC:16 or 32 bit CRC (31-7) Initialize the FCC Parameter RAM RIPTR:recv DPRAM3 pointer TIPTR:xmit DPRAM3 pointer MRBLR:max recv buffer lngth RSTATE:recv internal state RBASE:RxBD base address TSTATE:xmit internal state TBASE:TxBD base address (28-10) pimm->fcc1.rstate= 0x10<<24; 2-16

17 How to Initialize an 8260 FCC for HDLC (4 of 6) Steps in the Initialization Procedure Step Action Example Initialize RxBDs 7 8 rxbdptr:pointer to data buffer rxbddl:data length rxbdsac:status and control Initialize TxBDs (31-9) txbdptr:pointer to data buffer txbddl:data length txbdsac:status and control (31-12) pdsc->rxbd2.rxbdsac= 0x9000; pdsc->txbd1.txbddl=50; 2-17

18 How to Initialize an 8260 FCC for HDLC (5 of 6) Steps in the Initialization Procedure Step Action Example Initialize the FCC Mask Reg, pimm->fccm2=0xa; FCCMn 9 GRA:graceful stop TXE:xmit error RxF:receive frame BSY:busy TxB:xmit buffer sent RxB:recv buffer closed FLG:flag status IDL:idle status change (31-14) 10 Initialize FCC Priority, SCPRR_H XCxP:priority order (4-19) pimm->scprr_h = 0x ; 11 Initialize Interrupt Mask Reg, SIMR_L FCCn:interrupt mask bit (4-22) pimm->simr_l = 1<<30; 2-18

19 How to Initialize an 8260 FCC for HDLC (6 of 6) Steps in the Initialization Procedure Step Action Example Initialize Rx/Tx Parameters via pimm->cpcr=0x ; Command Reg, CPCR PAGE:page number SBC:sub-block code FLG:command semaphore flag MCN:protocol code OPCODE:operation code (13-12) Enable transmitand/or receive in GFMR ENR:enable receive ENT:enable transmit (28-3) pimm->gfmr = 1<<4; 2-19

20 HDLC Example (1 of 3) /* This is an example of receiving a buffer of data. The */ /* receive buffer closes either if it is filled or if a */ /* frame is completed. When the buffer is closed, an LED */ /* counter is incremented. */ void *const stdout = 0; /* STANDARD OUTPUT DEVICE */ #define hdlcf3 /* FCC3 IS TO BE HDLC */ #include mpc8260.h /* INTNL MEMORY MAP EQUATES */ extern struct immbase *pimm; /* POINTER TO INTNL MEMORY MAP*/ struct descs { rxbdfh RxBD0; /* RECEIVE BUFFER 0 */ }; struct descs *pdsc; /* POINTER TO DESCRIPTOR */ main() { clrdpr(); /* CLEAR DUAL PORT RAM */ pimm->pdatd = 0; /* CLEAR PORT D DATA REG */ pimm->pdird = 0xFF; /* MAKE PORT D24-31 OUTPUT*/ 2-20

21 HDLC Example (2 of 3) pimm->pparb = 0x00F00000; /* PB8-11 ARE RxD0,1,2,3 */ pimm->brgc6 = 1<< <<1 + 1; /* 64Kbps AT 133 MHz */ pimm->cmxfcr = 0x800; /* ROUTE BRG6 TO FCC3 */ /* INIT GFMR3: FROM RESET GFMR IS ZERO WHICH IS REQ D */ pimm->fpsmr3 = 0x ; /* 1 FLAG BETWEEN FRAMES */ /* ENABLE TIME STAMP, */ /* NIBBLE MODE,32-BIT CRC*/ pimm->fcc3.riptr = 0xB ; /* INIT TEMP RECV PNTR */ pimm->fcc3.mrblr = 1000; /* MAX RECV BUFFER=1KBYTE*/ pimm->fcc3.rstate = 0x11<<24; /* BIG ENDIAN,BDS LOCAL */ pimm->fcc3.rbase = 0x100000; /* RxBDS AT 0x */ pdsc = (struct descs *) 0x100000; /* INIT PNTR TO RxBD */ pdsc->rxbd0.rxbdptr = 0x200000; /* Rx BUFFER AT 0x */ pdsc->rxbd0.rxbdsac = 0xB000; /* INIT SAC EMPTY,WRAP, &*/ /* INTERRUPT */ /* NO TRANSMIT REQUIREMENT, THEREFORE NO TxBDS */ /* NO INTERRUPTS, THEREFORE FCCM3 IS NOT CHANGED */ /* DEFAULT PRIORITY ORDER OK, THEREFORE SCPRR_H NOT CHNGD*/ /* NO INTERRUPTS,THEREFORE SIMR_L IS NOT CHANGED */ pimm->cpcr = 0x1A410001; /* INIT Rx PARAMETERS */ while ((pimm->cpcr & (1<<16)) == 1<<16); 2-21

22 HDLC Example (3 of 3) } pimm->gfmr3 = 1<<5; /* ENABLE RECEIVE */ while ((pimm->fcce3 & (9<<16)) == 0); /* WAIT FOR EVENT*/ pimm->pdatd += 1; /* INCREMENT PORT D */ clrdpr() { UWORD *pint; /* integer pointer */ } pint = (UWORD *)(UWORD)pimm; for (i = 0; i < 0x1000; i++) /* CLEAR DPRAM1 */ *pint++ = 0; pint = (UWORD *)((UWORD)pimm + 0x8000); for (i = 0; i < 0x400; i++) /* CLEAR DPRAM2 */ *pint++ = 0; pint = (UWORD *)((UWORD)pimm + 0xB000); for (i = 0; i < 0x400; i++) /* CLEAR DPRAM3 */ *pint++ = 0; 2-22

23 HDLC Exercise (1 of 3) /* This is an example of transmitting on FCC1 in HDLC. A */ /* frame of data is transmitted using two buffers. When the*/ /* second buffer has been sent, the LED counter on Port D */ /* is incremented. */ void *const stdout = 0; /* STANDARD OUTPUT DEVICE */ #define hdlcf1 /* FCC1 IS TO BE HDLC */ #include mpc8260.h /* INTNL MEMORY MAP EQUATES */ extern struct immbase *pimm; /* POINTER TO INTNL MEMORY MAP*/ struct descs { txbdfh TxBD0; /* TRANSMIT BUFFER 0 */ txbdfh TxBD1; /* TRANSMIT BUFFER 1 */ }; struct descs *pdsc; /* POINTER TO DESCRIPTOR */ main() { clrdpr(); /* CLEAR DUAL PORT RAM */ pimm->pdatd = 0; /* CLEAR PORT D DATA REG */ pimm->pdird = 0xFF; /* MAKE PORT D24-31 OUTPUT*/ 2-23

24 HDLC Exercise (2 of 3) pimm->pparb = 0x ; /* PB4 IS TxD */ pimm->brgc7 = 1<<16 + <<1 + 1; /* 256Kbps AT 133 MHz */ pimm-> = 0x ; /* ROUTE BRG7 TO FCC1 */ pimm->gfmr1 = 0x ; /* FLAGS BETWEEN FRAMES */ pimm-> = 0x ; /* 2 FLAGS BETWEEN FRAMES*/ /* NO TIME STAMP, NOT */ /* NIBBLE MODE,16-BIT CRC*/ pimm->fcc1.tiptr = 0x + 32; /* INIT TEMP XMIT PNTR */ pimm->fcc1. = 0x12<<24; /* BIG ENDIAN,BUFS LOCAL */ pimm->fcc1. = 0x200000; /* TxBDS AT 0x */ pdsc = (struct descs *) 0x200000; /* INIT PNTR TO TxBD */ pdsc->txbd0.txbdptr = 0x400000; /* Tx BUFFER0 AT 0x400000*/ pdsc->txbd0.txbddl = 100; /* INIT DATA LNGTH TO 100*/ pdsc->txbd0.txbdsac = 0x ; /* INIT SAC READY */ pdsc->txbd1.txbdptr = 0x400800; /* Tx BUFFER1 AT 0x400800*/ pdsc->txbd1.txbddl = 100; /* INIT DATA LNGTH TO 100*/ pdsc->txbd1.txbdsac = 0x ; /* INIT SAC READY,WRAP */ /* INTRPT,LAST,APPEND CRC*/ /* NO RECEIVE REQUIREMENT, THEREFORE NO RxBDS */ /* NO INTERRUPTS, THEREFORE FCCM1 IS NOT CHANGED */ /* DEFAULT PRIORITY ORDER OK, THEREFORE SCPRR_H NOT CHNGD*/ 2-24

25 HDLC Exercise (3 of 3) /* NO INTERRUPTS,THEREFORE SIMR_L IS NOT CHANGED */ pimm->cpcr = 0x ; /* INIT Tx PARAMETERS */ while (pimm->cpcr & (1<<16)) == 1<<16); /*WAIT FLAG CLEAR */ pimm-> = 1<<4; /* ENABLE TRANSMIT */ while ((pimm->fcce1 & (_<<16)) == 0); /* WAIT FOR EVENT */ pimm->pdatd += 1; /* INCREMENT PORT D */ } clrdpr() { UWORD *pint; /* integer pointer */ } pint = (UWORD *)(UWORD)pimm; for (i = 0; i < 0x1000; i++) /* CLEAR DPRAM1 */ *pint++ = 0; pint = (UWORD *)((UWORD)pimm + 0x8000); for (i = 0; i < 0x400; i++) /* CLEAR DPRAM2 */ *pint++ = 0; pint = (UWORD *)((UWORD)pimm + 0xB000); for (i = 0; i < 0x400; i++) /* CLEAR DPRAM3 */ *pint++ = 0; 2-25