Introduction to Control Divergence

Transcription

1 Introduction to Control Divergence Lectures Slides and Figures contributed from sources as noted (1) Objective Understand the occurrence of control divergence and the concept of thread reconvergence v Also described as branch divergence and thread divergence Cover a basic thread reconvergence mechanism PDOM v Set up discussion of further optimizations and advanced techniques xplore one approach for mitigating the performance degradation due to control divergence dynamic warp formation (2) 1

2 Reading W. Fung, I. Sham, G. Yuan, and T. Aamodt, Dynamic Warp Formation: fficient MIMD Control Flow on SIMD Graphics Hardware, ACM TACO, June 2009 W. Fung and T. Aamodt, Thread Block Compaction for fficient SIMT Control Flow, International Symposiumomn High Performance Computer Architecture, 2011 M. Rhu and M. rez, CAPRI: Prediction of Compaction- Adequacy for Handling Control-Divergence in GPGPU Architectures, ISCA 2012 Figure from M. Rhu and M. rez, Maximizing SIMD Resource Utilization on GPGPUs with SIMD Lane Permutation, ISCA 2013 (3) Handling Branches CUDA Code: if( ) (True for some threads) else (True for others) T T T T taken not taken What if threads takes different branches? Branch Divergence! (4) 2

3 Branch Divergence Occurs within a warp Branches lead serialization branch dependent code v Performance issue: low warp utilization if( ) { } Idle threads else { } Reconvergence! (5) Branch Divergence A C B D F Thread Warp Thread 1 Thread 2 Common PC Thread Thread 3 4 G Different threads follow different control flow paths through the kernel code Thread execution is (partially) serialized v Subset of threads that follow the same path execute in parallel Courtesy of Wilson Fung, Ivan Sham, George Yuan, Tor Aamodt 3

4 Basic Idea Split: partition a warp v Two mutually exclusive thread subsets, each branching to a different target v Identify subsets with two activity masks à effectively two warps Join: merge two subsets of a previously split warp v Reconverge the mutually exclusive sets of threads Orchestrate the correct execution for nested branches Note the long history of technques in SIMD processors (see background in Fung et. al.) Thread Warp T1 T2 T3 T4 Common PC activity mask (7) Thread Reconvergence Fundamental problem: v Merge threads with the same PC v How do we sequence execution of threads? Since this can effect the ability to reconverge Question: When can threads productively reconverge? Question: When is the best time to reconverge? A B C D F G (8) 4

5 Dominator Node d dominates node n if every path from the entry node to n must go through d A B C D F G (9) Immediate Dominator Node d immediate dominates node n if every path from the entry node to n must go through d and no other nodes dominate n between d and n A B C D F G (10) 5

6 Post Dominator Node d post dominates node n if every path from the node n to the exit node must go through d A B C D F G (11) Immediate Post Dominator Node d immediate post dominates node n if every path from node n to the exist node must go through d and no other nodes post dominate n between d and n A B C D F G (12) 6

7 Baseline: PDOM A A/1111 B B/1111 Stack Reconv. PC Next PC Active Mask TOS - G A B 1111 TOS D 0110 TOS C 1001 C C/1001 D D/0110 /1111 G G/1111 F Thread Warp Thread 1 Thread 2 Thread 3 Common PC Thread 4 A B C D G A Courtesy of Wilson Fung, Ivan Sham, George Yuan, Tor Aamodt Time Stack ntry A A/1111 B B/1111 Stack Reconv. PC Next PC Active Mask TOS - G A B 1111 TOS D 0110 TOS C 1001 C C/1001 D D/0110 F /1111 G G/1111 A stack entry is a specification of a group of active threads that will execute that basic block The natural nested structure of control exposes the use stack-based serialization (14) 7

8 More Complex xample Stack based implementation for nested control flow v Stack entry RPC set to IPDOM Re-convergence at the immediate post-dominator of the branch From Fung, et. Al., Dynamic Warp Formation: fficient MIMD Control Flow in SIMD Graphics Hardware, ACM TACO, June 2009 (15) Implementation I-Fetch scalar Pipeline Decode I-Buffer Issue PRF RF scalar pipeline D-Cache All Hit? Data Writeback scalar pipeline pending warps Stack Reconv. PC Next PC Active Mask TOS - G A B 1111 TOS D 0110 TOS C 1001 GPGPUSim model: v Implement per warp stack at issue stage v Acquire the active mask and PC from the TOS v Scoreboard check prior to issue v Register writeback updates scoreboard and ready bit in instruction buffer v When RPC = Next PC, pop the stack Implications for instruction fetch? FromGPGPU-Sim Documentation Sim_3.x_Manual#SIMT_Cores (16) 8

9 Implementation (2) warppc (next instruction) compared to reconvergence PC On a branch v Can store the reconvergence PC as part of the branch instruction v Branch unit has NextPC, TargetPC and reconvergence PC to update the stack On reaching a reconvergence point v Pop the stack v Continue fetching from the NextPC of the next entry on the stack (17) Warps are formed statically Can We Do Better? Key idea of dynamic warp formation v Show a pool of warps and how they can be merged At a high level what are the requirements B A C D F G (18) 9

10 Compaction Techniques Can we reform warps so as to increase utilization? Basic idea: Compaction v Reform warps with threads that follow the same control flow path v Increase utilization of warps Two basic types of compaction techniques Inter-warp compaction v Group threads from different warps v Group threads within a warp o Changing the effective warp size (19) Inter-Warp Thread Compaction Techniques Lectures Slides and Figures contributed from sources as noted (20) 10

11 Goal Warp 0 Merge threads? Warp 1 Warp 2 Warp 3 if( ) { } Taken Not Taken Warp 4 Warp 5 else { } (21) Reading W. Fung, I. Sham, G. Yuan, and T. Aamodt, Dynamic Warp Formation: fficient MIMD Control Flow on SIMD Graphics Hardware, ACM TACO, June 2009 W. Fung and T. Aamodt, Thread Block Compaction for fficient SIMT Control Flow, International Symposiumomn High Performance Computer Architecture, 2011 (22) 11

12 DWF: xample Baseline B x/1110 y/0011 A x/1111 y/1111 C x/1000 y/0010 D x/0110 y/0001 F x/0001 y/1100 x/1110 y/0011 G x/1111 y/1111 Legend A A xecution of Warp x at Basic Block A D A new warp created from scalar threads of both Warp x and y executing at Basic Block D A A B B C C D D F F G G A A xecution of Warp y at Basic Block A Dynamic Warp Formation Courtesy of Wilson Fung, Ivan Sham, George Yuan, Tor Aamodt A A B B C D F G G A A Time Time How Does This Work? Criteria for merging v Same PC v Complements of active threads in each warp v Recall: many warps/tb all executing the same code What information do we need to merge two warps v Need thread IDs and PCs Ideally how would you find/merge warps? (24) 12

13 DWF: Microarchitecture Implementation Identify available lanes Assists in aggregating threads Identify occupied lanes Point to warp being formed Thread Scheduler PC-Warp LUT Warp Update Register T TID x N RQ PC A Warp Update Register NT TID x N RQ PC B H H PC OCC PC OCC IDX IDX Warp Pool PC PC PC TID x N Prio TID x N Prio TID x N Prio I s s u e L o g i c Warp Allocator Commit/ Writeback Courtesy of Wilson Fung, Ivan Sham, George Yuan, Tor Aamodt ALU 1 ALU 2 ALU 3 ALU 4 RF 1 RF 2 RF 3 RF 4 (TID, Reg#) (TID, Reg#) (TID, Reg#) (TID, Reg#) Warps formed dynamically in the warp pool After commit check PC-Warp LUT and merge or allocated newly forming warp Decode I-Cache DWF: Microarchitecture Implementation A: BQ R2, B C: Thread Scheduler PC-Warp LUT Warp Pool Warp Update Register T PC B OCC IDX 02 PC A B 15 TID 2 3 x N 48 5 TID 2 x 73 N RQ PC B A H PC C OCC IDX 1 PC A C 51 TID 6 7 x N 84 Warp Update Register NT PC B TID x C TID x N Commit/ Writeback RQ X Y PC B H ALU 1 ALU 2 ALU 3 ALU 4 X Y RF 1 RF 2 RF 3 RF 4 N Warp Allocator X Z Y (TID, Reg#) (TID, Reg#) (TID, Reg#) (TID, Reg#) Prio Prio Prio X Z Y Decode I s s u e L o g i c X Z Y I-Cache No Lane Conflict Courtesy of Wilson Fung, Ivan Sham, George Yuan, Tor Aamodt 13

14 Resource Usage Ideally would like a small number of unique PCs in progress at a time à minimize overhead Warp divergence will increase the number of unique PCs v Mitigate via warp scheduling Scheduling policies v FIFO v Program counter address variation measure of divergence v Majority/Minority- most common vs. helping stragglers v Post dominator (catch up) (27) Hardware Consequences xpose the implications that warps have in the base design v Implications for register file access à lane aware DWF Register bank conflicts From Fung, et. Al., Dynamic Warp Formation: fficient MIMD Control Flow in SIMD Graphics Hardware, ACM TACO, June 2009 (28) 14

15 Relaxing Implications of Warps Thread swizzling v ssentially remap work to threads so as to create more opportunities for DWF à requires deep understanding of algorithm behavior and data sets Lane swizzling in hardware v Provide limited connectivity between register banks and lanes à avoiding full crossbars (29) Summary Control flow divergence is a fundamental performance limiter for SIMT execution Dynamic warp formation is one way to mitigate these effects v We will look at several others Must balance a complex set of effects v Memory behaviors v Synchronization behaviors v Scheduler behaviors (30) 15

16 Thread Block Compaction W. Fung and T. Aamodt HPCA 2011 Overcome some of the disadvantages of dynamic warp formation v Impact of Scheduling v Breaking implicit synchronization v Reduction of memory coalescing opportunities Goal (32) 16

17 DWF Pathologies: Starva:on Majority Scheduling Best Performing Priori:ze largest group of threads with same PC Starva&on LOWR SIMD fficiency! Other Warp Scheduler? Tricky: Variable Memory Latency B: if (K > 10) C: K = 10; else D: K = 0; : B = C[tid.x] + K; C C D D s cycles D D Time Wilson Fung, Tor Aamodt Thread Block Compac:on 33 DWF Pathologies: xtra Uncoalesced Accesses Coalesced Memory Access = Memory SIMD 1 st Order CUDA Programmer Op:miza:on Not preserved by DWF : B = C[tid.x] + K; No DWF With DWF #Acc = 3 #Acc = 9 0x100 0x140 0x180 0x100 0x140 0x180 Memory Memory L1 Cache Absorbs Redundant Memory Traffic L1$ Port Conflict Wilson Fung, Tor Aamodt Thread Block Compac:on 34 17

18 DWF Pathologies: Implicit Warp Sync. Some CUDA applications depend on the lockstep execution of static warps Warp 0 Warp 1 Warp 2 Thread Thread Thread From W. Fung, I. Sham, G. Yuan, and T. Aamodt, Dynamic Warp Formation: fficient MIMD Control Flow on SIMD Graphics Hardware, ACM TACO, June 2009 Wilson Fung, Tor Aamodt (35) Performance Impact From W. Fung and T. Aamodt, Thread Block Compaction for fficient SIMT Control Flow, International Symposiumomn High Performance Computer Architecture, 2011 (36) 18

19 Thread Block Compaction n Block-wide Reconvergence Stack Thread Warp Block 0 0 Warp 1 Warp 2 PC RPC AMask Active PC RPC Mask AMask PC RPC AMask Warp D D D D Warp 1100 U 1 C C C C D Warp 0011 X T 2 C Warp Y q Regroup threads within a block n Better Reconv. Stack: Likely Convergence q Converge before Immediate Post-Dominator n Robust q Avg. 22% speedup on divergent CUDA apps q No penalty on others Wilson Fung, Tor Aamodt Thread Block Compaction 37 GPU Microarchitecture SIMT SIMT Core Core SIMT SIMT Core SIMT Core Done (Warp ID) Interconnection Network Memory Memory Partition Last-Level Cache Cache Bank Bank Cache Bank DRAM DRAM Off-Chip DRAM Channel SIMT Front nd SIMD Datapath Fetch Decode Schedule Branch Memory Subsystem SMem L1 D$ Tex $ Const$ Icnt. Network More Details in Paper Wilson Fung, Tor Aamodt Thread Block Compaction 19

20 Observation n Compute kernels usually contain divergent and non-divergent (coherent) code segments n Coalesced memory access usually in coherent code segments q DWF no benefit there Coherent Divergent Static Warp Divergence Dynamic Warp Reset Warps Coales. LD/ST Coherent Static Warp Recvg Pt. Wilson Fung, Tor Aamodt Thread Block Compaction 39 Thread Block Compaction n Branch/reconverge pt. q All avail. threads arrive at branch q Insensitive to warp scheduling n Run a thread block like a warp q Whole block move between coherent/divergent code q Block-wide stack to track exec. paths reconvg. n Warp compaction q Regrouping with all avail. threads Implicit Warp Sync. Starvation xtra Uncoalesced Memory Access q If no divergence, gives static warp arrangement Wilson Fung, Tor Aamodt Thread Block Compaction 40 20

21 Thread Block Compaction PC RPC Active Threads A D C A A A A A A A: K = A[tid.x]; B: if (K > 10) C: K = 10; else D: K = 0; : B = C[tid.x] + K; C C D D C C C D D D Time Wilson Fung, Tor Aamodt Thread Block Compaction 41 Thread Block Compaction n Barrier every basic block?! (Idle pipeline) n Switch to warps from other thread blocks q Multiple thread blocks run on a core q Already done in most CUDA applications Branch Warp Compaction Block 0 xecution xecution Block 1 Block 2 xecution Time xecution Wilson Fung, Tor Aamodt Thread Block Compaction 42 21

22 High Level View DWF: warp broken down every cycle and threads in a warp shepherded into a new warp (LUT and warp pool) TBC: warps broken down at potentially divergent points and threads compacted across the thread block (43) Microarchitecture Modification n Per-Warp Stack à Block-Wide Stack n I-Buffer + TIDs à Warp Buffer q Store the dynamic warps n New Unit: Thread Compactor q Translate activemask to compact dynamic warps n More Detail in Paper Fetch I-Cache Branch Target PC Valid[1:N] Decode Warp Buffer Score- Board Thread Compactor Issue Done (WID) Block-Wide Stack Pred. Active Mask RegFile ALU ALU MM Wilson Fung, Tor Aamodt Thread Block Compaction 44 22

23 Microarchitecture Modification (2) TIDs of #compacted warps #compacted warps From W. Fung and T. Aamodt, Thread Block Compaction for fficient SIMT Control Flow, International Symposiumomn High Performance Computer Architecture, 2011 (45) Operation All threads mapped to the same lane Warp 2 arrives first creating 2 target entries Next warps update the active mask When this is zero compact (priority encoder) Pick a thread mapped to this lane From W. Fung and T. Aamodt, Thread Block Compaction for fficient SIMT Control Flow, International Symposiumomn High Performance Computer Architecture, 2011 (46) 23

24 Thread Compactor n Convert activemask from block-wide stack to thread IDs in warp buffer n Array of Priority-ncoder C P-nc P-nc P-nc P-nc Warp Buffer C C Wilson Fung, Tor Aamodt Thread Block Compaction 47 Likely-Convergence n Immediate Post-Dominator: Conservative q All paths from divergent branch must merge there n Convergence can happen earlier q When any two of the paths merge while (i < K) { X = data[i]; A: if ( X = 0 ) B: result[i] = Y; B C: else if ( X = 1 ) D: break; : i++; } ipdom of A F: return result[i]; Rarely Taken n xtended Recvg. Stack to exploit this q TBC: 30% speedup for Ray Tracing A F C D Details in Paper Wilson Fung, Tor Aamodt Thread Block Compaction 48 24

25 Likely-Convergence (2) n NVIDIA uses break instruction for loop exits q That handles last example n Our solution: Likely-Convergence Points PC RPC LPC LPos ActiveThds F F B F 1 1 C D F F 1 2 Convergence! n This paper: only used to capture loop-breaks Wilson Fung, Tor Aamodt Thread Block Compaction 49 Likely-Convergence (3) Check! Merge inside the stack From W. Fung and T. Aamodt, Thread Block Compaction for fficient SIMT Control Flow, International Symposiumomn High Performance Computer Architecture, 2011 (50) 25

26 Likely-Convergence (4) n Applies to both per-warp stack (PDOM) and thread block compaction (TBC) q nable more threads grouping for TBC q Side effect: Reduce stack usage in some case Wilson Fung, Tor Aamodt Thread Block Compaction 51 valuation n Simulation: GPGPU-Sim (2.2.1b) q ~Quadro FX L1 & L2 Caches n 21 Benchmarks q All of GPGPU-Sim original benchmarks q Rodinia benchmarks q Other important applications: n n n n Face Detection from Visbench (UIUC) DNA Sequencing (MUMMR-GPU++) Molecular Dynamics Simulation (NAMD) Ray Tracing from NVIDIA Research Wilson Fung, Tor Aamodt Thread Block Compaction 52 26

27 xperimental Results n 2 Benchmark Groups: q COH = Non-Divergent CUDA applications q DIVG = Divergent CUDA applications DWF TBC COH DIVG Serious Slowdown from pathologies No Penalty for COH 22% Speedup on DIVG IPC Relative to Baseline Per-Warp Stack Wilson Fung, Tor Aamodt Thread Block Compaction 53 Normalized Memory Stalls ffect on Memory Traffic n TBC does still generate some extra uncoalesced memory access 300% 250% 200% 150% 100% 50% 0% C C nd Acc will hit the L1 cache TBC DWF Baseline Memory Traffic Normalized to Baseline #Acc = BFS2 FCDT 0x100 0x140 0x180 HOTSP Memory TBC-AG TBC-RRB 2.67x LPS MUM DIVG MUMpp NAMD NVRT AS BACKP CP DG HRTWL LIB No Change to Overall Memory Traffic In/out of a core LKYT MGST COH NNC RAY STMCL STO WP Wilson Fung, Tor Aamodt Thread Block Compaction 54 27

28 Conclusion Thread Block Compaction v Addressed some key challenges of DWF v One significant step closer to reality Benefit from advancements on reconvergence stack v Likely-Convergence Point v xtensible: Integrate other stack-based proposals Wilson Fung, Tor Aamodt Thread Block Compaction (55) CAPRI: Prediction of Compaction- Adequacy for Handling Control- Divergence in GPGPU Architectures M. Rhu and M. rez ISCA

29 Improve the performance of inter-warp compaction techniques Predict when branches diverge v Borrow philosophy from branch prediction Use prediction to apply compaction only when it is beneficial Goals (57) Issues with Thread Block Compaction C B Implicit barrier across warps to collect compaction candidates A D G F TBC: warps broken down at potentially divergent points and threads compacted across the thread block Barrier synchronization overhead cannot always be hidden When it works, it works well (58) 29

30 Divergence Behavior: A Closer Look Compaction ineffective branch Loop executes a fixed number of times Figure from M. Rhu and M. rez, CAPRI: Prediction of Compaction-Adequacy for Handling Control- Divergence in GPGPU Architectures, ISCA 2012 (59) Compaction-Resistant Branches Control flow graph Figure from M. Rhu and M. rez, CAPRI: Prediction of Compaction-Adequacy for Handling Control- Divergence in GPGPU Architectures, ISCA 2012 (60) 30

31 Compaction-Resistant Branches(2) Control flow graph Figure from M. Rhu and M. rez, CAPRI: Prediction of Compaction-Adequacy for Handling Control- Divergence in GPGPU Architectures, ISCA 2012 (61) Impact of Ineffective Compaction Threads shuffled around with no performance improvement However, can lead to increased memory divergence! Figure from M. Rhu and M. rez, CAPRI: Prediction of Compaction-Adequacy for Handling Control- Divergence in GPGPU Architectures, ISCA 2012 (62) 31

32 Only stall and compact when there is a high probability of compaction success Basic Idea Otherwise allow warps to bypass the (implicit) barrier Compaction adequacy predictor! v Think branch prediction! (63) xample: TBC vs. CAPRI Bypassing enables increased overlap of memory references Figure from M. Rhu and M. rez, CAPRI: Prediction of Compaction-Adequacy for Handling Control- Divergence in GPGPU Architectures, ISCA 2012 (64) 32

33 CAPRI: xample No divergence, no stalling Diverge, stall, initialize history, all others will now stall Diverge and history available, predict, update prediction All other warps follow (one prediction/ branch CAPT updated Figure from M. Rhu and M. rez, CAPRI: Prediction of Compaction-Adequacy for Handling Control- Divergence in GPGPU Architectures, ISCA 2012 (65) Available threads in a lane The Predictor Prediction uses active masks of all warps v Need to understand what could have happened Actual compaction only uses actual stalled warps Minimum provides the maximum compaction ability, i.e., #compacted warps Update history predictor accordingly Figure from M. Rhu and M. rez, CAPRI: Prediction of Compaction-Adequacy for Handling Control- Divergence in GPGPU Architectures, ISCA 2012 (66) 33

34 Behavior Figure from M. Rhu and M. rez, CAPRI: Prediction of Compaction-Adequacy for Handling Control- Divergence in GPGPU Architectures, ISCA 2012 (67) Impact of Implicit Barriers Idle cycle count helps us understand the negative effects of implicit barriers in TBC Figure from M. Rhu and M. rez, CAPRI: Prediction of Compaction-Adequacy for Handling Control- Divergence in GPGPU Architectures, ISCA 2012 (68) 34

35 Summary The synchronization overhead of thread block compaction can introduce performance degradation Some branches more divergence than others Apply TBC judiciously à predict when it is beneficial ffectively predict when the inter-warp compaction is effective. (69) M. Rhu and M. rez, Maximizing SIMD Resource Utilization on GPGPUs with SIMD Lane Permutation, ISCA

36 Goals Understand the limitations of compaction techniques and proximity to ideal compaction Provide mechanisms to overcome these limitations and approach ideal compaction rates (71) Limitations of Compaction Figure from M. Rhu and M. rez, Maximizing SIMD Resource Utilization on GPGPUs with SIMD Lane Permutation, ISCA 2013 (72) 36

37 Mapping Threads to Lanes: Today Linearization of thread IDs Grid 1 Block (0, 0) Block (1, 0) Block (0, 1) Block (1, 1) Warp 0 Warp 1 Modulo assignment to lanes RF n-1 RF n-1 RF n-1 RF n-1 RF n-1 RF n-1 RF n-1 RF n-1 RF n-2 RF n-2 RF n-2 RF n-2 RF n-2 RF n-2 RF n-2 RF n-2 RF n-3 RF n-3 RF n-3 RF n-3 RF n-3 RF n-3 RF n-3 RF n-3 RF n-4 RF n-4 RF n-4 RF n-4 RF n-4 RF n-4 RF n-4 RF n-4 Block (1,1) (1,0,0) (1,0,1) (1,0,2) (1,0,3) RF1 RF0 RF1 RF0 RF1 RF0 RF1 RF0 RF1 RF0 RF1 RF0 RF1 RF0 RF1 RF0 Thread (0,0,0) Thread (0,1,0) Thread (0,0,1) Thread (0,1,1) Thread (0,0,2) Thread (0,1,2) Thread (0,0,3) Thread Thread (0,0,0) (0,1,3) scalar Pipeline scalar pipeline scalar pipeline scalar pipeline scalar Pipeline scalar pipeline scalar pipeline scalar pipeline (73) Data Dependent Branches Data dependent control flows less likely to produce lane conflicts Figure from M. Rhu and M. rez, Maximizing SIMD Resource Utilization on GPGPUs with SIMD Lane Permutation, ISCA 2013 (74) 37

38 Programmatic Branches Programmatic branches can be correlated to lane assignments (with modulo assignment) Program variables that operate like constants across threads can produced correlated branching behaviors Figure from M. Rhu and M. rez, Maximizing SIMD Resource Utilization on GPGPUs with SIMD Lane Permutation, ISCA 2013 (75) P-Branches vs. D-Branches P-branches are the problem! Figure from M. Rhu and M. rez, Maximizing SIMD Resource Utilization on GPGPUs with SIMD Lane Permutation, ISCA 2013 (76) 38

39 Compaction Opportunities Lane reassignment can improve compaction opportunities Figure from M. Rhu and M. rez, Maximizing SIMD Resource Utilization on GPGPUs with SIMD Lane Permutation, ISCA 2013 (77) Aligned Divergence Threads mapped to a lane tend to evaluate (programmatic) predicates the same way v mpirically, rarely exhibited for input, data dependent control flow behavior Compaction cannot help in the presence of lane conflicts à performance of compaction mechanisms depends on both divergence patterns and lane conflicts We need to understand impact of lane assignment (78) 39

40 Impact of Lane Reassignment Goal: Improve compactability Figure from M. Rhu and M. rez, Maximizing SIMD Resource Utilization on GPGPUs with SIMD Lane Permutation, ISCA 2013 (79) Random Permutations Does not always work well à works well on average Better understanding of programs can lead to better permutations choices Figure from M. Rhu and M. rez, Maximizing SIMD Resource Utilization on GPGPUs with SIMD Lane Permutation, ISCA 2013 (80) 40

41 Mapping Threads to Lanes; New Warp 0 Warp 1 RF n-1 RF n-2 RF n-3 RF n-4 RF n-1 RF n-2 RF n-3 RF n-4 RF n-1 RF n-2 RF n-3 RF n-4 RF n-1 RF n-2 RF n-3 RF n-4 RF n-1 RF n-2 RF n-3 RF n-4 RF n-1 RF n-2 RF n-3 RF n-4 RF n-1 RF n-2 RF n-3 RF n-4 RF n-1 RF n-2 RF n-3 RF n-4 RF1 RF0 RF1 RF0 RF1 RF0 RF1 RF0 RF1 RF0 RF1 RF0 RF1 RF0 RF1 RF0 Warp N-1 scalar pipeline scalar pipeline scalar pipeline scalar Pipeline scalar pipeline scalar pipeline scalar pipeline scalar Pipeline SIMD Width = 8 What criteria do we use for lane assignment? (81) ven warps: permutation within a half warp Balanced Permutation Odd warps: swap upper and lower XOR evenwid = evenwid 2 ach lane has a single instance of a logical thread from each warp Figure from M. Rhu and M. rez, Maximizing SIMD Resource Utilization on GPGPUs with SIMD Lane Permutation, ISCA 2013 (82) 41

42 Balanced Permutation (2) XOR evenwid = evenwid 2 Logical TID of 0 in each warp is now assigned a different lane Figure from M. Rhu and M. rez, Maximizing SIMD Resource Utilization on GPGPUs with SIMD Lane Permutation, ISCA 2013 (83) Characteristics Vertical Balance: ach lane only has logical TIDs of distinct threads in a warp Horizontal balance: Logical TID x in all of the warps is bound to different lanes This works when CTA have fewer than SIMD_Width warps: why? Note that random permutations achieve this only on average (84) 42

43 Impact on Memory Coalescing Modern GPUs do not require ordered requests Coalescing can occur across a set of requests à speicific lane assignments do not affect coalescing behavior Increase is L1 miss rate offset by benefits of compaction Figure from M. Rhu and M. rez, Maximizing SIMD Resource Utilization on GPGPUs with SIMD Lane Permutation, ISCA 2013 (85) Speedup of Compaction Can improve the compaction rate of divergence dues to the majority of programmatic branches Figure from M. Rhu and M. rez, Maximizing SIMD Resource Utilization on GPGPUs with SIMD Lane Permutation, ISCA 2013 (86) 43

44 Compaction Rate vs. Utilization Distinguish between compaction rate and utilization! Figure from M. Rhu and M. rez, Maximizing SIMD Resource Utilization on GPGPUs with SIMD Lane Permutation, ISCA 2013 (87) Application of Balanced Permutation scalar Pipeline I-Fetch Decode I-Buffer Issue PRF RF scalar pipeline scalar pipeline D-Cache All Hit? Data pending warps Permutation is applied when the warp is launched Maintained for the life of the warp Does not affect the baseline compaction mechanism nable/disable SLP to preserve target specific, programmer implemented optimizations Writeback (88) 44

45 Structural hazards limit the performance improvements from inter-warp compaction Program behaviors produce correlated lane assignments today Summary Remapping threads to lanes enables extension of compaction opportunities (89) Summary: Inter-Warp Compaction A Thread Block Thread Block B C D F G Co-Design of applications, resource management, software, microarchitecture, Program Properties Scope μarch Resource Management (90) 45