Resource-efficient regular expression matching architecture for text analytics
|
|
- Theodora Barnett
- 6 years ago
- Views:
Transcription
1 Resource-efficient regular expression matching architecture for text analytics Kubilay Atasu IBM Research - Zurich Presented at ASAP 2014
2 SystemT: an algebraic approach to declarative information extraction distill structured data from unstructured and semi-structured text exploit the extracted data in your applications For years, Microsoft Corporation CEO Bill Gates was against open source. But today he appears to have changed his mind. "We can be open source. We love the concept of shared source," said Bill Veghte, a Microsoft VP. "That's a super-important shift for us in terms of code access. Richard Stallman, founder of the Free Software Foundation, countered saying Annotations Name Title Organization Bill Gates CEO Microsoft Bill Veghte VP Microsoft Richard Stallman Founder Free Soft.. (from Cohen s IE tutorial, 2003) 2
3 A simple SystemT information extraction rule Find the names (regex) that are at most 20 chars after a title (dict.) Founder...Bill Gates dict. match regex match start offset end offset start offset end offset at most 20 chars start offset end offset result 3
4 Finding leftmost regular expression matches Assume that we are searching for the regex.*(a aa aaaa) in the input string aaaa Find the regex match with the smallest start offset value at each end offset position The leftmost maches are marked using solid lines 4
5 Regex matching: background Consider the regex.*(a b aa aba) Can be transformed into NFA/DFA NFA DFA Traditional architectures do not support start offset reporting & leftmost matching: Reconfigurable NFAs (Sidhu FCCM 2001, Bispo FPT 2006, Yang ANCS 2008) Programmable DFAs (Smith SIGCOMM 2008, Van Lunteren MICRO 2012) 5
6 Previous solution: network of state machines active_reg state_reg start_offset_reg -Dimension of the network (# state machines) is statically computed for each regex -DRAWBACK: replication of the state transition logic K. Atasu, R. Polig, C.Hagleitner, F. R. Reiss: Hardware-accelerated regular expression matching for high-throughput text analytics. FPL 2013: 1-7 6
7 Contributions of this work 1. Extending Sidhu and Prasanna s NFA architecture to support start offset reporting 2. A graph coloring based register clustering method to minimize the register usage 3. An efficient leftmost match computation method without using offset comparisons NFA Sidhu and Prasanna s NFA Architecture 7
8 A straightforward extension of Sidhu & Prasanna s architecture Add a start offset register to each NFA state offset_reg[0] = value of current offset position DRAWBACK: redundant start offset registers offset_reg [0] offset_reg [1] offset_reg [3] offset_reg [4] offset_reg [2] NFA Baseline Architecture 8
9 Clustering offset registers NFA DFA Build a conflict graph and apply graph coloring States with the same color can share registers 9
10 Leftmost match computation Assume that state 0 and state 1 are active and the current input is a We have to compute offset_reg[2] = MIN(offset_reg[0], offset_reg[1]) offset_reg [0] offset_reg [1] offset_reg [3] offset_reg [4] offset_reg [2] NFA Baseline Architecture 10
11 Leftmost match computation without offset comparisons (1) Assume that state K has M incoming state transitions We have to compute the minimum of M offset values offset_reg [1] offset_reg [2] offset_reg [0] offset_reg [M-1] K tree-based implementation (long latency) fully parallel implementation (expensive) offset_reg [K] Better solution: each state keeps track of the states that are activated earlier -Define an N N bit matrix: earlier[i,j]=1 if state j is activated before state i 11
12 Leftmost match computation without offset comparisons (2) offset_reg[0] = value of the current offset pointer, earlier[0, :] = active_reg Assume that state 1 is active (i.e., earlier[0,1] = 1), and the input is a we have two transitions into state 2: from state 0 and from state 1 since earlier[0,1] = 1, we choose the start offset provided by state 1 due to transitions 0 1 and 1 2, earlier[1,2]=1 in the next cycle offset_reg [0] offset_reg [1] tr[ 0,2] ( tr[1,2] earlier [0,1]) 2 tr[ 1,2] ( tr[0,2] earlier [1,0]) offset_reg [2] 12
13 Experiments (text analytics regexs) Altera Stratix IV GX530KH40C2, Altera Quartus II V11 tools 32-bit start offset registers, 250 MHz target clock frequency NFA representation: Follow Automata with character classes 13
14 Experiments (L7 filter regexs) Altera Stratix IV GX530KH40C2, Altera Quartus II V11 tools 32-bit start offset registers, 250 MHz target clock frequency NFA representation: Follow Automata with character classes 14
15 Summary & future work Support for start offset reporting and leftmost matching without replicating the state transition logic without using redundant offset registers without using expensive offset comparison > threefold reduction in the logic resource usage > 1.25-fold improvement in the clock frequency < 8.6-fold overhead w.r.t. Sidhu & Prasanna s architecture while using 32-bit offset registers Our current and future work includes design of intermediate fabrics for fast compilation analysis and optimization of the energy consumption 15
16 Resource-efficient regular expression matching architecture for text analytics Kubilay Atasu IBM Research - Zurich Presented at ASAP 2014
TOKEN-BASED DICTIONARY PATTERN MATCHING FOR TEXT ANALYTICS. Raphael Polig, Kubilay Atasu, Christoph Hagleitner
TOKEN-BASED DICTIONARY PATTERN MATCHING FOR TEXT ANALYTICS Raphael Polig, Kubilay Atasu, Christoph Hagleitner IBM Research - Zurich Rueschlikon, Switzerland email: pol, kat, hle@zurich.ibm.com ABSTRACT
More informationHardware-accelerated regular expression matching with overlap handling on IBM PowerEN processor
Kubilay Atasu IBM Research Zurich 23 May 2013 Hardware-accelerated regular expression matching with overlap handling on IBM PowerEN processor Kubilay Atasu, Florian Doerfler, Jan van Lunteren, and Christoph
More informationHARDWARE-ACCELERATED REGULAR EXPRESSION MATCHING FOR HIGH-THROUGHPUT TEXT ANALYTICS
HARDWARE-ACCELERATED REGULAR EXPRESSION MATCHING FOR HIGH-THROUGHPUT TEXT ANALYTICS Kubilay Atasu, Raphael Polig, Christoph Hagleitner IBM Research - Zurich email: {kat,pol,hle}@zurich.ibm.com Frederick
More informationCompiling Text Analytics Queries to FPGAs
Compiling Text Analytics Queries to FPGAs Raphael Polig, Kubilay Atasu, Heiner Giefers IBM Research - Zurich Rueschlikon, Switzerland (pol, kat, hgi)@zurich.ibm.com Laura Chiticariu IBM Research - Almaden
More informationRegular Expression Acceleration at Multiple Tens of Gb/s
Regular Expression Acceleration at Multiple Tens of Gb/s Jan van Lunteren, Jon Rohrer, Kubilay Atasu, Christoph Hagleitner IBM Research, Zurich Research Laboratory 8803 Rüschlikon, Switzerland email: jvl@zurich.ibm.com
More informationLarge-scale Multi-flow Regular Expression Matching on FPGA*
212 IEEE 13th International Conference on High Performance Switching and Routing Large-scale Multi-flow Regular Expression Matching on FPGA* Yun Qu Ming Hsieh Dept. of Electrical Eng. University of Southern
More informationAutomation Framework for Large-Scale Regular Expression Matching on FPGA. Thilan Ganegedara, Yi-Hua E. Yang, Viktor K. Prasanna
Automation Framework for Large-Scale Regular Expression Matching on FPGA Thilan Ganegedara, Yi-Hua E. Yang, Viktor K. Prasanna Ming-Hsieh Department of Electrical Engineering University of Southern California
More information2068 (I) Attempt all questions.
2068 (I) 1. What do you mean by compiler? How source program analyzed? Explain in brief. 2. Discuss the role of symbol table in compiler design. 3. Convert the regular expression 0 + (1 + 0)* 00 first
More informationDesign Once with Design Compiler FPGA
Design Once with Design Compiler FPGA The Best Solution for ASIC Prototyping Synopsys Inc. Agenda Prototyping Challenges Design Compiler FPGA Overview Flexibility in Design Using DC FPGA and Altera Devices
More informationQuestion Bank. 10CS63:Compiler Design
Question Bank 10CS63:Compiler Design 1.Determine whether the following regular expressions define the same language? (ab)* and a*b* 2.List the properties of an operator grammar 3. Is macro processing a
More informationLeveraging the Intel HyperFlex FPGA Architecture in Intel Stratix 10 Devices to Achieve Maximum Power Reduction
white paper FPGA Leveraging the Intel HyperFlex FPGA Architecture in Intel Stratix 1 s to Achieve Maximum Reduction devices leverage the innovative Intel HyperFlex FPGA architecture to achieve power savings
More informationFPGA Implementation of Token-Based Clam AV Regex Virus Signatures with Early Detection
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735 PP 54-61 www.iosrjournals.org FPGA Implementation of Token-Based Clam AV Regex Virus Signatures
More informationVASim: An Open Virtual Automata Simulator for Automata Processing Research
University of Virginia Technical Report #CS2016-03 VASim: An Open Virtual Automata Simulator for Automata Processing Research J. Wadden 1, K. Skadron 1 We present VASim, an open, extensible virtual automata
More informationHardware Implementation for Scalable Lookahead Regular Expression Detection
Hardware Implementation for Scalable Lookahead Regular Expression Detection Masanori Bando, N. Sertac Artan, Nishit Mehta, Yi Guan, and H. Jonathan Chao Department of Electrical and Computer Engineering
More informationDynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers
Dynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers Young Hoon Kang, Taek-Jun Kwon, and Jeff Draper {youngkan, tjkwon, draper}@isi.edu University of Southern California
More informationEFFICIENT FAILURE PROCESSING ARCHITECTURE IN REGULAR EXPRESSION PROCESSOR
EFFICIENT FAILURE PROCESSING ARCHITECTURE IN REGULAR EXPRESSION PROCESSOR ABSTRACT SangKyun Yun Department of Computer and Telecom. Engineering, Yonsei University, Wonju, Korea skyun@yonsei.ac.kr Regular
More informationDeveloping Dynamic Profiling and Debugging Support in OpenCL for FPGAs
Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAs ABSTRACT Anshuman Verma Virginia Tech, Blacksburg, VA anshuman@vt.edu Skip Booth, Robbie King, James Coole, Andy Keep, John Marshall
More informationECE1387 Exercise 3: Using the LegUp High-level Synthesis Framework
ECE1387 Exercise 3: Using the LegUp High-level Synthesis Framework 1 Introduction and Motivation This lab will give you an overview of how to use the LegUp high-level synthesis framework. In LegUp, you
More informationHighly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs
Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs Chia-Tien Dan Lo and Yi-Gang Tai Department of Computer Science University of Texas at San Antonio {danlo,ytai}@cs.utsa.edu
More informationReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching
ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching Marco Paolieri, Ivano Bonesana ALaRI, Faculty of Informatics University of Lugano, Lugano, Switzerland {paolierm, bonesani}@alari.ch
More informationConfigurable String Matching Hardware for Speeding up Intrusion Detection
Configurable String Matching Hardware for Speeding up Intrusion Detection Monther Aldwairi, Thomas Conte, Paul Franzon Dec 6, 2004 North Carolina State University {mmaldwai, conte, paulf}@ncsu.edu www.ece.ncsu.edu/erl
More informationParallel graph traversal for FPGA
LETTER IEICE Electronics Express, Vol.11, No.7, 1 6 Parallel graph traversal for FPGA Shice Ni a), Yong Dou, Dan Zou, Rongchun Li, and Qiang Wang National Laboratory for Parallel and Distributed Processing,
More informationSYED AMMAL ENGINEERING COLLEGE (An ISO 9001:2008 Certified Institution) Dr. E.M. Abdullah Campus, Ramanathapuram
CS6660 COMPILER DESIGN Question Bank UNIT I-INTRODUCTION TO COMPILERS 1. Define compiler. 2. Differentiate compiler and interpreter. 3. What is a language processing system? 4. List four software tools
More informationComputer Science at Kent
Computer Science at Kent Regular expression matching with input compression and next state prediction. Gerald Tripp Technical Report No. 3-08 October 2008 Copyright 2008 University of Kent at Canterbury
More informationAutomata Computing. Mircea R. Stan UVA-ECE Center for Automata Processing (CAP) Co-Director Kevin Skadron, UVA-CS, CAP Director
Automata Computing Mircea R. Stan (mircea@virginia.edu), UVA-ECE Center for Automata Processing (CAP) Co-Director Kevin Skadron, UVA-CS, CAP Director 2013 Micron Technology, Inc. All rights reserved. Products
More informationImproving Signature Matching using Binary Decision Diagrams
Improving Signature Matching using Binary Decision Diagrams Liu Yang, Rezwana Karim, Vinod Ganapathy Rutgers University Randy Smith Sandia National Labs Signature matching in IDS Find instances of network
More informationFrequency Domain Acceleration of Convolutional Neural Networks on CPU-FPGA Shared Memory System
Frequency Domain Acceleration of Convolutional Neural Networks on CPU-FPGA Shared Memory System Chi Zhang, Viktor K Prasanna University of Southern California {zhan527, prasanna}@usc.edu fpga.usc.edu ACM
More informationAchieving Lightweight Multicast in Asynchronous Networks-on-Chip Using Local Speculation
Achieving Lightweight Multicast in Asynchronous Networks-on-Chip Using Local Speculation Kshitij Bhardwaj Dept. of Computer Science Columbia University Steven M. Nowick 2016 ACM/IEEE Design Automation
More informationLab 1: Using the LegUp High-level Synthesis Framework
Lab 1: Using the LegUp High-level Synthesis Framework 1 Introduction and Motivation This lab will give you an overview of how to use the LegUp high-level synthesis framework. In LegUp, you can compile
More informationAccelerating Pattern Searches with Hardware. Kevin Angstadt CS 6354: Graduate Architecture 7. April 2016
Accelerating Pattern Searches with Hardware Kevin Angstadt angstadt@virginia.edu CS 6354: raduate Architecture 7. April 2016 Who am I? Work with Wes Weimer and Kevin Skadron PL + Architecture Programming
More information! Readings! ! Room-level, on-chip! vs.!
1! 2! Suggested Readings!! Readings!! H&P: Chapter 7 especially 7.1-7.8!! (Over next 2 weeks)!! Introduction to Parallel Computing!! https://computing.llnl.gov/tutorials/parallel_comp/!! POSIX Threads
More informationINTRODUCTION TO FPGA ARCHITECTURE
3/3/25 INTRODUCTION TO FPGA ARCHITECTURE DIGITAL LOGIC DESIGN (BASIC TECHNIQUES) a b a y 2input Black Box y b Functional Schematic a b y a b y a b y 2 Truth Table (AND) Truth Table (OR) Truth Table (XOR)
More informationCentip3De: A 64-Core, 3D Stacked, Near-Threshold System
1 1 1 Centip3De: A 64-Core, 3D Stacked, Near-Threshold System Ronald G. Dreslinski David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman
More informationNETWORK INTRUSION DETECTION SYSTEMS ON FPGAS WITH ON-CHIP NETWORK INTERFACES
In Proceedings of International Workshop on Applied Reconfigurable Computing (ARC), Algarve, Portugal, February 2005. NETWORK INTRUSION DETECTION SYSTEMS ON FPGAS WITH ON-CHIP NETWORK INTERFACES Christopher
More informationRegular expression matching with input compression: a hardware design for use within network intrusion detection systems
J Comput Virol (27) 3:125 134 DOI 1.17/s11416-7-47-z EICAR 27 BEST ACADEMIC PAPERS Regular expression matching with input compression: a hardware design for use within network intrusion detection systems
More informationTPUTCACHE: HIGH-FREQUENCY, MULTI-WAY CACHE FOR HIGH-THROUGHPUT FPGA APPLICATIONS. Aaron Severance, Guy G.F. Lemieux
TPUTCACHE: HIGH-FREQUENCY, MULTI-WAY CACHE FOR HIGH-THROUGHPUT FPGA APPLICATIONS Aaron Severance, Guy G.F. Lemieux Department of Electrical and Computer Engineering University of British Columbia email:
More informationCenter Extreme Scale CS Research
Center Extreme Scale CS Research Center for Compressible Multiphase Turbulence University of Florida Sanjay Ranka Herman Lam Outline 10 6 10 7 10 8 10 9 cores Parallelization and UQ of Rocfun and CMT-Nek
More informationPL in the Broader Research Community
PL in the Broader Research Community EECS 590: Advanced Programming Languages 27. November 2017 Kevin Angstadt angstadt@umich.edu 1 Who am I? Fourth-year PhD student (I did my first three years at UVA)
More informationVendor Agnostic, High Performance, Double Precision Floating Point Division for FPGAs
Vendor Agnostic, High Performance, Double Precision Floating Point Division for FPGAs Xin Fang and Miriam Leeser Dept of Electrical and Computer Eng Northeastern University Boston, Massachusetts 02115
More informationRAPID Programming of Pattern-Recognition Processors
RAPID Programming of Pattern-Recognition Processors Kevin Angstadt Westley Weimer Kevin Skadron Department of Computer Science University of Virginia {angstadt, weimer, skadron}@cs.virginia.edu 6. April
More informationVisualizing Data Flow and Control Signaling Inside the Microprocessor
Visualizing Data Flow and Control Signaling Inside the Microprocessor Ms. Isha Sharma 1, Mrs. Neha Sharma 2, Mr. Jitender Chhabra 3 1 M.Tech. Scholar, SGTIET, Gurgaon. 2 Asst. Professor, SGTIET, Gurgaon
More informationScanners. Xiaokang Qiu Purdue University. August 24, ECE 468 Adapted from Kulkarni 2012
Scanners Xiaokang Qiu Purdue University ECE 468 Adapted from Kulkarni 2012 August 24, 2016 Scanners Sometimes called lexers Recall: scanners break input stream up into a set of tokens Identifiers, reserved
More informationNew Approach to Unstructured Data
Innovations in All-Flash Storage Deliver a New Approach to Unstructured Data Table of Contents Developing a new approach to unstructured data...2 Designing a new storage architecture...2 Understanding
More informationDelay Time Analysis of Reconfigurable. Firewall Unit
Delay Time Analysis of Reconfigurable Unit Tomoaki SATO C&C Systems Center, Hirosaki University Hirosaki 036-8561 Japan Phichet MOUNGNOUL Faculty of Engineering, King Mongkut's Institute of Technology
More informationImplementation Of Quadratic Rotation Decomposition Based Recursive Least Squares Algorithm
157 Implementation Of Quadratic Rotation Decomposition Based Recursive Least Squares Algorithm Manpreet Singh 1, Sandeep Singh Gill 2 1 University College of Engineering, Punjabi University, Patiala-India
More informationGujarat Technological University Sankalchand Patel College of Engineering, Visnagar B.E. Semester VII (CE) July-Nov Compiler Design (170701)
Gujarat Technological University Sankalchand Patel College of Engineering, Visnagar B.E. Semester VII (CE) July-Nov 2014 Compiler Design (170701) Question Bank / Assignment Unit 1: INTRODUCTION TO COMPILING
More informationPark Sung Chul. AE MentorGraphics Korea
PGA Design rom Concept to Silicon Park Sung Chul AE MentorGraphics Korea The Challenge of Complex Chip Design ASIC Complex Chip Design ASIC or FPGA? N FPGA Design FPGA Embedded Core? Y FPSoC Design Considerations
More informationLast lecture CMSC330. This lecture. Finite Automata: States. Finite Automata. Implementing Regular Expressions. Languages. Regular expressions
Last lecture CMSC330 Finite Automata Languages Sets of strings Operations on languages Regular expressions Constants Operators Precedence 1 2 Finite automata States Transitions Examples Types This lecture
More informationAdvanced VLSI Design Prof. Virendra K. Singh Department of Electrical Engineering Indian Institute of Technology Bombay
Advanced VLSI Design Prof. Virendra K. Singh Department of Electrical Engineering Indian Institute of Technology Bombay Lecture 40 VLSI Design Verification: An Introduction Hello. Welcome to the advance
More informationCSE450. Translation of Programming Languages. Lecture 20: Automata and Regular Expressions
CSE45 Translation of Programming Languages Lecture 2: Automata and Regular Expressions Finite Automata Regular Expression = Specification Finite Automata = Implementation A finite automaton consists of:
More informationAutomatic compilation framework for Bloom filter based intrusion detection
Automatic compilation framework for Bloom filter based intrusion detection Dinesh C Suresh, Zhi Guo*, Betul Buyukkurt and Walid A. Najjar Department of Computer Science and Engineering *Department of Electrical
More informationAn Operating System History of Operating Systems. Operating Systems. Autumn CS4023
Operating Systems Autumn 2017-2018 Outline 1 2 What is an Operating System? From the user s point of view an OS is: A program that acts as an intermediary between a user of a computer and the computer
More informationGeneral Overview of Compiler
General Overview of Compiler Compiler: - It is a complex program by which we convert any high level programming language (source code) into machine readable code. Interpreter: - It performs the same task
More information8. Remote System Upgrades with Stratix II and Stratix II GX Devices
8. Remote System Upgrades with Stratix II and Stratix II GX Devices SII52008-4.5 Introduction System designers today face difficult challenges such as shortened design cycles, evolving standards, and system
More informationComparing and Contrasting different Approaches of Code Generator(Enum,Map-Like,If-else,Graph)
Comparing and Contrasting different Approaches of Generator(Enum,Map-Like,If-else,Graph) Vivek Tripathi 1 Sandeep kumar Gonnade 2 Mtech Scholar 1 Asst.Professor 2 Department of Computer Science & Engineering,
More informationModular Multi-ported SRAMbased. Ameer M.S. Abdelhadi Guy G.F. Lemieux
Modular Multi-ported SRAMbased Memories Ameer M.S. Abdelhadi Guy G.F. Lemieux Multi-ported Memories: A Keystone for Parallel Computation! Enhance ILP for processors and accelerators, e.g. VLIW Processors
More informationA Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms
A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms Jingzhao Ou and Viktor K. Prasanna Department of Electrical Engineering, University of Southern California Los Angeles, California,
More informationRegular expression matching with input compression: a hardware design for use within network intrusion detection systems.
Regular expression matching with input compression: a hardware design for use within network intrusion detection systems. Gerald Tripp University of Kent About Author Gerald Tripp is a Lecturer in Computer
More informationMy First FPGA for Altera DE2-115 Board
My First FPGA for Altera DE2-115 Board 數位電路實驗 TA: 吳柏辰 Author: Trumen Outline Complete Your Verilog Design Assign The Device Add a PLL Megafunction Assign the Pins Create a Default TimeQuest SDC File Compile
More informationPerformance Issues and Query Optimization in Monet
Performance Issues and Query Optimization in Monet Stefan Manegold Stefan.Manegold@cwi.nl 1 Contents Modern Computer Architecture: CPU & Memory system Consequences for DBMS - Data structures: vertical
More informationDon t Forget Memories A Case Study Redesigning a Pattern Counting ASIC Circuit for FPGAs
Don t Forget Memories A Case Study Redesigning a Pattern Counting ASIC Circuit for FPGAs David Sheldon Department of Computer Science and Engineering, UC Riverside dsheldon@cs.ucr.edu Frank Vahid Department
More informationDesign of Adaptive Communication Channel Buffers for Low-Power Area- Efficient Network-on. on-chip Architecture
Design of Adaptive Communication Channel Buffers for Low-Power Area- Efficient Network-on on-chip Architecture Avinash Kodi, Ashwini Sarathy * and Ahmed Louri * Department of Electrical Engineering and
More informationCOE 561 Digital System Design & Synthesis Introduction
1 COE 561 Digital System Design & Synthesis Introduction Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Outline Course Topics Microelectronics Design
More informationUNIT III & IV. Bottom up parsing
UNIT III & IV Bottom up parsing 5.0 Introduction Given a grammar and a sentence belonging to that grammar, if we have to show that the given sentence belongs to the given grammar, there are two methods.
More informationFPGA Design, Implementation and Analysis of Trigonometric Generators using Radix 4 CORDIC Algorithm
International Journal of Microcircuits and Electronic. ISSN 0974-2204 Volume 4, Number 1 (2013), pp. 1-9 International Research Publication House http://www.irphouse.com FPGA Design, Implementation and
More informationCompiler Optimisation
Compiler Optimisation 1 Introductory Lecture Hugh Leather IF 1.18a hleather@inf.ed.ac.uk Institute for Computing Systems Architecture School of Informatics University of Edinburgh 2018 Textbooks Engineering
More informationTorben./Egidius Mogensen. Introduction. to Compiler Design. ^ Springer
Torben./Egidius Mogensen Introduction to Compiler Design ^ Springer Contents 1 Lexical Analysis 1 1.1 Regular Expressions 2 1.1.1 Shorthands 4 1.1.2 Examples 5 1.2 Nondeterministic Finite Automata 6 1.3
More informationInternational Journal of Scientific & Engineering Research, Volume 4, Issue 5, May-2013 ISSN
255 CORRECTIONS TO FAULT SECURE OF MAJORITY LOGIC DECODER AND DETECTOR FOR MEMORY APPLICATIONS Viji.D PG Scholar Embedded Systems Prist University, Thanjuvr - India Mr.T.Sathees Kumar AP/ECE Prist University,
More informationAN 831: Intel FPGA SDK for OpenCL
AN 831: Intel FPGA SDK for OpenCL Host Pipelined Multithread Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel FPGA SDK for OpenCL Host Pipelined Multithread...3 1.1
More informationAn FPGA Architecture Supporting Dynamically-Controlled Power Gating
An FPGA Architecture Supporting Dynamically-Controlled Power Gating Altera Corporation March 16 th, 2012 Assem Bsoul and Steve Wilton {absoul, stevew}@ece.ubc.ca System-on-Chip Research Group Department
More informationMonday, August 26, 13. Scanners
Scanners Scanners Sometimes called lexers Recall: scanners break input stream up into a set of tokens Identifiers, reserved words, literals, etc. What do we need to know? How do we define tokens? How can
More informationCS 432 Fall Mike Lam, Professor. Finite Automata Conversions and Lexing
CS 432 Fall 2017 Mike Lam, Professor Finite Automata Conversions and Lexing Finite Automata Key result: all of the following have the same expressive power (i.e., they all describe regular languages):
More informationNetworks-on-Chip Router: Configuration and Implementation
Networks-on-Chip : Configuration and Implementation Wen-Chung Tsai, Kuo-Chih Chu * 2 1 Department of Information and Communication Engineering, Chaoyang University of Technology, Taichung 413, Taiwan,
More informationTHE UNIVERSITY OF CHICAGO EFFCLIP + UAP: UNIFIED, EFFICIENT REPRESENTATION AND ARCHITECTURE FOR AUTOMATA PROCESSING A DISSERTATION SUBMITTED TO
THE UNIVERSITY OF CHICAGO EFFCLIP + UAP: UNIFIED, EFFICIENT REPRESENTATION AND ARCHITECTURE FOR AUTOMATA PROCESSING A DISSERTATION SUBMITTED TO THE FACULTY OF THE DIVISION OF THE PHYSICAL SCIENCES IN CANDIDACY
More informationWednesday, September 3, 14. Scanners
Scanners Scanners Sometimes called lexers Recall: scanners break input stream up into a set of tokens Identifiers, reserved words, literals, etc. What do we need to know? How do we define tokens? How can
More informationCS2 Practical 2 CS2Ah
CS2 Practical 2 Finite automata This practical is based on material in the language processing thread. The practical is made up of two parts. Part A consists of four paper and pencil exercises, designed
More informationLecture 5: Instruction Pipelining. Pipeline hazards. Sequential execution of an N-stage task: N Task 2
Lecture 5: Instruction Pipelining Basic concepts Pipeline hazards Branch handling and prediction Zebo Peng, IDA, LiTH Sequential execution of an N-stage task: 3 N Task 3 N Task Production time: N time
More informationSoftware Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors Francisco Barat, Murali Jayapala, Pieter Op de Beeck and Geert Deconinck K.U.Leuven, Belgium. {f-barat, j4murali}@ieee.org,
More informationMotivation for Parallelism. Motivation for Parallelism. ILP Example: Loop Unrolling. Types of Parallelism
Motivation for Parallelism Motivation for Parallelism The speed of an application is determined by more than just processor speed. speed Disk speed Network speed... Multiprocessors typically improve the
More informationHETEROGENEOUS SYSTEM ARCHITECTURE: PLATFORM FOR THE FUTURE
HETEROGENEOUS SYSTEM ARCHITECTURE: PLATFORM FOR THE FUTURE Haibo Xie, Ph.D. Chief HSA Evangelist AMD China OUTLINE: The Challenges with Computing Today Introducing Heterogeneous System Architecture (HSA)
More informationPower Efficient Solutions w/ FPGAs. Bill Jenkins Altera Sr. Product Specialist for Programming Language Solutions
1 Poer Efficient Solutions / FPGs Bill Jenkins ltera Sr. Product Specialist for Programming Language Solutions System Challenges CPU rchitecture is inefficient for most parallel computing applications
More informationIP Forwarding. CSU CS557, Spring 2018 Instructor: Lorenzo De Carli
IP Forwarding CSU CS557, Spring 2018 Instructor: Lorenzo De Carli 1 Sources George Varghese, Network Algorithmics, Morgan Kauffmann, December 2004 L. De Carli, Y. Pan, A. Kumar, C. Estan, K. Sankaralingam,
More informationCSE302: Compiler Design
CSE302: Compiler Design Instructor: Dr. Liang Cheng Department of Computer Science and Engineering P.C. Rossin College of Engineering & Applied Science Lehigh University March 20, 2007 Outline Recap LR(0)
More informationEnabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center
Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center Naif Tarafdar, Thomas Lin, Eric Fukuda, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow University of Toronto 1 Cloudy with
More informationThe Nios II Family of Configurable Soft-core Processors
The Nios II Family of Configurable Soft-core Processors James Ball August 16, 2005 2005 Altera Corporation Agenda Nios II Introduction Configuring your CPU FPGA vs. ASIC CPU Design Instruction Set Architecture
More informationCHAPTER 1 INTRODUCTION
1 CHAPTER 1 INTRODUCTION 1.1 Advance Encryption Standard (AES) Rijndael algorithm is symmetric block cipher that can process data blocks of 128 bits, using cipher keys with lengths of 128, 192, and 256
More informationHardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University
Hardware Design Environments Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Outline Welcome to COE 405 Digital System Design Design Domains and Levels of Abstractions Synthesis
More informationFPGAs Provide Reconfigurable DSP Solutions
FPGAs Provide Reconfigurable DSP Solutions Razak Mohammedali Product Marketing Engineer Altera Corporation DSP processors are widely used for implementing many DSP applications. Although DSP processors
More informationHigh-Speed NAND Flash
High-Speed NAND Flash Design Considerations to Maximize Performance Presented by: Robert Pierce Sr. Director, NAND Flash Denali Software, Inc. History of NAND Bandwidth Trend MB/s 20 60 80 100 200 The
More informationVerilog for High Performance
Verilog for High Performance Course Description This course provides all necessary theoretical and practical know-how to write synthesizable HDL code through Verilog standard language. The course goes
More informationReview. Pat Morin COMP 3002
Review Pat Morin COMP 3002 What is a Compiler A compiler translates from a source language S to a target language T while preserving the meaning of the input 2 Structure of a Compiler program text syntactic
More informationINSTITUTE OF AERONAUTICAL ENGINEERING
INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 00 043 INFORMATION TECHNOLOGY TUTORIAL QUESTION BANK Name AUTOMATA AND COMPILER DESIGN Code A03 Class III B. Tech I Semester Branch
More informationCS143 Handout 20 Summer 2011 July 15 th, 2011 CS143 Practice Midterm and Solution
CS143 Handout 20 Summer 2011 July 15 th, 2011 CS143 Practice Midterm and Solution Exam Facts Format Wednesday, July 20 th from 11:00 a.m. 1:00 p.m. in Gates B01 The exam is designed to take roughly 90
More informationALTDQ_DQS2 Megafunction User Guide
ALTDQ_DQS2 Megafunction ALTDQ_DQS2 Megafunction 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01089-2.2 Feedback Subscribe 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE,
More informationIntel Xeon with FPGA IP Asynchronous Core Cache Interface (CCI-P) Shim
Intel Xeon with FPGA IP Asynchronous Core Cache Interface (CCI-P) Shim AN-828 2017.10.02 Subscribe Send Feedback Contents Contents 1... 3 1.1 Conventions...3 1.2 Glossary...3 1.3 Introduction...3 1.4 Design...
More informationProgrammable Logic Devices FPGA Architectures II CMPE 415. Overview This set of notes introduces many of the features available in the FPGAs of today.
Overview This set of notes introduces many of the features available in the FPGAs of today. The majority use SRAM based configuration cells, which allows fast reconfiguation. Allows new design ideas to
More informationHigh-Performance Integer Factoring with Reconfigurable Devices
FPL 2010, Milan, August 31st September 2nd, 2010 High-Performance Integer Factoring with Reconfigurable Devices Ralf Zimmermann, Tim Güneysu, Christof Paar Horst Görtz Institute for IT-Security Ruhr-University
More informationUtilizing Parallelism of TMR to Enhance Power Efficiency of Reliable ASIC Designs
Utilizing Parallelism of TMR to Enhance Power Efficiency of Reliable ASIC Designs Hagen Sämrow, Claas Cornelius, Jakob Salzmann, Andreas Tockhorn, Dirk Timmermann 30/11/2010, Cairo Institute of Applied
More informationSupporting Multithreading in Configurable Soft Processor Cores
Supporting Multithreading in Configurable Soft Processor Cores Roger Moussali, Nabil Ghanem, and Mazen A. R. Saghir Department of Electrical and Computer Engineering American University of Beirut P.O.
More informationReconfigurable Multicore Server Processors for Low Power Operation
Reconfigurable Multicore Server Processors for Low Power Operation Ronald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor Mudge University of Michigan, Advanced Computer Architecture
More information