Utilizing Parallelism of TMR to Enhance Power Efficiency of Reliable ASIC Designs
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1 Utilizing Parallelism of TMR to Enhance Power Efficiency of Reliable ASIC Designs Hagen Sämrow, Claas Cornelius, Jakob Salzmann, Andreas Tockhorn, Dirk Timmermann 30/11/2010, Cairo Institute of Applied Microelectronics and Computer Engineering University of Rostock
2 Outline Motivation Power-efficient TMR approach Design idea Design structure Results Conclusion / Outlook 2
3 Motivation Power reduction for mobile applications Reliability suffers with every new technology and becomes more and more a concern of VLSI designers Redundancy traditional approach to enhance reliability At the cost of area and power consumption 3
4 Design Idea TMR Triple modular redundancy Three identical units Same input for every module Results are merged by a voting unit Threefold power consumption and area Parallelized data paths Reduced operating frequency and supply voltage Same throughput Larger design area Inherent parallel data paths of TMR Power reduction possible 4
5 Design idea NTMR operation mode Power efficient operation mode Every module executes the original function on different data sets Creation of a 3-fold parallel system f MODULEx = 1/3 f OPERATION mode mode Control Mux inputs outputs Functional Demux fault_out Demultiplexer Multiplexer CLK 5
6 Design idea TMR operation mode For error detection Usual TMR Same inputs for all modules mode mode Control inputs outputs Functional Demux Voter Error Detection fault_out Demultiplexer Multiplexer CLK 6
7 Design Structure mode inputs Control Functional Demux Demultiplexer 7
8 Design Structure Demultiplexer mode inputs Control Functional Demux Demultiplexer Assignment of the correct data inputs to the appropriate modules TMR mode Enabling all inputs concurrently f ORIGINAL NTMR mode Enabling the inputs of ONE module during a clock phase (disabling of the two other ones) 1/3 f ORIGINAL 8
9 Design Structure Multiplexer Assignment of the correct data output TMR mode Voting of the module outputs Voting result as design output NTMR mode The appropriate module output has to be routed to the design output Error detection during TMR mode XOR implementation + OR-tree Small amount of inherent reliability due to 3 XORs per output 9
10 Simulation Setup Industrial 65 nm technology Gate level simulation Toggle rate analysis for power calculation Stuck-at faults with randomly chosen locations (incl. periphery) Constant failure rate for every net of the system Area dependent system failure rate 10
11 Results Design overhead 1,25 1 0,75 0,5 0,25 0 Delay 1,25 1 0,75 0,5 0,25 0 Area 11 Normalized design parameters (in relation to conventional TMR) Normalized design parameters (in relation to conventional TMR) ISCAS Designs (from slow to fast) ISCAS Designs (from high to low [A/#output]) Lowest overhead for large and slower designs with few output bits
12 Results Reliability 1,0 0,8 Enhanced Enhanced TMR TMR conventional TMR Enhanced TMR (faultfree periphery) conventional TMR conventional TMR unprotected REF unprotected unprotected REF REF 0,6 R(t) 0,4 0,2 0, t in time steps c
13 Results MTTF improvements 0,8 0,6 MTTF improvements TMR TMR ENH 0,4 0,2 0 ISCAS Designs Larger designs suffer less from area overhead 13
14 Results Power consumption 1,2 Power Consumption (normalized to conventional TMR) 1 0,8 0,6 0,4 0, ,2 0,4 0,6 0,8 1 t TMR / t OPERATION c1908 c2670 c3540 c432 c5315 c6288 c7552 c499 REF 14
15 Results Switching Strategies Number of errors before detection t TMR / t OPERATION Duration of the TMR modein clk cycles Fast detection of faults in the module with Sufficient high t TMR / t OPERATION rate Sufficient long TMR mode duration possible low t TMR / t OPERATION rate 15
16 Conclusion / Outlook Lifetime reliability will be a major issue in ciruit design Design of an enhanced power-efficient TMR design using the inherent parallelism of TMR Power savings up to 50 % compared to conventional TMR are achievable with a slightly overhead in area, latency Further enhancements Reduced Supply voltage More reliable periphery Implementation of further operation modes 16
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