«Safe (hardware) design methodologies against fault attacks»
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1 «Safe (hardware) design methodologies against fault attacks» Bruno ROBISSON Assia TRIA SESAM Laboratory (joint R&D team CEA-LETI/EMSE), Centre Microélectronique de Provence Avenue des Anémones, Gardanne, France CEA Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA ROBISSON Bruno 10/10/2006 1
2 Introduction Securing today s devices Securing tomorrow s devices ROBISSON Bruno 10/10/2006 2
3 Integrated Circuit «Classical» Design Flow Specifications: Fonctionnality Simulation Virtual Power, Speed, Price - Synthesis Fabrication Modeling Technology: CMOS Real SOI Molecular Characterization ROBISSON Bruno 10/10/2006 3
4 Securing today s devices How to secure devices to known attacks? Simulation Syndroms Specifications: X - resistance Data - Retrieval Synthesis Fabrication? Technology Characterization DFA and DPA test benches ROBISSON Bruno 10/10/2006 4
5 Example: Securing AES against DFA Specifications: DFA-resistant DPA-resistant Commercial logic simulators ad hoc and commercial power estimation tools - Technology: CMOS Matlab Implementation of main DFA C Implementation of CPA/DPA Error detection via spatial duplication + Error spreading + Balancing Counter-measures validated Detecting sensitivity to round reduction attacks ROBISSON Bruno 10/10/2006 5
6 Securing today s devices : the challenges Specifications: X- resistance - Simulation Synthesis Fabrication Characterization Virtual NO realistic specifications Incomplete understanding Modeling Constant Enhance Real Few available CAD to be adapted ROBISSON Bruno 10/10/2006 6
7 Securing today s chip: Adressing the challenges Characterization Sharing equipments Publications should describe experimental protocols and equipments Towards an a minima standardization of security measurments (devoted to R&D s activities) Physics of attacks Modeling physical phenomena which make attacks possible (faults, EM) Dedicated test IC CAD tools to be adapted (simulation and synthesis) Simulators should support models dedicated to security Development of ad hoc verification tools (based on formal methods) Formalization of security constraints Towards automatic synthesis of circuits verifying such constraints Simulation Synthesis Fabrication Characterization ROBISSON Bruno 10/10/2006 7
8 Securing today s chip: Adressing the challenges Data retrieval Data base of physical signals (power and EM waveforms, faulty executions traces) Challenges from this data base to improve data retrieval algorithms Open library of optimized cryptographic primitives (DPA, DFA and cryptanalysis) sortie sbox cpa_2b cpa_ sortie sbox cpa_2b cpa_ sortie sbox cpa_2b cpa_ sortie sbox cpa_2b cpa_ Specifications Take care of «naive» countermeasures Take into account all the known attacks Always test counter-measures on real devices ROBISSON Bruno 10/10/2006 8
9 Securing tomorrow s devices Given an advanced technology : - Will it resist to existing attacks? - Will it lead to new attacks? Simulation Specifications Technology?- Synthesis Fabrication Characterization ROBISSON Bruno 10/10/2006 9
10 Example: QDI asynchronous circuit S S A S_ack B S Deadlock during second transfert «1» «0» Spacer (invalid) Valid Data S S Deadlock during first transfert Permanent «stuck-at zero» on a wire of a dual rail may induce deadlock Deadlock instants depend on the data values Deadlock instants may be easily detected by monitoring the power consumption ROBISSON Bruno 10/10/
11 DBA principles Safe-error Key bits leak only through the information whether the device has a normal behavior or not in presence of fault + DPA Correlating a power model parameterized by the value of a small number of bits of the key (the partial key) to power measurments Differential Behavioral Analysis Correlating a functional model parameterized by the value of a partial key to behaviors of the device in presence of faults ROBISSON Bruno 10/10/
12 DBA hypothesis DPA hypothesis Known cryptographic algorithms, Known plain texts (or cipher texts) There must exist intermediate variables that can be expressed as functions depending on the plain texts and on only a small number of key bits Fault injection Type : Stuck-at zero (or one) Location : On one bit in the set of the attack bits defined in DPA Duration : Permanent (or transient) Repetitivity : Same fault, at same time, on same bit Detecting behavior between faults which create an error during round one or during another round Deadlock during round 1 Deadlock during round 2 ROBISSON Bruno 10/10/
13 DBA on a QDI asynchronous DES DATA PATH Mux_3L HB DATA IP HB Expansion XOR48 HB SBOXES Xor32 Mux_3R HB HB CRYPT KEY counter KEY SCHEDULE PC1 Mux_K HB Shift-Reg DMux_K Design QDI asynchronous DES DPA counter-measures (logical balancing) Standard cells 0.13 μm STMicroelectronics 180 ns for DES encryption 0.94mm 2 with s IP -1 PC2 OUTPUT Faults injected on a bit at the output of the Sboxes 15 faulty executions with random values but known plain texts Simulation DBA Value of the partial key (6 bit long) Location of the faulty bit Value of the faulty bit Repetitivity of the fault injection ROBISSON Bruno 10/10/
14 Securing tomorrow s chip Evaluate advanced architectures Asynchronous circuits, GALS soft HW HW Reconfigurable devices HW soft RAM SOC, NOC Evaluate advanced technologies SOI Memories MRAM Technology shrinking Nano-technologies Above-IC power sources Smart packaging Anticipate attacker s means Equipments Towards hybrid attacks HW HW ROBISSON Bruno 10/10/ ROM
15 Conclusion A lot of work Towards a more collaborative approach Sharing some competences and equipments Objective comparison of counter-measures But with incorporate industrial constraints Fears and secrets around cryptographic developments Time and cost constraints CIMPACA/ Micro-Packs Gemalto, STMicrolectronics, Atmel, CEA LIRMM, ENST, ENSMSE, ROBISSON Bruno 10/10/
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