Ultra Depedable VLSI by Collaboration of Formal Verifications and Architectural Technologies

Transcription

1 Ultra Depedable VLSI by Collaboration of Formal Verifications and Architectural Technologies CREST-DVLSI - Fundamental Technologies for Dependable VLSI Systems - Masahiro Fujita Shuichi Sakai Masahiro Goshima Kenji Kise Kazutoshi Wakabayashi 2012/12/1 The University of Tokyo The University of Tokyo The University of Tokyo Tokyo Institute of Technology NEC principal investigator CREST-DVLSI

2 Research Map: Dependability Layers user interface software architecture circuit test design verification (1) Formal Verification Equivalence Checking Software Verifications by HW/SW Collaboration Collaborations of Bottom-up and Top-down Verification Synthesis, Verification and Optimization of Arithmetic Circuits Design Analysis and Support for Debugging (2) Testing / Recovery at Testing Easy-to-Test Design Support for Post-Silicon Verification and Debugging Patchable HW (3) Circuits Tolerating Timing Faults (4) Architectures Fault/Error Detection/Recovery 2 Research in each layer + Optimization among layers + Verification of the proposed architecture Best Effort Design Run Time Recovery FPGA with Permanent Error Recovery Mechanisms On Chip Multi-Function Routers Ultra Dependable Processor Ultra Dependable Many Cores (5) Formal Verification of Proposed Architectures (6) Opitimization of Dependability Layers

3 Formal Verification and Debugging of Equivalence checking for design refinements Developed a formal verifier, FLEC Under industrial evaluation with NEC Support for post-silicon verification and debug Developed Patchable HW VLSI C based design 11 Design library (Including modules for post-silicon debugging) Guarantee the total correctness of chip: Behaves as original C based designs Post-silicon support for verification and debug (Patchable HW) C based design 2 C based design n High level synthesis Manual optimization (Hardware insertion for post-silicon verification and debugging) RTL + Post-silicon debugging mechanism 3 Equivalence checking (block, core, chip)

4 Patchable HW for post-silicon verification and debug Insert redundancy/programmability in design time Use them if something wrong happens at post-silicon Bug Fix High-Level Tool sets are under Description development (available in March 2013) Bug Localization Verification/ Simulation Pre-Silicon High-Level Verification High-Level Synthesis of Patchable HW Logic Synthesis Place & Route Patchable SoC Design Error Detection Bug Localization No Bug Fix Respin Needed! Patch Compilation Post-Silicon High-Level ECO 4

5 FLEC in an industrial design environment Verify with FLEC Target: Reduction of verification time required to ensure correctness after incremental improvement Retargeting IPs designed for ASICs to FPGAs verified Design for ASIC Design for FPGA ASICs Performance improvement for FPGAs FPGAs Extreme long verification time is required to guarantee the same correctness as the original code even if using FLEC Verification TIme Computation time explosion for industrial-level circuits DES Number of branch statements in design Floating Point Arithmetic 5

6 Before Difference-based Hierarchical Verification Built a hierarchical verification framework for large C-descriptions and succeed to verify the design Extracting differences (code snippets) between designs Applying FLEC engine for the code snippets only int str_to_i(char str[10]) { int val = 0; for(int i=0;i<9;i++) { val += char_to_i(str[i]); val = val * 10 ; val += str[9];? == After int str_to_i(char str[10]) { int val = 0; for(int i=0;i<9;i++) { val += char_to_i(str[i]); int t = (val << 3); int u = (val << 1); val = t + u; val += str[9]; Extract difference Before int str_to_i(char str[10]) { int val = 0; for(int i=0;i<9;i++) { val += char_to_i(str[i]); val = uif(val) ; val += str[9]; int uif(int u) { int val ; val = val * 10 ; Equiv. == Equiv? == After int str_to_i(char str[10]) { int val = 0; for(int i=0;i<9;i++) { val += char_to_i(str[i]); val = uif(val) ; val += str[9]; int uif(int u) { int val ; int t =(val << 3); int u = (val << 1); val = t + u; 6 FLEC FLEC failed even after 3 days because the entire code verification is too large to be evaluated. FLEC FLEC succeeded within several seconds because extracted snippets are more easily evaluated

7 Circuit & Architecture Technologies: Transient- & Permanent-Fault-Tolerant FPGA 7 Basic Idea: Triple Modular Redundancy to detect faults Dynamic Partial Reconfiguration to replace faulty module with spare module Voter Copy Goal : One FPGA both for Normal and for Dependable Use Minimizing hardware overhead esp. in normal use Voters implemented as Hard-Wired Logic Reconfiguration Controller implemented in User Logic Voter Non-Stop Dynamic Reconfiguration when dynamically copy the contents of s from faulty module to spare module, the voter of another spare module is use to check successful completion Spare Module

8 Circuit & Architecture Technologies: Timing-Fault-Tolerant Circuit & Processor 8 Against Random Variation of LSIs Dynamic Timing Fault Detection & Recovery Clocking Scheme Enabling Dynamic Time Borrowing FPGA Board for Demonstration Combination of 2-Phase Latch System + Timing Fault Detection Clock Cycle is not determined by Worst- but by Typical-Case Delays Doubles the Max Clk Frequency Timing-Fault-Tolerant Processor Architecture New Configuration of Store Buffer in Commitment Pipeline Applicable to out-of-order superscalar processors

9 Circuit & Architecture Technologies: Plan to Yield Practical Applications 9 Fault-Tolerant FPGA Cooperation with Institute of Space and Astronautical Science (JAXA) NEC Space System Division / NEC Toshiba Space system Hitachi Research Laboratory Timing-Fault-Tolerant Circuit & Processor Discussion with LSI vendors Renesas Intel, AMD, ARM, etc... (plan)

10 Dependable and high performance many-core architecture 10 Development of on-chip multifunction routers supporting ultra dependability Designed multifunction router has 3 unique functions for Router-based DMR (Dual Modular Redundancy) and error detection packet duplication modification of packet destination packet level error detection Development of 180 FPGA prototyping system With realistic configurations, our HW system emulating a many-core processor is 129x faster than the SW simulator Development and evaluations of our task mapping method and the dependable mechanism for a many-nodes system normal task mapping RMAP Multifunction router Many-core prototyping system Task mapping method RMAP