ELECTROMAGNETIC FAULT INJECTION ON MICROCONTROLLERS
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1 ELECTROMAGNETIC FAULT INJECTION ON MICROCONTROLLERS Nicolas Moro 1,3, Amine Dehbaoui 2, Karine Heydemann 3, Bruno Robisson 1, Emmanuelle Encrenaz 3 1 CEA Commissariat à l Energie Atomique et aux Energies Alternatives 2 ENSM.SE Ecole Nationale Supérieure des Mines de Saint-Etienne 3 LIP6 - UPMC Laboratoire d Informatique de Paris 6 Université Pierre et Marie Curie PAGE 1
2 MOTIVATIONS Security of microcontroller-based embedded systems against fault injection attacks Target: ARM Cortex-M3 microcontroller Fault injection means: Pulsed electromagnetic fault injection Theoretical attacks rely on an attacker s fault model Electromagnetic fault injection is quite recent Very few in-depths studies of the effects on complex systems Better understanding of the effects of EM fault injection Detailed fault model at a register-transfer level 28 AOÛT 2013 Chip to Cloud 2013 Nice, France PAGE 2
3 OUTLINE I. Experimental setup II. General approach III. Study of the injection parameters IV. Register-transfer level fault model V. Conclusion Chip to Cloud 2013 Nice, France PAGE 3
4 FAULT INJECTION ATTACKS Perturbation M K C Comparison Faulty ciphertext Several physical ways to inject faults into a circuit s computation Necessary for an attacker to know the type of injected faults Fault target Fault type Granularity Determinism Temporal aspect Data, instructions Bit flip, reset at 0, set at 1, stuck Bit, byte, word Deterministic, metastable, random Single piece of data/instruction, multiple I Experimental AUGUST setup 28, 2013 Chip to Cloud 2013 Nice, France PAGE 4
5 EXPERIMENTAL SETUP Pulsed electromagnetic fault injection Transient and local effect of the fault injection Standard circuits not protected against this technique Solenoid used as an injection antenna Up to 200V sent on the injection antenna, pulses width longer than 10ns Microcontroller based on an ARM Cortex-M3 - Frequency 56 MHz -16/32 bits Thumb2 RISC instruction set - ARMv7-M modified Harvard architecture - SWD link to debug the microcontroller I Experimental 28 AOÛT setup 2013 Chip to Cloud 2013 Nice, France PAGE 5
6 DETAILED EXPERIMENTAL PROTOCOL Experiment driven by the computer Execution of a computation on the target device Sending of a voltage pulse Stop of the microcontroller Harvesting of the microcontroller s internal data Analysis of the obtained results Main experimental parameters Position of the injection antenna Electric parameters of the pulse Injection time of the pulse Executed code on the microcontroller I Experimental setup Chip to Cloud 2013 Nice, France PAGE 6
7 OUTLINE I. Experimental setup II. General approach III. Study of the injection parameters IV. Register-transfer level fault model V. Conclusion Chip to Cloud 2013 Nice, France PAGE 7
8 GENERAL APPROACH Exhaustive instruction simulation (finds instructions which could enable to reach B from A) Fault injection B Experimental fault (depends on the experimental parameters) Initial state A Instruction B Expected state Output pieces of data R0 to R12 R13 (SP) R14 (LR) R15 (PC) XPSR Result Detail General-purpose registers Stack pointer Link register Program counter Program Status Register - Flags - Details about the triggered interruptions - Details about the execution mode Memory address that contains the calculation s output II General 28 AOÛT approach 2013 Chip to Cloud 2013 Nice, France PAGE 8
9 SIMULATION OF A FAULT MODEL Instruction replacement simulation Experimental measurements Two lines are equal R0 to R12 + XPSR + result + SP + PC are equal II General 28 AOÛT approach 2013 Chip to Cloud 2013 Nice, France PAGE 9
10 OUTLINE I. Experimental setup II. General approach III. Study of the injection parameters IV. Register-transfer level fault model V. Conclusion Chip to Cloud 2013 Nice, France PAGE 10
11 INFLUENCE OF THE ANTENNA S POSITION Green : hardware interrupts have been triggered Red : faults on the output value have been obtained t = 0.4 ns t = 1 ns t = 2 ns t = 3.6 ns Frequency 56 MHz Pulse width 10 ns Pulse voltage 190V Period 17ns t = 16.8 t = 18.6 t = 19.2 ns t = 20 ns ns ns Target instruction : single LOAD instruction that loads 0x into R8 20 ns time interval, by steps of 200 ps - 3 mm square, by steps of 200 µm Variable increase of the Hamming weight of the loaded piece of data No fault on other registers than R8 (except for very few faults on R0) III Study of the injection parameters Chip to Cloud 2013 Nice, France PAGE 11
12 INFLUENCE OF THE INJECTION TIME Example of temporal cartography on an addition loop 0xfe 0xfd 0xfb 0xf7 0xef 0xdf 0xbf 0x7f Observations: One power of two has not been added BusFault or UsageFault interrupts Does our fault injection have an effect on the data flow or the control flow? Test program: loop to sum the elements of an array that contains eight powers of two 3.5 µs, by steps of 200 ps Expected result: 0xFF III Study of the injection parameters Chip to Cloud 2013 Nice, France PAGE 12
13 INFLUENCE OF THE PULSE S VOLTAGE LDR R4, PC#44 with 0x at the address PC#44 Pulse voltage Output value Occurrence rate 172V % 174V % 176V FE % 178V FFF % 180V FFFD % 182V FFFF 7F78 46 % 184V FFFF FFFB 40 % 186V FFFF FFFF 100 % Simulation : corresponds to no instruction replacement Looks like a set at 1 fault model on the Flash memory data transfers Possible precharge of the data bus on this architecture III Study 28 AOÛT of the injection 2013 parameters Chip to Cloud 2013 Nice, France PAGE 13
14 OUTLINE I. Experimental setup II. General approach III. Study of the injection parameters IV. Register-transfer level fault model V. Conclusion Chip to Cloud 2013 Nice, France PAGE 14
15 FAULTS ON THE CONTROL FLOW Experiments with a sequence of NOP (BF 00) Four kinds of faults Fault on R7 The program does not stop UsageFault exceptions (Invalid Instruction / No Coprocessor) Fault on R0 Sometimes a modification of the number of executed cycles Simulation on the ISA: some instructions can explain the results Some faults only equivalent to a STR R0, [R0, #0] instruction NOP - BF NOP - BF STR R0, [R0, #0] NOP - BF IV Register-transfer level fault model Chip to Cloud 2013 Nice, France PAGE 15
16 SEVERAL PHYSICAL POSSIBILITIES Direct coupling on the bus lines Unlikely: otherwise we could also inject faults on the address bus Coupling on the power grid or the ground network Likely: could slow down the transfers on the bus Coupling on the clock tree Possible: could provoke a shorter clock cycle Investigation of timing constraints violation as a fault injection means Loïc Zussa, Jean-Max Dutertre, Jessy Clédière, Bruno Robisson, Assia Tria 27th Conference on Design of Circuits and Integrated Systems (DCIS). Avignon IV Register-transfer level fault model Chip to Cloud 2013 Nice, France PAGE 16
17 INSTRUCTION FETCH Normal behaviour IV Register-transfer 28 AOÛT 2013 level fault model Chip to Cloud 2013 Nice, France PAGE 17
18 INSTRUCTION FETCH With an electromagnetic fault injection IV Register-transfer 28 AOÛT 2013 level fault model Chip to Cloud 2013 Nice, France PAGE 18
19 DATA LOAD FROM THE FLASH MEMORY Normal behaviour IV Register-transfer 28 AOÛT 2013 level fault model Chip to Cloud 2013 Nice, France PAGE 19
20 DATA LOAD FROM THE FLASH MEMORY With an electromagnetic fault injection IV Register-transfer 28 AOÛT 2013 level fault model Chip to Cloud 2013 Nice, France PAGE 20
21 INSTRUCTION SKIP EFFECTS Many instruction replacements have an effect which is equivalent to instruction skips In our experiments, up to 30% of successful fault injection lead to an instruction skip effect Balasch et al. (FDTC 2011) 50% on another platform Possible explanations ARM conditional execution? (unlikely on this architecture with the Thumb2 instruction set) Replacement by a useless instruction? (writing on a dead register, on a useless memory address) Re-execution of the previous instruction? (many instructions are idempotent) IV Register-transfer 28 AOÛT 2013 level fault model Chip to Cloud 2013 Nice, France PAGE 21
22 OVERVIEW OF THE DEFINED FAULT MODEL Possible to fault the transfers from the Flash memory Consequences regarding the instruction flow Instructions replacements Instruction skips under certain conditions (~ 20-30% of time) Some instructions may be more sensitive than others Some registers seem to be more sensitive than others Consequences regarding the data flow Corruption of the LOAD instructions from the Flash memory (encryption keys, ) Some metastability phenomena, but deterministic under some conditions Faulty values with higher Hamming weight (on this architecture) IV Register-transfer 28 AOÛT 2013 level fault model Chip to Cloud 2013 Nice, France PAGE 22
23 OUTLINE I. Experimental setup II. General approach III. Study of the injection parameters IV. Register-transfer level fault model V. Conclusion Chip to Cloud 2013 Nice, France PAGE 23
24 CONCLUSION AND PERSPECTIVES A first attempt of fault model for EM fault injection on a 32-bit µc Corruption of the transfers from the Flash memory on the buses The obtained effects seem very similar to the ones obtained with clock glitches or other fault injection means Similar effects obtained previously on a very different architecture (Atmel AVR ATmega128 8-bit microcontroller) Possibility to perform instruction skips under some specific conditions Perspectives Use more advanced debug techniques to understand better instruction replacements Define a higher-level fault model that can be used for theoretical attacks Conclusion 28 AOÛT 2013 Chip to Cloud 2013 Nice, France PAGE 24
25 THANK YOU FOR YOUR ATTENTION Any questions? Conclusion 28 AOÛT 2013 Chip to Cloud 2013 Nice, France PAGE 25
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