Intel I/O Processor

Transcription

1 Design Guide September 2002 Document Number:

2 Intel I/O Processor INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling or by visiting Intel's website at Copyright Intel, 2002 AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, icat, icomp, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel or its subsidiaries in the United States and other countries. *ARM and StrongARM are registered trademarks of ARM, Ltd. *Other names and brands may be claimed as the property of others. 2 Design Guide

3 Contents Contents 1 Introduction Features Terminology and Definitions Intel I/O Processor Package Ball Map By Function Signal List Routing Guidelines General Routing Guidelines Crosstalk EMI Considerations Power Distribution and Decoupling Decoupling Intel I/O Processor Decoupling DDR Decoupling PCI-X Decoupling Trace Impedance Printed Circuit Board (PCB) Methodology PCI/PCI-X Interface PCI/PCI-X Voltage Levels PCI/PCI-X Design Considerations IDSEL Lines PCI-X Initialization Clocking Modes Protection Circuitry for Add-in Cards PCI Arbitration Logic PCI General Layout Guidelines PCI Clock Layout Guidelines PCI-X Topology Layout Guidelines Single-Slot at 133 MHz Using the Intel I/O Processor at PCI-X 133 MHz PCI-X 133 MHz Add-in Cards Intel I/O Processor Embedded Application at 133 MHz Dual-Slot At 100 MHz Intel I/O Processor Applications Using PCI-X 100 MHz PCI-X 100MHz Add-in cards Embedded Intel I/O Processor Application at 100 MHz Quad-Slots at 66 MHz PCI-X 66 MHz Add-in Cards Embedded Intel I/O Processor Application at 66 MHz Intel I/O Processor Memory Interface DDR SDRAM Configurations Registered DDR (buffered) DIMM DDR SDRAM Initialization...61 Design Guide 3

4 Contents 7.3 DDR Signal Grouping DDR Bias Voltages DDR Layout Guidelines Source Synchronous Signal Group Routing Requirements Source Clocked and Command Clock Signal Groups Clocked Signal Group Source Clocked Signals Termination Routing Requirements for Chip Selects and CKE Lines DDR Signal Termination Discrete DDR Devices DDR Voltages Requirements DDR Termination Voltage V TT DDR Reference Voltage V REF Power-up Sequencing Power Failure Mode Non-Battery Backup Circuits Power Failure Sequence DDR Initialization MCU Configuration Registers Output Driver Programming Peripheral Local Bus Clock and Reset Signals Address/Data Signal Definitions Control/Status Signal Definitions Bus Arbitration HOLD/HOLDA Arbitration Overview Byte Ordering and Bus Accesses Layout Guidelines for the Peripheral Bus Flash Memory Support Programming the PBI FLASH Interface Layout Guidelines Voltage Power Delivery Power Delivery for the Intel I/O Processor Intel I/O Processor Core Supply Voltage Clocks Clocking Theory of Operation Clocking Region Clocking Region Clocking Region Clocking Region Output Clocks Interrupt Routing and GPIO Internal Interrupts External Interrupts Generating External PCI Interrupts From Internal Source General Purpose Input/Output Support General Purpose Inputs Design Guide

5 Contents General Purpose Outputs Reset Initialization of GPIO Function Terminations: Pull-down/Pull-ups Miscellaneous Signal Routing POR# Reference Board JTAG Circuitry for Debug Requirements JTAG Signals / Header System Requirements JTAG Hardware Requirements Macraigor Raven* and WindRiver Systems* visionprobe / visionice ARM* Multi-ICE* Debug Connectors and Logic Analyzer Connectivity Probing PCI-X Signals Probing DDR Memory Probing Other Intel I/O Processor Signals Design for Manufacturability Thermal Solutions Package Thermal Specifications Thermal Specifications Ambient Temperature Case Temperature Thermal Resistance Thermal Analysis References Related Documents Electronic Information A Intel Evaluation Platform Board Bill of Materials B Schematics Design Guide 5

6 Contents Figures lead PBGA Package (Top View) Lead PBGA Package (Bottom View) PBGA Mapped By Pin Function Examples of Stubless and Short Stub Traces Crosstalk Effects on Trace Distance and Height PCB Ground Layout Around Connectors Intel I/O Processor Decoupling Bottom View Intel I/O Processor Decoupling Top View Four-Layer Stackup Six-Layer Stackup Eight-Layer Stackup IDSEL Mapping PCI/PCI-X Add-In Card Protection Diodes PCI Clock Distribution and Matching Requirements Single-Slot Point-to-Point Topology Add-in Card PCI-X 133 MHz Configurations Intel I/O Processor Standalone application at 133 MHz Embedded Intel I/O Processor Design 133 MHz PCI-X Layout Dual-Slot Configuration Add-in Card PCI-X 100 MHz Configurations Embedded Intel I/O Processor Application at 100 MHz Embedded Intel I/O Processor Design 100 MHz PCI-X Layout Quad-Slots 66 MHz Topology Add-in Card PCI-X 66 MHz Configurations Intel I/O Processor Embedded 66 MHz Application Embedded Intel I/O Processor Wiring for 66 MHz Discrete Dual-Bank DDR SDRAM Memory Subsystem Buffered/Unbuffered DIMM SDRAM Memory Source Synchronous Length Matching Source Synchronous Routing Data Group Length Matching Trace Guidelines for Clocks Trace Length Requirements for Source Clocked Routing Matching Control Signals to the Clocks Routing Termination Resistors V Power Generation V TT Termination Voltage Generation Power Failure Comparator Circuit Power Delay Circuit SCKE Circuit Peripheral Bus Data Lines Four Load Topology Peripheral Bus Clock Buffer Single-Load Topology Peripheral Bus Clock Buffer Dual-Load Topology Four Megabyte Flash System VCCPLL Circuit Example V REF Circuit Voltage Island 1.3 V on GND Layer Voltage Island 1.3 V on Top Layer Multiple Voltage Islands on Internal Layer Design Guide

7 Contents 50 Intel I/O Processor Clock Generation Unit External Interrupt Routing on the Intel I/O Processor Internal Interrupt routing POR# Circuit Diagram Intel Evaluation Platform Board Form Factor Intel Evaluation Platform Board Block Diagram JTAG Header Pin Out JTAG Signals at Powerup JTAG Signals at Debug Startup Example Power-Up Circuit for ntrst Thermocouple Attachment - No Heatsink Design Guide 7

8 Contents Tables 1 Terminology and Definition Package Dimensions Pin Description Nomenclature Signal Description Nomenclature PCI Interface Signals PCI/PCI-X Voltage Levels PCI-X Clocking Modes Add-in Card Routing Parameters PCI-X Slot Guidelines Wiring Lengths for 133 MHz Slot Wiring Rules for Embedded 133 MHz Design Wiring Lengths for 100 MHz Dual-Slot Wiring Lengths for Embedded 100 MHz Design Wiring Lengths for 66 MHz Quad-Slot Wiring Lengths for Embedded 66 MHz Design Supported DDR SDRAM Configurations Grouping of DDR Signals DDR Bias voltages x64 DDR Memory Configuration x72 DDR Memory Configuration Source Synchronous Termination Requirements Source Synchronous Routing Recommendations Clocked Signal Group Termination Clock Signal Group Routing Requirements Source Clocked Signal Routing Source Clocked Signals Routing Guidelines Chip Select and CKE Termination CS and CKE Signal Routing Guidelines DDR Output Drive Strength Flash Wait State Profile Programming Terminations: Pull-up/Pull-down Reference Board Specification Logic Analyzer Pod Logic Analyzer Pod Logic Analyzer Pod Logic Analyzer Pod Logic Analyzer Pod Logic Analyzer Pod Lead PBGA Package Thermal Characteristics Design References Electronic Information Intel Related Documentation Bill of Materials Design Guide

9 Contents Revision History Date Revision Reason for Change September Minor text changes. June Updated Sections 7.4 and and added Section Updated Table 31 and Figures 36, 37, and39. Fixed Incorrect Data in Tables 4, 16, and18 and Sections 6.2.2, 7.6.1, and Added Missing Data in Table 18; Figure14; and Sections and 14.1 February Initial Release. Design Guide 9

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11 Introduction 1 This document provides layout information and guidelines for designing platform or add-in board applications with the Intel I/O processor with Intel XScale microarchitecture (ARM* architecture compliant). It is recommended that this document be used as a guideline. Intel recommends employing best-known design practices with board level simulation, signal integrity testing and validation for a robust design. Designers should note that this guide focuses upon specific design considerations for the Intel I/O processor (80321) and is not intended to be an all-inclusive list of all good design practices. Use this guide as a starting point and use empirical data to optimize your particular design. 1.1 Features The is a single-function device that integrates the Intel XScale core with a single-function PCI interface. The processor is able to run at a maximum core frequency of up to 600 MHz. Other intelligent peripherals integrated on the include: DMA Controller Address Translation Unit Performance Monitoring Unit DDR Memory Controller Synchronous Serial Port Unit Peripheral Bus Interface Messaging Unit Application Accelerator Unit I 2 O* Compatibility I 2 C Bus Interface Units The instruction cache is 32 KBytes in size and is 32-way set associative. Also, the core processor includes a 32 Kbyte, 32-way set associative data cache and a 2 Kbyte, 2-way set associative mini data cache. The also includes eight General Purpose I/O (GPIO) pins. Design Guide 11

12 Introduction 1.2 Terminology and Definitions Table 1. Terminology and Definition (Sheet 1 of 2) Term Definition Intel I/O processor Stripline StriplineinaPCBiscomposedofthe conductor inserted in a dielectric with GND planes to the top and bottom. NOTE: An easy way to distinguish stripline from microstrip is that you need to strip away layers of the board to view the trace on stripline. Microstrip Microstrip in a PCB is composed of the conductor on the top layer above the dielectric with a ground plane below Prepreg Core PCB DDR DIMM SD DS Source Synchronous DDR SSTL_2 JEDEC DLL Material used for the lamination process of manufacturing PCBs. It consists of a layer of epoxy material that is placed between two cores. This layer melts into epoxy when heated and forms around adjacent traces. Material used for the lamination process of manufacturing PCBs. This material is two sided laminate with copper on each side. The core is an internal layer that is etched. Printed circuit board. Layer 1: copper Example manufacturing process consists of Prepreg Layer 2: GND the following steps: Consists of alternating layers of core and Core prepreg stacked The finished PCB is heated and cured. Layer 3: V CC Prepreg The via holes are drilled Layer 4: copper Plating covers holes and outer surfaces Etching removes unwanted copper Board is tinned, coated with solder mask Example of a Four-Layer Stack and silk screened Double Data Rate Synchronous DRAM. Data is clocked on both rising and falling edges of the clock. Dual Inline Memory Module Single sided. Referring to memory chips on one side of the PCB. Double sided. Referring to memory chips on both sides of the PCB. For reads data leaves the DDR or memory controller with a data strobe. The memory controllerdelaysthedatastrobeinternallytolineitupwiththedatavalidwindow. For writes the memory controller places the data strobe in the middle of the data valid window to ensure that the correct data gets clocked into the DRAM. Series Stub Terminated Logic for 2.5 V Provides standards for the semiconductor industry. Delay Lock Loop - refers to the DDR feature used to provide appropriate strobe delay to clock in data. 12 Design Guide

13 Introduction Table 1. Terminology and Definition (Sheet 2 of 2) Term Definition A network that transmits a coupled signal to another network is aggressor network. Zo Zo Aggressor Zo Victim Network Zo Aggressor Network Victim Network Stub ISI CRB PC1600 PC2100 A network that receives a coupled cross-talk signal from another network is a called the victim network The trace of a PCB that completes an electrical connection between two or more components. Branch from a trunk terminating at the pad of an agent. Intersymbol Interference (ISI). This occurs when a transition that has not been completely dissipated, interferes with a signal being transmitted down a transmission line. ISI can impact both the timing and signal integrity. It is dependent on frequency, time delay of the line and the refection coefficient at the driver and receiver. Examples of ISI patterns that could be used in testing at the maximum allowable frequencies are the sequences shown below: Customer Reference Board JEDEC Names for DDR based on peak data rates. PC1600= clock of 100 MHz * 2 data words/clock * 8 bytes = 1600 MB/sec JEDEC Names for DDR based on peak data rates. PC2100= clock of 133 MHz * 2 data words/clock * 8 bytes = 2128 MB/sec Design Guide 13

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15 Package 2 The Intel I/O processor (80321) signals, are located on the PBGA package to simplify signal routing and system implementation. Figure 1 shows the top view of and Figure 2, shows the bottom view of the For detailed signal descriptions refer to the Intel I/O Processor Datasheet document. Contact your Intel sales representative to obtain a copy of this document. Figure lead PBGA Package (Top View) Pin A1Corner D D1 Pin A1 I.D. E1 E 45º Chamfer (4 places) TOP VIEW C A2 A 30º A1 SIDE VIEW Seating Plane -C- A Design Guide 15

16 Intel I/O Processor Package Table 2. Package Dimensions Symbol Minimum Nominal Maximum Units A mm A mm A mm D mm D mm E mm E mm e 1.27 (solder ball pitch) mm I 1.63 REF. mm J 1.63 REF. mm M 26 x 26 Matrix mm b mm c mm NOTES: 1. All dimensions and tolerances conform to ANSI Y Dimensions are measured at maximum solder ball diameter parallel to primary datum (-C-) 3. Primary Datum (-C-) and seating plane are defined by the spherical crowns of the solder balls. 16 Design Guide

17 Intel I/O Processor Package Figure Lead PBGA Package (Bottom View) Pin #1Corner 1 ø0.30 S C ø A S B S 1.63 REF A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF ø 1.0 (3 places) 1.63 REF 1.27 A Design Guide 17

18 Intel I/O Processor Package 2.1 Ball Map By Function Figure 3 shows the 544 BGA pins mapped by pin function. This diagram is helpful in placing components around the for the layout of a PCB. To simplify routing and minimize the number of cross traces, keep this layout in mind when placing components on your board. Name signals, by design, are located on the PBGA package to simplify signal routing and system implementation. Figure 3. PBGA Mapped By Pin Function A A B B C DDR Memory Interface C D D E E F F G G H J K Peripheral Bus Interface Bottom View H J K L L M M N N P P R R T T U U V V W Y GPIO W Y AA AB Serial Port AA AB AC AD AE Interrupts JTAG PCI Interface AC AD AE AF AF A Design Guide

19 Signal List 3 The signal list for the Intel I/O processor (80321) is provided as a reference. A complete list is also available in the Intel I/O Processor Datasheet. Table 3. Pin Description Nomenclature Symbol Description I O I/O OD Sync(...) Sync(P) Sync(M) Sync(PB) Sync(SS) Sync(T) Async Rst(P) Rst(M) Rst(T) Input pin only. Output pin only. Pin can be either an input or output. Open Drain pin. Synchronous. Signal meets timings relative to an input clock. Synchronous to P_CLK. Synchronous to M_CK[2:0]. Synchronous to PB_CLK. Synchronous to SSCKO. Synchronous to TCK. Asynchronous. Inputs may be asynchronous relative to all clocks. All asynchronous signals are level sensitive. The pin is reset with P_RST#. The pin is reset with M_RST#. The pin is reset with TRST#. Design Guide 19

20 Signal List Table 4. Signal Description Nomenclature (Sheet 1 of 4) Name Type Description RCVENI# RCVENO# M_CK[2:0] M_CK[2:0]# M_RST# SA[12:0] SBA[1:0] SRAS# SCAS# SWE# SCS[1:0]# SCKE[1:0] SCB[7:0] DQ[63:0] DQS[8:0] SDQM[8:0] V REF I O O O O Async O Sync(M) Rst(M) I/O Sync(M) Rst(M) O Sync(M) Rst(M) O Sync(M) Rst(M) O Sync(M) Rst(M) O Sync(M) Rst(M) O Sync(M) Rst(M) I/O Sync(M) Rst(M) I/O Sync(M) Rst(M) I/O Sync(M) Rst(M) O Sync(M) Rst(M) I RECEIVE ENABLE IN provides delay information for enabling the input receivers and must be connected to RCVENO# of the Intel I/O processor. RECEIVE ENABLE OUT - This pin must be connected to RCVENI# of the and be Trace Length Matched = Average Memory Clock Length + Average DQS Length. MEMORY CLOCKS areusedtoprovidethepositivedifferentialclocksto the external SDRAM memory subsystem. MEMORY CLOCKS areusedtoprovidethenegativedifferentialclocksto the external SDRAM memory subsystem. MEMORY RESET indicates when the memory subsystem has been reset with P_RST# or a software reset. MEMORY ADDRESS BUS carries the multiplexed row and column addresses to the SDRAM memory banks. For SA[10], See Note 1. SDRAM BANK ADDRESS indicates which of the SDRAM internal banks are read or written during the current transaction. See Note 1. SDRAM ROW ADDRESS STROBE indicates the presence of a valid row address on the Multiplexed Address Bus SA[12:0]. SeeNote1. SDRAM COLUMN ADDRESS STROBE indicates the presence of a valid column address on the Multiplexed address Bus SA[12:0]. See Note 1. SDRAM WRITE ENABLE indicates that the current memory transaction is a write operation. See Note 1. SDRAM CHIP SELECT enables the SDRAM devices for a memory access (Physical banks 0 and 1). See Note 1. SDRAM CLOCK ENABLE enables the clocks for the SDRAM memory. Deasserting places the SDRAM in self refresh mode. See Note 1. SDRAM ECC CHECK BITS carrythe8-bitecccodetoandfrom memory during data cycles. See Note 1. SDRAM DATA BUS carries 64-bit data to and from memory. During a data cycle, read or write data is present on one or more contiguous bytes. During write operations, unused pins are driven to determinate values. See Note 1. SDRAM DATA STROBES carry the strobe signals which are used to capture data on the data bus. See Note 1. SDRAM DATA MASK controls which bytes on the data bus should be written. When SDQM[8:0] is asserted, the SDRAM devices do not accept valid data from the byte lanes. See Note1. SDRAM VOLTAGE REFERENCE is used to supply the reference voltage to the differential inputs of the memory controller pins. 20 Design Guide

21 Signal List Table 4. Signal Description Nomenclature (Sheet 2 of 4) Name Type Description AD[31:0] A[3:2] BE[3:0]# ALE ADS# PB_CLK W/R# FWE# DEN# BLAST# I/O Sync(PB) Rst(M) O Sync(PB) Rst(PB) O Sync(PB) Rst(M) O Sync(PB) Rst(M) O Sync(PB) Rst(M) O O Sync(PB) Rst(PB) O Sync(PB) Rst(PB) O Sync(PB) Rst(PB) O Sync(PB) Rst(PB) ADDRESS / DATA BUS During an address cycle bits 31-2 contain the physical word address and bits 1-0 specify the number of data transfers during the bus transaction. 00= 1 Transfer 01= 2 Transfers 10= 3 Transfers 11= 4 Transfers During a data cycle bits 31-0, 15-0 or 7-0 contain valid data, depending on the corresponding -32, -16 or 8-bit bus width. During 16- and 8-bit bus write operations the unused bus pins are driven to determinate values. ADDRESS [3:2] carries a demultiplexed version of bits 3 and 2 of the address bus. During an address cycle A[3:2] matches AD[3:2]. Duringa bursted read or write data cycle A[3:2] represents the current DWORD address in the bursted transaction. BYTE ENABLES selectwhichofuptofourdatabytesonthebus participate in the current bus access. The byte enables are asserted during the address cycle. These signals do not toggle during a burst and they remain active through the last data cycle. Byte enable encoding is dependent on the bus width. ADDRESS LATCH ENABLE indicates the transfer of a physical address. The pin is asserted during the first address cycle and deasserted during the second address cycle. The pin floats whenever the bus is relinquished to an external device. ADDRESS STROBE indicates a valid address and the start of a new bus access. The pin is asserted during the second address cycle and deasserted during the first data cycle. The pin floats whenever the bus is relinquished to an external device. PERIPHERAL BUS CLOCK is the reference clock for all signals on the peripheral bus. WRITE / READ indicates whether the bus access is a write or a read with respect to the Intel I/O processor and is valid during the entire bus access. This pin can be used to control the OE# input on the flash ROM. The pin floats whenever the bus is relinquished to an external device. 0= read 1= write FLASH WRITE ENABLE indicates whether the bus access is a write or a read with respect to the and is valid during the entire bus access. This pin is used for flash memory accesses and controls the SWE# input on the ROM. The pin floats whenever the bus is relinquished to an external device. 0= write 1= read DATA ENABLE indicates data transfer cycles during a bus access. DEN# is asserted at the start of the first data cycle and deasserted at the end of the last data cycle. The pin is used to provide control for data transceivers connected to the bus. The pin floats whenever the bus is relinquished to an external device. BURST LAST indicates the last data transfer of a bus access. BLAST# remains active when wait states are inserted and becomes inactive after the final data transfer is complete. The pin floats whenever the bus is relinquished to an external device. Design Guide 21

22 Signal List Table 4. Signal Description Nomenclature (Sheet 3 of 4) Name Type Description RDYRCV# HOLD HOLDA PB_RST# I Sync(PB) I Sync(PB) O Sync(PB) Rst(M) O Async READY /RECOVER During a data cycle the pin indicates that data can be sampled or removed. 0= sampledata 1 = insert wait state During a recover state the pin indicates that the recover state is repeated. This function allows slow external devices longer to float their pins before the next address is driven. 0 = insert recovery state 1 = recovery complete HOLD is used by an external device to request access to the PBI bus. HOLD ACKNOWLEDGE indicates to an external device that it has been granted access to the PBI bus. PERIPHERAL BUS RESET indicates when the peripheral bus has been reset with P_RST# or a software reset. 22 Design Guide

23 Signal List Table 4. Signal Description Nomenclature (Sheet 4 of 4) Name Type Description PCE[5:0]# (Config. Pin) WIDTH[1:0] I/O Sync(PB) Rst(M) O Sync(PB) Rst(M) PERIPHERAL CHIP ENABLES specify which of the six memory address ranges are associated with the current bus access. The pin remains valid during the entire bus access. PERIPHERAL CHIP ENABLES PCE[5:0] are latched at the deasserting edge of P_RST# PCE[5:4] indicates the speed at which the PBI bus operates ranges are associated with the local bus [PBI100MHZ#, PBI66MHZ#] 11= 33 MHz, (default mode) 10 = 66 MHz, 01 = 100 MHz 00 = Undefined (Reserved - Do Not Use) PCE[3]/P_BOOT16#: PERIPHERAL BUS BOOT WIDTH 16 ENABLE specifies the width of the peripheral bus for flash accesses during boot up. 0 = 16-bit bus width 1 = 8-bit bus width (default mode) PCE[2]/32BITPCI#: 32-bit PCI is latched at the deasserting edge of P_RST# and it indicates the width of the PCI-X bus to the PCI-X Status Register (bit 16 of the PCI-X Status Register). 0 = 32-bit PCI-X Bus (Requires pull-down resistor) 1 = 64-bit PCI-X Bus (Default mode) PCE[1]/RETRY: is latched at the deasserting edge of P_RST# and it determines when the Primary PCI interface disables PCI configuration cycles by signaling a Retry until the Configuration Cycle Retry bit is clearedinthe PCI Configuration and Status Register. 0 = Configuration Cycles enabled (Requires pull-down resistor) 1 = Retry enabled (Default mode) PCE[0]#/RST_MODE#: RESET MODE is latched at the deasserting edge of P_RST# and it determines when the Intel I/O processor is held in reset until the Intel XScale core process or Reset bit is cleared in the PCI Configuration and Status Register. 0 = Hold in reset (Requires pull-down resistor) 1 = Don't hold in reset (Default mode) RST_MODE# RETRY Init. Mode 0 0 mode mode mode mode 3 default Primary PCI Interface accepts transaction retries all configuration transactions accepts transactions retries all configuration transactions Intel I/O Processor held in reset held in reset Initializes Initializes WIDTH denotes the physical memory attributes for a bus transaction. The pins float whenever the bus is relinquished to an external device. 00 = 8 Bits Wide 01 = 16 Bits Wide 10 = 32 Bits Wide 11 = Reserved Design Guide 23

24 Signal List Table 5. PCI Interface Signals (Sheet 1 of 3) Name Type Description P_AD[31:0] P_AD[63:32] P_PAR P_PAR64 P_C/BE[3:0]# P_C/BE[7:4]# P_REQ# P_REQ64# P_GNT# P_ACK64# P_FRAME# P_IRDY# P_TRDY# P_STOP# P_DEVSEL# P_SERR# P_CLK I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rs(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) O Rst(P) I/O Sync(P) Rst(P) I Sync(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O Sync(P) Rst(P) I/O OD Sync(P) Rst(P) I PCI ADDRESS/DATA is the multiplexed PCI address and bottom 32 bits of thedatabus. PCI DATA is the upper 32 bits of the PCI data bus driven during the data phase. PCI BUS PARITY is even parity across P_AD[31:0] and P_C/BE[3:0]#. PCI BUS UPPER DWORD PARITY is even parity across P_AD[63:32] and P_C/BE[7:4]#. PCI BUS COMMAND and BYTE ENABLES are multiplexed on the same PCI pins. During the address phase, they define the bus command. During the data phase, they are used as byte enables for P_AD[31:0]. PCI BUS BYTE ENABLES are as byte enables for P_AD[63:32] during the data phase. PCI BUS REQUEST indicates to the PCI bus arbiter that the Intel I/O processor desires use of the PCI bus. PCI BUS REQUEST 64-BIT TRANSFER indicates the attempt of a 64-bit transaction on the PCI bus. When the target is 64-bit capable, the target acknowledges the attempt with the assertion of P_ACK64#. PCI BUS GRANT indicates that access to the PCI bus has been granted. PCI BUS ACKNOWLEDGE 64-BIT TRANSFER indicates that the device has positively decoded its address as the target of the current access and the target is willing to transfer data using the full 64-bit data bus. PCI BUS CYCLE FRAME is asserted to indicate the beginning and duration of an access. PCI BUS INITIATOR READY indicates the initiating agent s ability to complete the current data phase of the transaction. During a write, it indicates that valid data is present on the Address/Data bus. During a read, it indicates the processor is ready to accept the data. PCI BUS TARGET READY indicates the target agent s ability to complete the current data phase of the transaction. During a read, it indicates that valid data is present on the Address/Data bus. During a write, it indicates the target is ready to accept the data. PCI BUS STOP indicates a request to stop the current transaction on the PCI bus. PCI BUS DEVICE SELECT is driven by a target agent that has successfully decoded the address. As an input, it indicates whether or not. PCI BUS SYSTEM ERROR is driven for address parity errors on the PCI bus. PCI BUS INPUT CLOCK provides the timing for all PCI transactions and is the clock source for most internal units. 24 Design Guide

25 Signal List Table 5. PCI Interface Signals (Sheet 2 of 3) Name Type Description P_RST# P_PERR# P_IDSEL P_INT[A:D]# I Async I/O Sync(P) Rst(P) Sync(P) OD Async Rst(P) RESET brings PCI-specific registers, sequencers, and signals to a consistent state. When P_RST# is asserted: PCI output signals are driven to a known consistent state. PCI bus interface output signals are three-stated. Open drain signals such as P_SERR# are floated. P_RST# may be asynchronous to P_CLK when asserted or deasserted. Although asynchronous, deassertion must be guaranteed to be a clean, bounce-free edge. PCI BUS PARITY ERROR is asserted when a data parity error occurs during a PCI bus transaction. PCI BUS INITIALIZATION DEVICE SELECT is used to select the Intel I/O processor during a Configuration Read or Write command on the PCI bus. PCI BUS INTERRUPT requests an interrupt. The assertion and deassertion of P_INT[A:D]# is asynchronous to P_CLK. A device asserts its P_INT[A:D]# line when requesting attention from its device driver. Once the P_INT[A:D]# signal is asserted, it remains asserted until the device driver clears the pending request. P_INT[A:D]# Interrupts are level sensitive. P_M66EN I 66 MHz ENABLE indicates the speed of the PCI bus. When this signal is sampled high the PCI bus speed is 66 MHz, when low the bus speed is 33 MHz. SSCKO O SERIAL PORT CLOCK OUT is the output bit rate clock. SFRM TXD RXD SSCKI XINT[3:0]# HPI# GPIO[3:0] GPIO[4] / SDA1 GPIO[5] / SCL1 O Sync(SS) Rst(M) O Sync(SS)/ Rst(M) I Sync(SS) I I Async I Async I/O Async Rst(P) I/O Async Rst(P) I/O OD Rst(M) I/O Async Rst(P) I/O OD Rst(M) SERIAL FRAME indicates the beginning and end of a serial data word. TRANSMIT DATA is the outbound serial data pin. RECEIVE DATA is the inbound serial data pin. SERIAL PORT CLOCK IN is the input bit rate clock which can be used when a frequency other than the default of MHz is needed. EXTERNAL INTERRUPT REQUESTS are used by external devices to request interrupt service. These pins are level detecting only and are internally synchronized. These interrupts can be directed to either the PCI pins P_INT[A:D]# or to the interrupt controller pins XINT[3:0]# as shown below. XINT[0]# -> P_INT[A]# or XINT[0]# XINT[1]# -> P_INT[B]# or XINT[1]# XINT[2]# -> P_INT[C]# or XINT[2]# XINT[3]# -> P_INT[D]# or XINT[3]# HIGH PRIORITY INTERRUPT causes a high priority nonmaskable interrupt to the This pin is level detecting only and is internally synchronized. GENERAL PURPOSE INPUT/OUTPUT. These pins can be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. GENERAL PURPOSE INPUT/OUTPUT. These pins can be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. I 2 C DATA is used for data transfer and arbitration on the I 2 C bus. This is one of two I 2 C buses that the user can enable. GENERAL PURPOSE INPUT/OUTPUT. These pins can be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. I 2 C CLOCK provides synchronous operation of the I 2 Cbus. This is one of two I 2 C buses that the user can enable. Design Guide 25

26 Signal List Table 5. PCI Interface Signals (Sheet 3 of 3) Name Type Description GPIO[6] / SDA0 GPIO[7] / SCL0 TCK TDI TDO TRST# TMS RCOMP PWRDELAY NC[2:1] I/O Async Rst(P) I/O OD Rst(M) I/O Async Rst(P) I/O OD Rst(M) I Rst(T) I Sync(T) Rst(T) O Sync(T) Rst(T) I Async Rst(T) I Sync(T) Rst(T) I I Async I GENERAL PURPOSE INPUT/OUTPUT. These pins can be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. I 2 C DATA is used for data transfer and arbitration on the I 2 C bus. This is one of two I 2 C buses that the user can enable. GENERAL PURPOSE INPUT/OUTPUT. These pins can be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. I 2 C CLOCK provides synchronous operation of the I 2 Cbus. This is one of two I 2 C buses that the user can enable. TEST CLOCK is an input which provides the clocking function for the IEEE Boundary Scan Testing (JTAG). State information and data are clocked into the component on the rising edge and data is clocked out of the component on the falling edge. TEST DATA INPUT is the serial input pin for the JTAG feature. TDI is sampled on the rising edge of TCK, during the SHIFTIR and SHIFT DR states of the Test Access Port. This signal has a weak internal pull-up to ensure proper operation when this signal is unconnected. TEST DATA OUTPUT is the serial output pin for the JTAG feature. TDO is driven on the falling edge of TCK during the SHIFT IR and SHIFT DR states of the Test Access Port. At other times, TDO floats. The behavior of TDO is independent of P_RST#. TEST RESET asynchronously resets the Test Access Port (TAP) controller function of IEEE Boundary Scan Testing (JTAG). This signal has a weak internal pull up. TEST MODE SELECT sampled at the rising edge of TCK to select the operation of the test logic for IEEE Boundary Scan testing. This signal has a weak internal pull up to ensure proper operation when this signal is unconnected. Register Compensation is connected through a 30.1 ohm 1% 1/4 W resistor to ground. This is used to minimize the PCI pin variations due to voltage and temperature variations. POWER FAIL DELAY is used with external delay circuits to delay the reset of the memory controller in a power fail condition. This allows the self refresh commandtobesenttotheddrsdramarray. NO CONNECT pins have no usable function. However, they are in the boundary scan chain and must not be connected to any signal, power or ground. V CCPLL1 I PLL POWER is a separate V CC13 supply ball for the phase lock loop clock generator. It is to be connected to the board V CC13 plane. In noisy environments, add a simple bypass filter circuit to reduce noise induced clock jitter and its effects on timing relationships. V CC33 I 3.3 V POWER balls to be connected to a 3.3 V powerboard plane. V CC25 I 2.5 V POWER balls to be connected to a 2.5 V powerboard plane. V CC13 I 1.3 V POWER balls to be connected to a 1.3 V powerboard plane. V SS I GROUND balls to be connected to a ground board plane. NOTE: These pins remain functional for 20 M_CK[2:0] periods after M_RST# is asserted for a warm boot. The designated Rst(M) state applies after 20 M_CK[2:0] periods after M_RST# is asserted. For more details, refer to the MCU Chapter in the Intel I/O Processor Developer s Manual. 26 Design Guide

27 Routing Guidelines 4 This chapter provides routing guidelines for layout and design of a printed circuit board using the Intel I/O processor (80321). The high speed clocking required when designing with the requires special attention to signal integrity. In fact it is highly recommended that the board design be simulated to determine optimum layout for signal integrity. The information in this chapter provides guidelines to aid the designer with board layout. Several factors influence the signal integrity of a design. These factors include: Power Distribution Minimizing Crosstalk Decoupling 100 MHz peripheral local bus 200 MHz DDR memory Layout considerations when connecting the to the PCI-X bus 4.1 General Routing Guidelines This section details general routing guidelines for connecting the The specific details on the layout of the PCI-X, 100 MHz peripheral local bus and the DDR memory interface are discussed in later sections. The order in which signals are routed varies from designer to designer. Some designers prefer to route all clock signals first, while others prefer to route all high speed bus signals first. Either order can be used, provided the guidelines listed here are followed. Route the address/data and control signals using a daisy chain topology. This topology assumes that no stubs are used to connect any devices on the net. Figure 4, shows two possible techniques to achieve a stubless trace. When it is not possible to apply one of these two techniques due to congestion, a very short stub is allowed - preferably not to exceed 250 mils. Note: A rule of the thumb for stub trace length is to make sure that the stub length is less than or equal to the one-quarter of the signal transition. Example: Nominal trace velocity To = 190 ps/in Typical signal slew rate = 2 V/ns Low-to-High Voltage differential (0.3 V CC to 0.5 V CC ) = 0.66 V Rise Time T R = 0.66 V *(1 ns/2 V) = 330 ps Equivalent Distance = 330 ps/to = 1.74 in Stub length < 1/4 of the length = 0.44 in Figure 4. Examples of Stubless and Short Stub Traces Stubless <250 Mils Short Stub A Design Guide 27

28 Routing Guidelines 4.2 Crosstalk Crosstalk is caused by capacitive and inductive coupling between signals. Crosstalk is composed of both backward and forward crosstalk components. Backward crosstalk creates an induced signal on victim network that propagates in the opposite direction of the aggressor signal. Forward crosstalk creates a signal that propagates in the same direction as the aggressor signal. Circuit board analysis software should be used to analyze your board layout for crosstalk problems. Examples of 2D analysis tools include Parasitic Parameters from ANSOFT * and XFS from Quad Design *. Crosstalk problems can occur when circuit etch lines run in parallel. When board analysis software is not available then the layout should maintain minimum spacing between parallel circuit signals lines: A general guideline to use is that space distance between adjacent signals should be a least of 3.3 times the distance from signal trace to the nearest return plane. The coupled noise between adjacent traces decreases by the square of the distance between the adjacent traces. It is also recommended to specify the height of the above the reference plane when laying out traces and provide this parameter to the PCB manufacturer. By moving traces closer to the nearest reference plane the coupled noise decreases by the square of the distance to the reference plane. Figure 5. Crosstalk Effects on Trace Distance and Height P Reduce Crosstalk: - Maximize P H aggressor victim Reference Plane - Minimize H A Avoid slots in the ground plane. Slots increases mutual inductance thus increasing crosstalk. Make sure that ground plane surrounding connector pin fields are not completely cleared out. When this area is completely cleared out around the connector pins all the return current must flow together around the pin field increasing crosstalk. The preferred method of laying out a connector in the GND layer is shown in Figure 6B. Figure 6. PCB Ground Layout Around Connectors Connector Connector Pins GND PCB Layer A. Incorrect method B. Correct method A Design Guide

29 Routing Guidelines 4.3 EMI Considerations It is highly recommended that good EMI design practices be followed when designing with the 80321: To minimize EMI on your PCB a useful technique is to not extend the power planes to the edge of the board. Another technique is to surround the perimeter of your PCB layers with a GND trace. This helps to shield the PCB with grounds minimizing radiation. The below link can provide some useful general EMI guidelines considerations: Power Distribution and Decoupling The power planes should have ample decoupling to ground to minimize the effects of the switching currents. The decoupling should consist of three types: the bulk, the high-frequency ceramic, and the inter-plane capacitors. Bulk capacitance consist of electrolytic or tantalum capacitors. These capacitors supply large reservoirs of charge but they are useful only at lower frequencies due to lead inductance effects. The bulk capacitors can be located anywhere on the board. For fast switching currents, high-frequency low-inductance capacitors are most effective. These capacitors should be placed as close to the device being decoupled as possible. This minimizes the parasitic resistance and inductance associated with board traces and vias. Use an inter-plane capacitor between power and ground planes to reduce the effective plane impedance at high frequencies. The general guideline for placing capacitors is to place high-frequency ceramic capacitors as close as possible to the module Decoupling The diagram below provides an example of how to place high frequency capacitors on the back (solder) side of the board. Inadequate high frequency decoupling results in intermittent and unreliable behavior. Review Section 7.4, DDR Layout Guidelines on page 64, for use of decoupling capacitors around the DDR memory. A general guideline recommends that you use the largest easily available capacitor in the lowest inductance package. Design Guide 29

30 Routing Guidelines Intel I/O Processor Decoupling The has three supply voltages V CC33, V CC25 and V CC13. V CC33 : The customer reference board, CRB deviates from the general guideline mentioned in the last section by using a combination of 0.01 µf and µf capacitors to achieve lower impedance values at higher frequencies. Simulation is recommended to determine whether using smaller capacitors than 0.1 µf capacitors yield better impedance at higher frequencies in your application. In summary the decoupling on the 3.3 V of this chip on the CRB include: 36, 0.01 µfcapacitors 10, µfcapacitor 6, 10 µfcapacitor V CC25 : the below capacitors were used to decouple the V CC25 rail on the CRB: 16, 0.1 µf capacitors 8, 10 µfcapacitors V CC13 : the below capacitors were used to decouple the V CC13 rail on the CRB: 12, 0.1 µf capacitors 3, 10 µfcapacitors Figure 7 shows the high frequency decoupling capacitors from the bottom of the board that surround the inside cavity of the processor. The caps without arrows are 0.1 µf. The 0.01 µf and µf capacitors are labeled. The larger capacitors on the left side of the package are the 10 µf capacitors used for low frequency decoupling. Figure 7. Intel I/O Processor Decoupling Bottom View 10 µf Capacitor 0.01 µf Capacitors µf Capacitors 10 µf Capacitor A Design Guide

31 Routing Guidelines Figure 8 shows the top view layout of the All the capacitors are 10 µf low frequency decoupling caps except for the third and fourth capacitors down from the top, along the left side of the chip. The third and fourth capacitors down from the top, along the left side of the chip are 4.7 µf and are used for the PLL circuit. Figure 8. Intel I/O Processor Decoupling Top View AF N Pin #1Corner A Notes: = 10 µf = 4.7 µf A Design Guide 31

32 Routing Guidelines DDR Decoupling The DDR voltages consist of V DD2.5, V DDQ2.5, V TT,andV REF. Refer also to the DDR section provides more details on decoupling and layout of the DDR voltages. V DD2.5 rail: The below capacitors were used to decouple the DDR V DD2.5 rail on the CRB. 16, 0.1 µfcapacitors 8, 10 µf capacitors V DDQ2.5 V rail: The below capacitors were used to decouple the DDR V DDQ2.5 Vrailonthe CRB. 24, 0.1 µfcapacitors 4, 10 µf capacitors V TT : As a guideline for decoupling capacitors, a conservative recommendation is to have approximately one decoupling capacitor for every two V TT voltage ground pairs. The below capacitors were used to decouple the DDR V TT rail on the CRB. 32, 0.1 µfcapacitors 8, 10 µf capacitor V REF : The V REF voltage is low current. The circuit for V REF is shown in Figure 47. This circuit should be placed close to the DDR DIMM module or DDR SDRAM chips. On the CRB eight additional 0.1 µf decoupling capacitors were used with the capacitors shown in Figure PCI-X Decoupling The PCI-X interface uses the 3.3 V rail. The guidelines for PCI-X decoupling are included in the Section The number of 3.3 V balls dedicated to the PCI-X interface in is Design Guide

33 Routing Guidelines 4.5 Trace Impedance All signal layers require controlled impedance of 60 Ω +/- 10% microstrip or stripline where appropriate unless otherwise specified. Selecting the appropriate board stack-up to minimize impedance variations is very important. When calculating flight times, it is important to consider the minimum and maximum trace impedance based on the switching neighboring traces. Wider spaces between traces may be used since this can minimize trace-to-trace coupling, and reduce cross talk. All recommendations, described in this document assume a T wid 5mil60Ω signal trace unless otherwise specified. When a different stack up is used the trace widths must be adjusted appropriately. When wider traces are used, the trace spacing must be adjusted accordingly (linearly). It is highly recommended that a 2D Field Solver be used to design the high-speed traces. The following Impedance Calculator URLs provide approximations for the trace impedance of various topologies. They may be used to generate the starting point for a full 2D Field solver. The following website link provides a useful basic guideline for calculating trace parameters: Note: Using stripline transmission lines may give better results than microstrip. This due to the difficulty of precisely controlling the dielectric constant of the solder mask, and the difficulty in limiting the plated thickness of microstrip conductors, which can substantially increase cross-talk. Design Guide 33

34 Routing Guidelines This Page Intentionally Left Blank 34 Design Guide

35 Printed Circuit Board (PCB) Methodology 5 This section provides a recommended guidelines for board stackup. These guidelines are provided as a reference for a four layer, six layer and eight layer board. For stripline (signals between planes) the stackup should be such that the signal line is closer to one of the planes by a factor of five or more. Then the trace impedance is controlled predominantly by the distance to the nearest plane. Figure 9. Four-Layer Stackup Layer 0 Layer 1 Layer 2 Layer 3 Signal Prepreg V SS Thick Core VDC Prepreg Signal A Figure 10. Six-Layer Stackup Layer 0 Layer 1 Signal Prepreg V SS Layer 2 Layer 3 Signal Core Signal Layer 4 Layer 5 VDC Prepreg Signal A Note: Signals on Layers two and layers three should be orthogonal to minimize crosstalk. Design Guide 35

36 Printed Circuit Board (PCB) Methodology Figure 11. Eight-Layer Stackup Layer 0 Layer 1 Layer 2 Layer 3 Layer 4 Layer 5 Layer 6 Layer 7 Signal Prepreg V SS Core Signal Thick Prepreg Signal or Flood Plane Core V SS Thick Prepreg Signal Core VDC Prepreg Signal A Note: Signals on Layers two and layers three should be orthogonal to minimize crosstalk. 36 Design Guide

37 PCI/PCI-X Interface 6 This section provides guidelines for designing with the Intel I/O processor (80321) PCI/PCI-X bus interface in your application. This chapter is divided as follows: PCI/PCI-X voltage levels. PCI/PCI-X considerations. Clocking Modes. General Layout Guidelines. Layout Guidelines for the different slot and embedded configurations. 6.1 PCI/PCI-X Voltage Levels The does not support a 5 V PCI signaling interface, it supports 3.3V only. Supporting a 5 V PCI interface would require additional I/O level translation circuitry. Table 6 is provided as a reference for the PCI/PCI-X signaling levels. A complete PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a can be found on the website. Table 6. PCI/PCI-X Voltage Levels Symbol Parameter Minimum Maximum Units V IL3 Input Low Voltage (PCI-X) V CC33 Voltage V IH3 Input High Voltage (PCI-X/PCI) 0.5V CC33 V CC V Voltage V IL4 Input Low Voltage (PCI) V CC33 Voltage V OL3 Output Low Voltage (PCI-X) 0.1V CC33 Voltage V OH3 Output HIGH Voltage (PCI-X) 0.9V CC33 Voltage Design Guide 37

38 PCI/PCI-X Interface 6.2 PCI/PCI-X Design Considerations This chapter describes several factors that should be considered with a PCI/PCI-X design. These include the IDSEL lines (Section 6.2.1), the PCI-X initialization pattern (Section 6.2.2), add-in card protection circuitry (Section 6.2.3) and arbitration logic (Section 6.2.4) IDSEL Lines The IDSEL lines acts as chip selects during the configuration cycles. Configuration cycles allow read and write access to one of the device configuration space registers. As in PCI the IDSEL lines can be mapped to upper address lines which are unused during the configuration cycles. Figure 12 provides an example of used as an embedded controller connected to four PCI devices. Note that AD16 typically is reserved for a PCI/PCI-X bridge. Figure 12. IDSEL Mapping Intel Network Processor PCI-X Bus AD17 AD18 AD19 AD20 IDSEL IDSEL IDSEL IDSEL Device 1 Device 2 Device 3 Device 4 A The IDSEL lines for PCI-X can be terminated with a nominal 2 KΩ resistor value. PCI specification does not recommend a specific resistor value. However, 2 KΩ resistor, or a smaller value may be used as long as system analysis guarantees that timing and noise budgets for the AD bit are met. On the CRB a 500 ohm resistor value was used. 38 Design Guide

39 PCI/PCI-X Interface PCI-X Initialization Clocking Modes The clocking modes for PCI-X and PCI bus are shown in Table 7. At PCI bus reset, the samples the P_FRAME#, P_IRDY#, P_TRDY#, P_STOP#, andp_devsel# to determine the operating frequency for PCI-X mode. When P_FRAME# is deasserted and P_IRDY# is deasserted (i.e., the bus is idle) and one or more of P_DEVSEL#, P_STOP#, and P_TRDY# are asserted at the rising edge of P_RST#, the device enters PCI-X mode (see Table 7). Otherwise the device enters conventional PCI mode. With conventional PCI mode, a low on P_M66EN determines the PCI bus is at 33 MHz. Table 7. Note: When the is used in as the host processor in an embedded application without a PCI-X bridge the initialization logic must be added to signal the correct PCI-X clock mode. This is described in more detail in Intel I/O Processor Initialization White Paper (273698). PCI-X Clocking Modes Mode/Clock PCIXCAP P_M66EN P_DEVSEL# P_STOP# P_TRDY# PCI/33 MHz GND Deasserted Deasserted Deasserted Deasserted PCI/66 MHz GND Asserted Deasserted Deasserted Deasserted PCI-X/66 MHz 10 KΩ, 0.01µF cap to GND N/A Deasserted Deasserted Asserted PCI-X/100 MHz 0.01µF cap to GND N/A Deasserted Asserted Deasserted PCI-X/133 MHz 0.01µF cap to GND N/A Deasserted Asserted Asserted Design Guide 39

40 PCI/PCI-X Interface Protection Circuitry for Add-in Cards Add-in cards designed for 3.3 V may still need to provide protection circuitry on the interrupt lines to prevent damaging the This is important in the case where the add-in card is plugging into a motherboard that has its interrupt lines INTA#, INTB#, INTC# and INTD# tied to 5 V. To prevent potential damage it is recommended that Schottky diodes be added to protect the input buffers as shown in Figure 13 below. Schottky diodes are used because of the 0.3 V forward bias voltage. As a safety precaution these diodes should be added on all based PCI/PCI-X add-in cards. Figure 13. PCI/PCI-X Add-In Card Protection Diodes PCI/PCI-X Add-In Card Intel I/O Processor 3.3 V 5 V P_IntA# P_IntB# P_IntC# P_IntD# 3.3 V PCI/PCI-X Slot INTA# INTB# INTC# INTD# Motherboard A PCI Arbitration Logic Additional arbitration logic maybe necessary when the embedded application uses the as the central controller, without a PCI bridge or any device implementing arbitration. Refer to the PCI Local Bus Specification, Revision 2.2, for more information on arbiter algorithms. The specification essentially states that the algorithm should be fair to prevent any one device from consuming to much of the PCI bandwidth. A typical implementation of the arbitration logic is a two-level rotating round robin configuration. A high priority status is assigned to a master request in level one and a low-level priority status is assigned to a master request in level two. The arbiter checks each of the REQ# lines in the first level. When none are asserted it traverses to checking level two. Once the GNT# has been asserted to a master, this master has the lowest priority in its level. The arbiter usually also conducts bus parking by driving A/D, C/BE# and PAR lines to a known value while the bus is idle. The arbiter typically leaves the GNT# asserted to the master that used the bus last. 40 Design Guide

41 PCI/PCI-X Interface 6.3 PCI General Layout Guidelines For acceptable signal integrity with bus speeds up to 133 MHz it is important to PCB design layout to have controlled impedance. Signal traces should have an unloaded impedance of 60 +/- 10% Ω. Signal trace velocity should be roughly ps/inch The below list provides general guidelines which should be used when routing your PCI bus signals: Avoid routing signals > 8. All clock nets must be on the top layer. All 32-bit interface signals from the PCI edge fingers must be no longer than 1.5 and no shorter than All 64-bit extension signal from the PCI edge fingers must be no longer than 2.75 and no shorter than P_CLK from the PCI edge finger must be 2.5 +/ P_RST# from the PCI edge finger must be no longer than 3.0 and no shorter than The following signals have no length restrictions: INTA#, INTB#, INTC#, INTD#, TCK, TDI, TDO, TMS and TRST# Table 8 provides information on maximum lengths for routing add-on card signals. Table 8. Add-in Card Routing Parameters Parameter Minimum PCI-X Maximum P_CLK P_AD[0 31] P_AD[32 63] P_RST# Note: Do not use more than one via for the primary PCI bus signals. Design Guide 41

42 PCI/PCI-X Interface PCI Clock Layout Guidelines The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, allows a maximum of 0.5 ns clock skew timing for each of the PCI-X frequencies: 66 MHz, 100 MHz and 133 MHz. A typical PCI-X application may require separate clock point-to-point connections distributed to each PCI device. Using a low skew clock buffer helps to meet the maximum clock skew requirements. The clock buffer also provides clock fanout to multiple PCI-X devices. The Figure 14 shows the use of a skew limited clock buffer with four clock outputs and length matching requirements. The recommended clock buffer layout are specified as follows: Match each of the PCI clock buffers lengths to within 0.1 to help keep the timing within the 0.5 ns maximum budget. Use a skew-limited clock buffer with a tight output-to-output skew specification. Keep the distance between the clock lines and other signals d at least 25 mils from each other. Keep the distance between the clock line and itself a at a minimum of 25 mils apart (for serpentine clock layout). Figure 14. PCI Clock Distribution and Matching Requirements P_CLK a X0 PCI Device 1 Low Skew Clock Buffer P_CLK0 P_CLK1 P_CLK2 P_CLK3 d X1 X2 PCI Device 2 PCI Device 3 PCI Bus X3 Intel I/O Processor Notes: PCI Clock lengths X0, X1, X2, X3 should be matched within 0.1inch of each other. Minimum separation between two different P_CLKs, "d" = 25 mils. Minimum separation between two segments of the same P_CLK line, "a" = 25 mils. A Total length of P_CLK for an add-in card is Total length of P_CLK in non add-in card design is < Design Guide

43 PCI/PCI-X Interface 6.4 PCI-X Topology Layout Guidelines The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, recommends the following guidelines for the number of loads for your PCI-X designs. Any deviation from these maximum values requires close attention to layout with regard to loading and trace lengths. Table 9. PCI-X Slot Guidelines Frequency Maximum Loads Maximum Number of Slots 66 MHz MHz MHz 2 1 The following PCI-X design layout considerations were compiled from the white paper Design, Modeling and Simulation Methodology for High Frequency PCI-X Subsystems available on the website. The following results were compiled from the simulation of system models that included system board and add-in cards for different slot configurations and bus speeds. This simulation addressed the signal integrity issues including reflective noise, cross-talk noise, overshoot/undershoot voltage, ring-back voltage, settling time, inter-symbol interference, input reference voltage offset and ground bounce effects. These results for the slot configurations met the required PCI-X timing characteristics and were within appropriate noise margins. Note that several of the figures show the use of a FET as hot-plug switch. These FETs can be removed when not applicable with the net effect of subtracting out an additional delay equivalent to about 0.5 inches of trace. Design Guide 43

44 PCI/PCI-X Interface Single-Slot at 133 MHz Figure 15 shows one of the chipset PCI AD lines connected through W1 and W12 line segments to a single-slot connector through W13 line segment to the This AD line is also used as an IDSEL line from line segment W14 to a 2K resistor through W15 to the PCI connector. The other end of the PCI connector IDSEL line connects through W16 to IDSEL line input buffer. Figure 15. Single-Slot Point-to-Point Topology W1 2 W11 W12 12 W13 Host W14 2K W PCI Connector W Slot 1 A Stublengths are represented by W#s. Table 10. Wiring Lengths for 133 MHz Slot Lower AD Bus Upper AD Bus Segment Units Minimum Length Maximum Length Minimum Length Maximum Length W inches W inches W inches W Note N/A N/A inches W15 Note 0.6 N/A N/A inches W N/A N/A inches NOTE: : W14, W15 and W16 represent the IDSEL line. W14 and W15 <= Using the Intel I/O Processor at PCI-X 133 MHz This section describes applications that use with the PCI-X bus running at 133 MHz. These applications include PCI-X add-in cards as well as standalone applications. As mentioned in the Table 9 the maximum PCI-X loads at 133 MHz is two. It is recommended that board simulation, and careful attention to layout be followed in order to achieve 133 MHz bus speeds PCI-X 133 MHz Add-in Cards Figure 16 shows two PCI-X add-in card configurations, one with an IBM * PCI-X bridge and one without the bridge. The IQ80321 Customer Reference board uses an IBM PCI-X to PCI-X Bridge part number IBM21P100. This bridge connects to and a Gigabit Ethernet Intel 82544EI controller (refer to Chapter 12 for more information about the IQ80321). The host bridge in Figure 16 is capable of driving a single slot at 133 MHz representing two electrical loads. The connector represents a single load and the bridge represents a single load. 44 Design Guide

45 PCI/PCI-X Interface Figure 16. Add-in Card PCI-X 133 MHz Configurations A Intel Add-in Card 1 load 1 load PCI-X Bus Intel I/O Processor PCI-X Bus Host Bridge CPU Motherboard Intel Add-in card configuration without a PCI-X Bridge B Intel I/O Processor 1 Load Intel Add-in Card PCI-X Bus PCI-X Chip 1 Load 1 load 1 load PCI-X Bus IBM PCI-X Bridge PCI-X Bus Host Bridge CPU Motherboard Intel Add-in card configuration with a PCI-X Bridge A Design Guide 45

46 PCI/PCI-X Interface Intel I/O Processor Embedded Application at 133 MHz Figure 17 shows application in a standalone embedded application. In this application the can drive a single load for a total of two loads. Figure 18 shows the PCI-X layout for an embedded 133 MHz design and Table 11 shows the corresponding wiring rules. Figure 17. Intel I/O Processor Standalone application at 133 MHz Intel Standalone Application Intel Add-in Card Intel I/O Processor PCI-X Chip 1 load PCI-X Bus 1 load A Table 11. Wiring Rules for Embedded 133 MHz Design Segment Lower AD Bus Upper AD Bus Minimum Length Maximum Length Minimum Length Maximum Length Units W inches W N/A N/A inches W N/A N/A inches Figure 18. Embedded Intel I/O Processor Design 133 MHz PCI-X Layout W1 Intel I/O Buffer IDSEL W2 W3 PCI Agent A Design Guide

47 PCI/PCI-X Interface Dual-Slot At 100 MHz Figure 19 shows one of the chipset PCI AD lines branching into two segments with each going through a hotplug switch (shown as a FET) and slot connectors to a buffer on a add-in card. This topology is a far-end clustered configuration. For other topologies such as balanced star refer to the PCI-X Electrical Subgroup Report listed in the reference section. The FET can be removed and replaced with a shorting segment for non-hotplug applications. Table 12 provides the wiring lengths for 100 MHz dual-slot design. Figure 19. Dual-Slot Configuration W1 2 W11 FET W12 12 W13 Host W14 2K W15 W PCI Connector Slot 1 W21 FET W22 W PCI Connector Slot 1 A Table12. WiringLengthsfor100MHzDual-Slot Lower AD Bus Upper AD Bus Segment Units Minimum Length Maximum Length Minimum Length Maximum Length W inches W inches W inches W inches W inches W inches W Note 1 N/A N/A inches W15 note N/A N/A inches W N/A N/A inches NOTE: : W14, W15 and W16 represent the IDSEL line. W14 and W15 <= 0.8 Design Guide 47

48 PCI/PCI-X Interface Intel I/O Processor Applications Using PCI-X 100 MHz This section describes applications using with the PCI-X bus running at 100 MHz. These applications include PCI-X add-in cards as well as standalone applications. As mentioned in the Table 9 the maximum PCI-X loads at 10 0MHz is four PCI-X 100MHz Add-in cards Figure 20 shows a PCI-X add-in card configurations at 100 MHz. The host bridge in Figure 20a is capable of driving two slots at 100 MHz representing four electrical loads. The first application without a bridge shows as a single load to the PCI-X slot. This is a PCI requirement that each add-in card represent a single load on the PCI bus. Figure 20b shows the add-in card with the IBM bridge. In this case the bridge can drive four loads which can consist of and three PCI-X devices. Alternately the can be connected to an additional PCI-X device and a PCI-X slot (capable of 100 MHz). 48 Design Guide

49 PCI/PCI-X Interface Figure 20. Add-in Card PCI-X 100 MHz Configurations A Intel Add-in Card 1 load Intel I/O Processor 1 load PCI-X Bus PCI-X Bus Host Bridge CPU Motherboard Intel Add-in card configuration without a PCI-X Bridge B Intel I/O Processor 1 Load Intel Add-in Card PCI-X Bus PCI-X Device 1 Load 3 PCI-X Devices 1 load 1 load PCI-X Bus IBM PCI-X Bridge PCI-X Bus Host Bridge CPU Motherboard Intel Add-in card configuration with a PCI-X Bridge with three PCI-X devices plus Intel I/O Processor A Design Guide 49

50 PCI/PCI-X Interface Embedded Intel I/O Processor Application at 100 MHz Figure 21 shows application in a standalone embedded application. In this application can drives three loads for a total of four loads. Figure 21 shows the PCI-X layout for an embedded 133 MHz design and Table 13 shows the corresponding wiring rules. Figure 21. Embedded Intel I/O Processor Application at 100 MHz Intel MHz Standalone Application Intel I/O Processor PCI-X Chip 1 load PCI-X Bus 3 loads A Table 13. Wiring Lengths for Embedded 100 MHz Design Segment Lower AD Bus Upper AD Bus Minimum Length Maximum Length Minimum Length Maximum Length Units W inches W N/A N/A inches W N/A N/A inches W N/A N/A inches W N/A N/A inches Figure 22. Embedded Intel I/O Processor Design 100 MHz PCI-X Layout W1 Intel I/O Buffer IDSEL W2 W3 PCI Agent 1 W4 PCI Agent 2 W5 PCI Agent 3 A Design Guide

51 PCI/PCI-X Interface Quad-Slots at 66 MHz Figure 23 shows one of the chipset AD lines branching to four segments with each segment connecting to a slot connector to a buffer on a add-in card. The first segment representing an upper address line branches to series resistor to become the IDSEL line for slot 1. This topology is a far-end clustered configuration. Figure 23. Quad-Slots 66 MHz Topology W1 12 W13 Host 1 W14 2K W PCI Connector W Slot 1 W22 22 PCI Connector 23 W23 24 Slot 2 W32 32 PCI Connector 33 W33 34 Slot 3 W42 42 PCI Connector 43 W43 44 Slot 4 A Note: W14, W15 and W16 represent the IDSEL line. W14 and W15 <= 0.8 Design Guide 51

52 PCI/PCI-X Interface Table 14. Wiring Lengths for 66 MHz Quad-Slot Segment Lower AD Bus Upper AD Bus Minimum Length Maximum Length Minimum Length Maximum Length Units W inches W inches W inches W Note 1 N/A N/A inches W15 Note N/A N/A inches W N/A N/A inches W inches W inches W inches w inches W inches W inches W inches W inches W inches NOTE: : W14, W15 and W16 represent the IDSEL line. W14 and W15 <= Design Guide

53 PCI/PCI-X Interface PCI-X 66 MHz Add-in Cards Figure 24 shows a PCI-X add-in card configurations at 66 MHz. The host bridge in Figure 24a is capable of driving four slots at 66 MHz representing eight electrical loads. The first application without a bridge shows as a single load to the PCI-X slot. This is a PCI requirement that each add-in card represent a single load on the PCI bus. Figure 24b showsthe add-in card with the IBM bridge. In this case the bridge can drive eight loads which can consist of and seven PCI-X devices or an additional PCI-X device and three PCI-X slots (capable of 66 MHz). Figure 24. Add-in Card PCI-X 66 MHz Configurations A Intel Add-in Card 1 load Intel I/O Processor PCI-X Bus 4 PCI-X Slots 1 load Host Bridge Processor Motherboard Intel Add-in card configuration without an IBM PCI-X Bridge B Intel PCI-X 66 MHz Add-in Card Intel I/O Processor PCI-X Device 3 PCI-X Slots 1 load IBM PCI-X Bridge PCI-X Bus 4 PCI-X Slots 1 load Host Bridge Processor Motherboard Intel Add-in card configuration with an IBM PCI-X Bridge A Design Guide 53

54 PCI/PCI-X Interface Embedded Intel I/O Processor Application at 66 MHz Figure 25 shows an in a standalone embedded application. In this application can drive seven loads for a total of eight loads. Figure 26 shows the PCI-X layout for an embedded 66 MHz design and Table 15 shows the corresponding wiring rules. Figure 25. Intel I/O Processor Embedded 66 MHz Application Intel IOP 66 MHz Application 4 Loads 2 PCI-X 66 MHz Slots Intel I/O Processor PCI-X Chip 1 load 3 loads PCI-X Bus A Table 15. Wiring Lengths for Embedded 66 MHz Design Segment Lower AD Bus Upper AD Bus Minimum Length Maximum Length Minimum Length Maximum Length Units W inches W N/A N/A inches W N/A N/A inches W N/A N/A inches W N/A N/A inches W N/A N/A inches W N/A N/A inches W N/A N/A inches W N/A N/A inches 54 Design Guide

55 PCI/PCI-X Interface Figure 26. Embedded Intel I/O Processor Wiring for 66 MHz W1 Intel I/O Buffer IDSEL W2 W3 PCI Agent 1 W4 PCI Agent 2 W5 PCI Agent 3 W6 PCI Agent 4 W7 PCI Agent 5 W8 PCI Agent 6 W9 PCI Agent 7 A Design Guide 55

56 PCI/PCI-X Interface This Page Intentionally Left Blank 56 Design Guide

57 Memory Interface 7 The Intel I/O Processor (80321) integrates a Memory Controller Unit, MCU to provide a direct interface between the and the local memory subsystem. The Memory Controller supports: PC200 Double Data Rate (DDR) SDRAM Between 64 MBytes and 1 GByte of 64-bit DDR SDRAM Between 32 Mbytes and 512 Mbytes of 32-bit DDR SDRAM for low cost solutions Single-bit error correction, multi-bit detection support (ECC) 1024-byte Posted Memory Write Queue 40- and 72-bit wide Memory Interfaces The DDR SDRAM interface provides a direct connection to a high bandwidth and reliable memory subsystem. The DDR SDRAM interface consists of a 64-bit wide data path to support 1.6 GBytes/sec throughput. An 8-bit Error Correction Code (ECC) across each 64-bit word improves system reliability. The ECC is stored into the DDR SDRAM array along with the data and is checked when the data is read. When the code is incorrect, the MCU corrects the data (when possible) before reaching the initiator of the read. User-defined fault correction software is responsible for scrubbing the memory array. The MCU supports two banks of DDR SDRAM in the form of one two-bank dual inline memory module (DIMM) or discrete PC200 SDRAM devices on the PC board. Note: The MCU has support for both Unbuffered and Registered (buffered) PC1600 DIMMs. The MCU supports a 32-bit SDRAM data interface. This mode enables lower-cost solutions at the cost of system performance. The MCU responds to internal bus memory accesses within its programmed address range and issues the memory request to the DDR SDRAM interface. The MCU provides two chip enables to the memory subsystem. These two chip enables service the DDR SDRAM subsystem (one per bank). Design Guide 57

58 Intel I/O Processor Memory Interface 7.1 DDR SDRAM Configurations The MCU supports a memory subsystem ranging from 64 Mbytes to 1 Gbyte. An ECC or non-ecc system may be implemented using x8, or x16 devices. Table 16 describes the supported DDR SDRAM configurations. Figure 27. Discrete Dual-Bank DDR SDRAM Memory Subsystem Intel I/O Processor DQS[8:0] DQ[63:0] CB[7:0] RAS# CAS# WE# MA[12:0] BA[0:1] DM[8:0] CKE[1:0] CS0# CS1# M_CK[2:0] M_CK[2:0]# RCVENO RCVENI DQS[8:0] DQ[63:0] CB[7:0] RAS# CAS# WE# A[12:0] BA[0:1] DQM[8:0] CKE CS M_CK M_CK# 64/256 Mbit BANK0 SDRAM Devices DQS[8:0] DQ[63:0] CS[7:0] RAS# CAS# WE# A[12:0] BA[0:1] DQM[8:0] CKE1 CS# M_CK M_CK# 64/256 Mbit BANK1 SDRAM Devices A Design Guide

59 Intel I/O Processor Memory Interface Figure 28. Buffered/Unbuffered DIMM SDRAM Memory Intel I/O Processor Registered or Unregistered DIMM M_RST# RST# 1 DQS[8:0] DQ[63:0] CB[7:0] RAS# CAS# WE# MA[12:0] BA[0:1] DM[8:0] CKE[1:0] CS0# CS1# M_CK[2:0] M_CK[2:0]# RCVENO RCVENI DQS[8:0] DQ[63:0] CS[7:0] RAS# CAS# WE# MA[12:0] BA[0:1] DM[8:0] CKE[1:0] CS0# CS1# M_CK[2:0] M_CK[2:0]# Note: 1 RST# used for buffered DIMMs A Design Guide 59

60 Intel I/O Processor Memory Interface Table 16. Supported DDR SDRAM Configurations DDR SDRAM DDR SDRAM Arrangement #Banks Total Memory Size 1 Address Size Leaf Select Row Column BA[1] BA[0] 64Mbit 8M x 8 16M x Mbit 8M x 16 32M x Mbit 16M x 16 64M x Mbit 32M x M 2 128M 1 128M 2 256M 1 64M 2 128M 1 256M 2 512M 1 128M 2 256M 1 512M 2 1G 1 256M 2 512M 12 9 I_AD[25] I_AD[24] I_AD[26] I_AD[25] 12 9 I_AD[25] I_AD[24] I_AD[27] I_AD[26] 13 9 I_AD[26] I_AD[25] I_AD[28] I_AD[27] I_AD[27] I_AD[26] 1. Table 16 indicates 64-bit wide memory subsystem sizes. For 32-bit wide memory, the memory subsystem size would be half of that indicated. 64/128/256/512 MBit DDR SDRAM devices comprise four internal leaves. The MCU controls the leaf selects within 64/128/256/512 Mbit DDR SDRAM by toggling BA[0] and BA[1]. Thetwo DDR SDRAM chip enables (CS[1:0]#) support an DDR SDRAM memory subsystem consisting of two banks. The base address for the two contiguous banks are programmed in the DDR SDRAM Base Register (SDBR) and must be aligned to a 32 Mbyte boundary. The size of each DDR SDRAM bank is programmed with the DDR SDRAM boundary registers (SBR0 and SBR1). Note: DDR SDRAM memory space must be aligned to a 32 Mbyte boundary and must not cross a 1 Gbyte boundary Registered DDR (buffered) DIMM Registered DDR DIMM modules latch the address bus before it is distributed to each of the DDR chips. This increases the access time by a single clock count to provide for the registering of the data. 60 Design Guide

61 Intel I/O Processor Memory Interface 7.2 DDR SDRAM Initialization When the DDR SDRAM subsystem implements ECC (see Intel Processor based on Intel XScale Microarchitecture Datasheet, Section 7.2.3, Error Correction and Detection on page 7-26), then initialization software should initialize the entire memory array with the It is important that every memory location has a valid ECC byte. The Application Accelerator Unit, AAU includes a memory block write mode which can be used to fill the memory array with a constant (Intel Processor based on Intel XScale Microarchitecture Datasheet, Section 6.5.2, Memory Block Fill Operation on page 6-27), thereby initializing the associated ECC bytes in the process. When the memory array is not initialized, the Bus Interface Unit, BIU may attempt to read memory locations beyond the specified word(s). In this case, the MCU reports an ECC error even though software did not specifically request the uninitialized data. Design Guide 61

62 Intel I/O Processor Memory Interface 7.3 DDR Signal Grouping Table 17. Grouping of DDR Signals Group Type Signal Group Description Clocks Feedback Data Clock Clock Source Synchronous Source Synchronous Source Synchronous M_CK[2:0] M_CK[2:0]# RCVENI# RCVENO# DQ[63:0] CB[7:0] DQS[8:0] DDR SDRAM Clock Out - Three (positive lines) of the output clocks driven to the Unbuffered DIMMs supported by the Intel I/O processor. Registered DIMMs only use M_CK[0] which drives the DIMM PLL. DDR SDRAM Clock Out - Three (negative lines) of the output clocks driven to the unbuffered DIMMS. Registered DIMMs only use M_CK[0]# which to drive the DIMM PLL. RCVENI# Receive Enable In - Connected to RCVENO# of the Intel I/O processor RCVENO# Receive Enable Out - this pin must be connected to RCVENI# of the and be Trace Length Matched = Average Memory Clock Length + Average DQS Length. Data Bus ECC Bus -8-bit error correction code Data Strobes - Strobes that accompany the data to be read or written from the DDR SDRAM devices. Data is sampled on the negative and positive edges of these strobes. Control Command Source Synchronous Source Clocked Source Clocked Source Clocked Source Clocked Source Clocked Source Clocked Source Clocked Source Clocked DM[8:0] M_RST# SCKE[1:0] CS[1:0]# MA[12:0] MA[10] BA[1:0] RAS# CAS# WE# Data Bus Mask - Controls the DDR SDRAM data input buffers. Asserting WE# causes the data on DQ[63:0] and CB[7:0] to be written into the DDR SDRAM devices. DM[8:0] controls this operation on a per byte basis. DDR Registered DIMM Reset - Reinitializes registered DIMM during a P_RST# assertion M_RST# during a P_RST# assertion or whenever internal bus reset bit is asserted in the PCSR. Clock enables - One clock after CKE[1:0] is deasserted, data is latched on DQ[63:0] and CB[7:0]. Chip Select - Must be asserted for all transactions to the DDR SDRAM device. One per bank. Address bits 12 through 0 Indicates the row or column to access depending on the state of RAS# and CAS# Address bit 10 Column burst read or write with auto precharge is not supported by the DDR SDRAM Bank Selects - Controls which of the internal DDR SDRAM banks to read or write RAS# Row Address Strobe - Indicates that the current address on MA[12:0] is the row. RAS# Row Address Strobe - Indicates that the current address on MA[12:0] is the row. WE# Write Strobe - Defines whether or not the current operationbytheddrsdramistobeareadorawrite. 62 Design Guide

63 Intel I/O Processor Memory Interface DDR Bias Voltages The supports 2.5 V DDR memory. Table 18 lists the minimum/maximum values for the DDR memory bias voltages. Table 18. DDR Bias voltages Symbol Parameter Minimum Maximum Units V CC V Supply Voltage for DDR (also referenced as V DD25 ) V V DDQ I/O Supply Voltage V V REF Memory I/O Reference Voltage V CC25 / V CC25 / V V TT DDR Memory I/O Termination Voltage V REF V REF V Design Guide 63

64 Intel I/O Processor Memory Interface 7.4 DDR Layout Guidelines using the DDR-SDRAM memory sub system has continuous ground referencing for all DDR signals. The DDR channel requires the referencing stack-up to allow ground referencing on all of the DDR signals from the to the parallel termination at the end of the channel. All DDR signals should be routed 5/12 (5 mils wide with at least 12 mil spacing between adjacent traces) unless otherwise noted. The DDR interface is divided up into three groups that have special routing guidelines: Source synchronous signal group Source clocked and command signals Clock and CKE signals Note: The receive enable out pin RCVENO# must be connected to the receive enable in pin RCVENI#. The RCVENI# trace length should be matched to the Average Clock L + Average DQS length. 64 Design Guide

65 Intel I/O Processor Memory Interface Source Synchronous Signal Group The guidelines below are for the source synchronous signal group which includes Data bits DQ, check bits CB, data mask DM, anddqs associated strobe. The source synchronous signals are divided into groups consisting of data bits DQ and check bits CB. There is an associated strobe DQS for each DQ, DM and CB group. When data masking is not used system memory DM pins on the DDR should be tied to ground. The grouping is as follows for the different memory configurations: Table 19. x64 DDR Memory Configuration Data Group DQ[7:0], DM[0] DQ[15:8], DM[1] DQ[23:16], DM[2] DQ[31:24], DM[3] DQ[39:32], DM[4] DQ[47:40], DM[5] DQ[55:48], DM[6] DQ[63:56], DM[7] Associated Strobe DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 Table 20. Note: Table 19 is valid for all the following x64 configurations: one and two bank configurations x8, x16 DDR unbuffered and registered DDR. x72 DDR Memory Configuration Data Group DQ[7:0], DM[0] DQ[15:8], DM[1] DQ[23:16], DM[2] DQ[31:24], DM[3] DQ[39:24], DM[4] DQ[47:40], DM[5] DQ[55:48], DM[6] DQ[63:56], DM[7] CB[7:0], DM[8] Associated Strobe DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 Note: Table 20 is valid for all the following x72 configurations: one and two bank configurations x8, x16 DDR unbuffered and registered DDR. Design Guide 65

66 Intel I/O Processor Memory Interface Routing Requirements Table 21 and Table 22,and Figure 29 through Figure 31 show the routing and termination requirements for the source synchronous signal group. Table 21. Source Synchronous Termination Requirements DDR SDRAM Rs 1 Series Rp 2 Parallel 10 +/- 1% ohms 60 +/- 1% ohms 1. Rs is the series resistor. 2. Rp is the parallel termination resistor. 3. These resistor values are valid for all memory configurations x8 1DD, x8 1SD, x16 1SD, Registered 1SD and Registered 1DD. Figure 29. Source Synchronous Length Matching 8 DQ Lines 1 DQS Line Intel I/O Processor DQ Length = X ± 25 mils DQS Length = X mil DQ Length = X ± 25 mils DataGroup 7:8 DQ Lines 1 DQS Line DIMM DQS Length = Y mil DQ Length = Y ± 25 mils A Design Guide

67 Intel I/O Processor Memory Interface Figure 30. Source Synchronous Routing DQ/CB group Rs = 10 Ω ± 1% Rp = 60 Ω ± 1% V TT Intel I/O Processor DQ/CB group Associated DQS Associated DQS Notes: Rs = Series Resistor Rp = Parallel Termination Resistor 1.8" - 4.9" DDR DIMM < 0.5" 0.1" to 0.8" A Table 22. Source Synchronous Routing Recommendations Parameter Routing Guideline Reference Plane TraceWidth Trace Spacing Group Spacing Trace Length 1: signal Ball to Series Termination Trace Length 2: Series Resistor Pad to DIMM Pin or first tree branch segment for SDRAM on the board Trace Length 3: DIMM to Parallel Termination Resistor Pad ground 5mils 12 mils nominally (7 mils acceptable through pin field). Spacing from other groups 20 mils minimum 1.8 minto4.9 max.5 max 0.1 min. to 0.8 max Trace Lengths for SDRAM on the board: Use lengths from the Unbuffered DDR JEDEC specification Series Resistor Rs 10 Ω +/- 1% Parallel Resistor Rp 60 Ω +/- 1% Length Matching Requirements: DQS Group +/ within DQS group Length Matching Requirements: To Clock Routing Guideline 1 Routing Guideline 2 Each DQS signal at a particular DIMM should have a maximum length x - 1 and minimum length of x - 2 where x = M_CK/M_CK# pair length. Route all data signals and their associated strobes on thesamelayer. Minimize layer changes (two vias or less) Design Guide 67

68 Intel I/O Processor Memory Interface Figure 31. Data Group Length Matching Longest Length DQ = x - 1" Intel I/O Processor Shortest Length DQ = x - 2" CK CLK Length = x CK# CLK# Length = x DDR DIMM A Note: Lengths are measure from pad to DIMM connector pin (including the series resistor). 68 Design Guide

69 Intel I/O Processor Memory Interface Source Clocked and Command Clock Signal Groups The drives the command clock signals required by the DDR interface. The source-clocked signals are clocked into the DIMM using the command clock signals. The drives the command clock signals and the source-clocked signals together, these signals can be source clocked. The drives the command clock in the center of the valid window, and the source-clocked signals propagate with the command clock signal. An important timing specification is the difference between the command clock flight time and the source clocked signal flight time. The absolute flight time is not as critical Clocked Signal Group The common clock signal group contains M_CK[2:0] and M_CK[2:0]#. The below tables and figures show the routing requirements for the clock signal group. Table 23. Clocked Signal Group Termination DDR SDRAM Rs 1 Series Rp 2 Parallel 27 +/- 1% ohms 120 +/- 1% ohms (non-dimm) 1. Rs is the series resistor. 2. Rp is the parallel termination resistor. DIMMs contain have termination resistor. Use 120 ohms for SDRAM on board only. 3. These resistor values are valid for all memory configurations x8 1DD, x8 1SD, x16 1SD, Registered 1SD and Registered 1DD. Figure 32. Trace Guidelines for Clocks DDR DIMM DQ Intel I/O Processor M_CK0 M_CK0# M_CK1 M_CK1# M_CK2 M_CK2# Length = x0 Length = x0# Length = x1 Length = x1# Length = x2 Length = x2# B A x0-x0# = 2 mils x1-x1# = 2 mils x2-x2# = 2 mils DQ Length = 1-7" A Design Guide 69

70 Intel I/O Processor Memory Interface Table 24. Clock Signal Group Routing Requirements Parameter Routing Guideline Reference Plane TraceWidth NOTE: 1 To meet the minimum DQ line length between (x-2) to (x-1 ) this minimum clock length may have to be increasedto Source Clocked Signals Termination ground 5mils 7 mils from one clock M_CK of the differential pair Trace Spacing M_CK#. At least 20 mils between the different pair sets. Group Spacing Spacing from other groups 20 mils minimum Trace Length 1: signal Ball to DIMM 1 min. to 7 max. 1 Trace Length 2: signal Ball to Series Termination not specified (within 1-7 ) Trace Length 3: Series Termination to DIMM not specified (within 1-7 ) Trace Lengths for SDRAM on the board: Use lengths from the Unbuffered DDR JEDEC specification Series Resistor Rs 27 Ω +/- 1% Parallel Resistor Rp Length Matching Requirements: Within differential pairs Length Matching Requirements: Between clock groups Routing Guideline 1 Routing Guideline 2 DIMM: Not needed DIMM has a termination resistor Non DIMM On Board SDRAM: 120 Ω +/- 1% Clock signals M_CK and M_CK# should be matched in length within 2 mils when possible (within 25mils is acceptable). Length between clock groups M_CK0/M_CK0#, M_CK1/M_CK1# and M_CK2/M_CK2# should be matchedtowithin +/-.025 (as tightly as feasible with layout tools). Clock signals polarity should be alternated. Minimize layer changes (two vias or less) The source clocked signal group includes RAS#, CAS#, WE#, BA[1:0] and MA[12:0].Theseries and parallel termination is shown in Table 25. Table 25. Source Clocked Signal Routing DDR SDRAM Rs 1 Series Rp 2 Parallel 15 +/- 1% ohms 60 +/- 1% ohms 1. Rs is the series resistor. 2. Rp is the parallel termination resistor. 3. These resistor values are valid for all memory configurations x8 1DD, x8 1SD, x16 1SD, Registered 1SD and Registered 1DD. 70 Design Guide

71 Intel I/O Processor Memory Interface Source Clock Signal Routing Guidelines Figure 33, Figure 34and Table 26 provide the routing guidelines for the source clocked group of signals. Figure 33. Trace Length Requirements for Source Clocked Routing DDR DIMM Rs 1 Rp 2 V TT RAS, CAS, WE Intel I/O Processor MA[12:0], BA[1:0] 2" - 5" <0.100" to 0.800" Notes: 1 Lengths are measured from the Intel I/O processor pad to the DIMM connector pin. 2 Resistor packs are acceptable for the parallel (Rp) control termination resistors but control signals can NOT be placed within the same RPACK as data, strobe, or command signals. Rs = Series Resistor Rp = Parallel Termination Resistor A Figure 34. Matching Control Signals to the Clocks Longest Length CNTRL = x - 1" Intel I/O Processor Shortest Length CNTRL = 2" CLK CLK Length = x CLK# CLK# Length = x DDR DIMM A Design Guide 71

72 Intel I/O Processor Memory Interface Table 26. Source Clocked Signals Routing Guidelines Parameter Routing Guideline Reference Plane ground TraceWidth 5mils Trace Spacing 12 mils nominally (7 mils acceptable through pin field). Group Spacing Spacing from other groups 20 mils minimum Trace Length 1: signal Ball to DIMM 2 min. to 5 max Trace Length 2: signal Ball to Series Termination not specified (within 2-5 ) Trace Length 3: Series Termination to DIMM not specified (within 2-5 ) Trace Length 4: DIMM to parallel termination Minimum of.1 to maximum of.8 Trace Lengths for SDRAM on the board: Use lengths from the Unbuffered DDR JEDEC specification Series Resistor Rs 15 Ω +/- 1% Parallel Resistor Rp 60 Ω +/- 1% Length Matching Requirements: To Clock Minimum length is 2, maximum is clock length - 1 Routing Guideline 1 Route these signals on the same layer as the M_CKs. Routing Guideline 2 Minimize layer changes (two vias or less) 72 Design Guide

73 Intel I/O Processor Memory Interface Routing Requirements for Chip Selects and CKE Lines The provides two chip select signals and two clock enable lines. Two chip selects are routed to the DIMM (one for each side). This signal is used during initialization to indicate that valid power and clocks are being applied to the DIMM. The trace length and matching requirements for chip selects and CKE lines are the same as what is recommended in Figure 33 and Figure 34. Table 27. Chip Select and CKE Termination DDR SDRAM Rs 1 Series Rp 2 Parallel 10 +/- 1% Ω 60 +/- 1% Ω Rs is the series resistor. Rp is the parallel termination resistor. These resistor values are valid for all memory configurations x8 1DD, x8 1SD, x16 1SD, Registered 1SD and Registered 1DD. Table 28. CS and CKE Signal Routing Guidelines Parameter Routing Guideline Reference Plane ground TraceWidth 5mils Trace Spacing 12 mils nominally (7 mils acceptable through pin field). Group Spacing Spacing from other groups 20 mils minimum Trace Length 1: signal Ball to DIMM 2 min. to 5 max Trace Length 2: signal Ball to Series Termination not specified (within 2-5 ) Trace Length 3: Series Termination to DIMM not specified (within 2-5 ) Trace Length 4: DIMM to parallel termination Minimum of 0.1 to maximum of 0.8 Trace Lengths for SDRAM on the board: Use lengths from the Unbuffered DDR JEDEC specification Series Resistor Rs 10 Ω +/- 1% Parallel Resistor Rp 60 Ω +/- 1% Length Matching Requirements: To M_CK clock Routing Guideline 1 Routing Guideline 2 Minimum length is 2, maximum is M_CK clock length - 1 Route CS and CKE lines on the same layer as the M_CKs Minimize layer changes (two vias or less) Design Guide 73

74 Intel I/O Processor Memory Interface DDR Signal Termination This section provides suggested guidelines for layout of the DDR termination resistors: Place a 1.25 V termination plane on the top layer or one of the inner layers, just beyond the DIMM connector. The V TT island must be at least 50 mils wide. Use this termination plane to terminate all DIMM signals, using the one termination resistor per signal. Decouple the V TT plane using one 0.1 µf decoupling capacitor per two termination resistors. Each decoupling capacitor must have at least two vias between the top layer ground fill and the internal ground plane. In addition, place one 10 µf or larger (100 µf suggested) Tantalum capacitor on each end of the termination island for bulk decoupling. Figure 35 provides an example of how to route the termination resistors. Figure 35. Routing Termination Resistors 2 Vias per Capacitor 1.0 µf Capacitor per two resistors 10.0 µf Capacitor 1.25 V Plane GND Plane < = 50 mil wide DIMM Rp Note: Rp = Parallel Termination Resistor A Discrete DDR Devices Use the same guidelines as shown in the above sections. However, to compensate for the trace length on the DIMM, add DIMM TL0 lengths (which are specified in the PC1600 and PC2100 DDR SDRAM Unbuffered DIMM Design Specification) to the trace lengths specified in the above sections. The same guidelines for routing for each of the control groups can be extrapolated from the above DIMM layout guidelines. Clock tree cannot be reduced without complete SI analysis. Refer to the PC1600 and PC2100 DDR SDRAM Unbuffered DIMM Design Specification for more details on the clock tree. Rs may be combined into a single resistor, tolerance becomes 1%. Rp stub must be connected between Rs and first branch. 74 Design Guide

75 Intel I/O Processor Memory Interface 7.5 DDR Voltages Requirements This section provides the details about the specific requirements for DDR Voltages as well as example circuitry DDR Termination Voltage V TT The V TT 1.25 V DDR termination voltage must track the V DDQ2.5 V and provide the termination voltage to the termination resistors. This tracking must be 50 percent of (V DDQ2.5 - V SSQ ) over voltage, temperature, and noise. It must maintain less than 40 mv offset from V REF over these conditions. This voltage must be low-impedance and source-significant current. The source and sink DC current for signal termination is at its absolute maximum current of A for a 64/72-bit DIMM. The customer reference board uses a Texas Instruments * Buck Controller TPPM0115 to generate this V TT voltage and V DDQ 2.5 V. It was chosen for its current source capability. For example while sourcing 12 A, the controller circuitry generates 14 mv of ripple or 0.56%. It can also dynamically switch current loads between 1 A and 8 A with 52.4 mv of ripple or 2.1%. Figure 36 shows a DDR memory application using the TPPM0115 device. Note that in the CRB 5 V and12vfromthepcislotwasusedtopowerthetppm0115andfetstoallowamplepower.refer to the Texas Instruments TPPM0115 Switch Mode Synchronous Buck Controller Specification and Intel Evaluation Platform Board schematics for actual circuit implementation. Figure V Power Generation 5 V MBRS340T3 0.1 µf 4.7 µf 4.7 µf 1000 µf 1000 µf D 12V Supply 5V 1 1 µf 2 20K 3 4 TPPMO115 GND V CC PWRGD SEN DRVL NC DRVH PHASE pf G G S D S 3.3 µh 1500 µf Low ESR 2.2K 4700 pf 470µF 470µF 470µF 470µF 0.1µF Low ESR caps 3K 1% VDD2_5 VDDQ 2K 1% A Design Guide 75

76 Intel I/O Processor Memory Interface Figure 37 details how the V DDQ is used to generate the V TT 1.25 V voltage. This circuitry allows V TT to track V DDQ voltage. Figure 37. V TT Termination Voltage Generation VDDQ FQD13N06L 5 V 1.5K 1% 0.1 µf (1.25 V) VTT 4.7 µf 0.1 µf 220 µf Low ESR 220 µf Low ESR 1K P-Channel LMV K 1% DDR REF 1 µf FDD5614P A DDR Reference Voltage V REF The DDR V REF is a low-current source (supplying input leakage and small transients). It must track 50 percent of (V DDQ2.5 -V SSQ ) over voltage, temperature, and noise. Use a single source for V REF to eliminate variation and tracking of multiple generators. Maintain mils clearance around other nets. Use a distributed decoupling scheme. Use a simple resistor divider with 1% or better accuracy. An example of this circuit is shown in Figure Design Guide

77 Intel I/O Processor Memory Interface 7.6 Power-up Sequencing There are guidelines for power up sequencing of the DDR to prevent latch-up. For more details refer to your DDR chip or module manufacturer specification. The sequence is as follows: 1. System sets M_RST# low (registered device). 2. Power-up V DD and V DDQ. V DD should lead V DDQ or they should rise simultaneously 3. Power-up of supply V REF and V TT. V REF and V TT should rise at the same time or after V DDQ. V TT should not precede V DDQ to prevent latch-up. 4. The system must drive clocks to the PLL. 5. The system must drive valid levels on the address and control inputs to the DDR. SCKE lines should be held low. 6. The M_RST# can be switched high (registered device) Power Failure Mode The power-fail circuit uses the PWRDELAY signal implemented on the Applications that support battery back-up circuit for the SDRAM must also be able to control the SCKE pins of the DDR. The circuit shown in Figure 38 through Figure 40, serve three purposes: Monitors the board voltage to initiate a power-fail sequence Generates PWRDELAY signal to reset the power-fail state machine Controls the SCKE signals of the DDR SDRAM while system power is off AccordingtothePCI Local Bus Specification, Revision 2.2, PCI RST# can be asserted when the system power drops as low as 2.5 V. This voltage is too low for the to be able to execute the power-fail sequence. Figure 38. Power Failure Comparator Circuit +3.3V 3.01 KW 1% 12.1 KW 1% 10 KW 1% V+ MAX921 IN+ IN OUT HYST REF GND V KW 5% POWER_GOOD A The comparator circuit shown in Figure 38 is used to trigger a power-fail sequence while the power to the is still within valid operating conditions. The trip point of the comparator is set using the ratio of 0.4. This is set with the voltage divider values of the 10 K and the combined value 12.1 K and 3.01 K 1% resistors. This ratio provides a trip point value of 2.96 V. When the 3.3 V rail falls below the 2.96 V level the POWER_GOOD signal is forced low. In the CRB the S_RST#, secondary side reset (CRB connects to the secondary side of the PCI-X bridge), is tied to the P_RST# pin of the The S_RST# triggers the power-fail sequence. Design Guide 77

78 Intel I/O Processor Memory Interface The RC Circuit consisting of the 0.22 µf capanda10kω resistor in the Figure 39 is used to generate the PWRDELAY signal. This PWRDELAY is an analog input to the It is used by the processor to reset the memory controller in a power-fail condition. This PWRDELAY signal remains asserted a few milliseconds after the P_RST# to allow ample time for the power-fail state machine to execute its sequence. When P_RST# is deasserted, the FET is turned on allowing the capacitor to charge. The circuit stays charged until the system looses power or system asserts P_RST#.WhenP_RST# is high but the system loses power, the RC circuit discharges through the diode. When P_RST# is low but the power is still valid, the RC circuit discharges through the resistor to ground. Figure 39. Power Delay Circuit P_RST* LVC08AD 8 P_RST* 1 POWER_GOOD +3.3V K 74LVC04AD G S MBRSI30T3 D SI K 10K.22µF PWRDELAY A Design Guide

79 Intel I/O Processor Memory Interface The SCKE latch circuitry in the above Figure 40 is battery powered. It allows maintaining the SCKE[1:0] while the system power is off. The DDR remains in self-refresh mode while SCKE[1:0] are low. The latches are cleared when the drives SCKE[1:0] low with a self-refresh command and are reset when P_RST# is driven from low to high after system power is recovered. During normal operation, the SCKE signals are controlled by the while the PnP transistors are turned off. During the power-up, the output of the PWRDELAY signal forces the SCKE signals low using the Q1 and Q2 transistors. When the power is turned off, the battery powered latches pull the SCKE signals low using Q3 and Q4. Figure 40. SCKE Circuit SCKE0 OUT MMBT3906 Q3 MMBT3906 Q1 74LVC08AD P_RST* 1 74LVC32 SCKE1 OUT MMBT3906 Q4 Q2 MMBT LVC08AD 74LVC32 PWRDELAY 74LVC14 74LVC14 A With a self-refresh command the DDR is able to store data. After a self-refresh command, the DDR refreshes itself autonomously with internal logic and timers. The DDR remains in the self-refresh mode as long as it continues to be powered and the SCKE[1:0] signals are held low. Design Guide 79

80 Intel I/O Processor Memory Interface Non-Battery Backup Circuits For applications that do not support battery back-up, this circuit is not required. In this case follow these steps: Pull the DDR SCKE pins high, and leave the SCKE signals on the as no connects. This keeps the SDRAM from entering a pseudo, self-refresh mode which can cause a lock-up condition on the SDRAM device. Pull the PWRDELAY pin low through a 1.5 K pull-down. Pulling it low has the effect of keeping the power fail state machine in reset, therefore not allowing the power fail sequence to ever occur Power Failure Sequence For storage applications it is imperative that the data cached within DDR memory system not be lost in a power failure condition. To prevent this from happening the local DDR memory should be saved with provisions for battery backup to allow the DDR data be saved using the refresh mode at an appropriate interval until power is restored. The DDR has a self-refresh command that can be invoked as long as the device remains powered and CKE is held low. Power to DDR SDRAM is ensured with an automatic switch over to backup battery power when the system power is lost. Battery backup should maintain power on DDR voltages V DD, V DDQ and V REF to prevent data loss. Refer to the Intel I/O Processor Developer s Manual, section 7.3, for more information about this Power Failure Mode. PWRGOOD is deasserted P_RST# is asserted allowing 2 µs of reliable power remaining Memory controller assumes that the P_RST# is a power failure condition Clock Reset Unit, CRU initiates the power failure sequence: a. MCU gracefully terminates SDRAM activity b. Issue precharge-all command to SDRAM c. Issue auto-refresh command to SDRAM and wait 8 clocks d. Issue self-refresh command to SDRAM MCU notifies the CRU of the completion of the power failure circuit Clock Reset Unit, CRU then asserts I_RST# to reinitialize all internal bus agents including the MCU Note: The SCKE[1:0] must be held low during the entire power-down sequence. This is initially down with the self-refresh command but a pull-down resistor is required to continually drive it low. 80 Design Guide

81 Intel I/O Processor Memory Interface 7.7 DDR Initialization Note: DDR SDRAM devices require programming of the internal controller prior to use. Refer to the Intel I/O Processor Developer s Manual, section for the appropriate procedure for DDR initialization. When the DDR subsystem implements ECC, it is important that the software initializes the entire memory array with the Every memory location has a valid ECC byte. ECC Initialization can take place by allowing the AAU to do a memory block write to fill the memory array with a constant value. Refer to the Intel I/O Processor Developer s Manual, section 7.3 for more information on ECC. Design Guide 81

82 Intel I/O Processor Memory Interface MCU Configuration Registers These registers provide a series of control parameters necessary for the operation of the DDR devices. Refer to the Intel I/O Processor Developer s Manual for a complete set of the configuration register values. The parameters that get programmed through these registers include: 1. DIMM data bus width 2. DIMM type register/unregistered 3. SDRAM base and boundary (or limit) 4. Error correction or ECC modes and status 5. Refresh frequency 6. Data bus pull-up/pull-down drive strength 7. Clock and Clock enable pull-up/pull-down drive strength 8. Chip select pull-up and pull-down drive strength 9. Receive enable pull-up/pull-down drive strength 10. Address bus pull-up/pull-down drive strength Output Driver Programming Table 30 provides a set of values that was determined in simulation to be optimal for the different DDR configuration types. These values get programmed into the MCU Configuration Registers as mentioned in the last section. Table 29. DDR Output Drive Strength DDR Type Drive Strength Register Address Location X8 1DD, X8 1SD, X16 1SD Reg 1DD, Reg 1SD Data Bus Pull Up FFFF E554H 0dH 0dH Data Bus Pull Down FFFF E558H 0dH 0dH Clock Pull Up FFFF E55CH 22H 22H Clock Pull Down n FFFF E560H 20H 20H Clock Enable Pull Up FFFF E564H 30H 30H Clock Enable Pull Down FFFF E568H 30H 30H Chip Select Pull Up FFFF E56CH 18H 0dH Chip Select Pull Down n FFFF E570H 18H 0dH Receive Enable Pull Up FFFF E574H 0dH 0dH Receive Enable Pull Down FFFF E578H 0dH 0dH Address Bus Pull Up FFFF E57CH 18H 0dH Address Bus Pull Down FFFF E580H 18H 0dH NOTES: 1DD - Double-sided DRAM 1SD - Single-sided DRAM Reg - Register DRAM An increase in buffer output drive strength number provides a stronger buffer and equivalent decreased buffer impedance. 82 Design Guide

83 Intel I/O Processor Memory Interface 7.8 Peripheral Local Bus Bus signals consist of the clock and reset signals and three main groups: Address/Data Control/Status Bus Arbitration Clock and Reset Signals The output signal PB_CLK is the reference for all signal timing relationships. Transitions on the AD31:0, ALE, ADS#, BE3:0#, WIDTH[1:0],W/R#, FWE#, DEN#, BLAST#, RDYRCV#, HOLD,andHOLDA signals are always clocked on the rising edge of PB_CLK. The output signal PB_RST# is used to initialize devices connected to the external peripheral bus. The peripheral bus reset output pin PB_RST# mirrors the P_RST# input pin. In addition, software can reinitialize the PBI and the peripheral bus by writing to bit 4 of the PCSR Address/Data Signal Definitions The address/data signal group consists of 34 lines. Thirty-two of these signals multiplex within the processor to serve a dual purpose. During T A, the processor drives AD31:2 with the address of the bus access. At all other times, these lines are defined to contain data. AD3:2 are demultiplexed address pins providing incrementing DWORD addresses during burst cycles. AD1:0 denotes burst size during T A and data during other states. The PBI routinely performs data transfers less than 32 bits wide for Intel XScale core accesses. When the programmed bus width is 32 bits and transfers are 16- or 8-bit, then during write cycles the PBI replicates the data being driven on the unused address/data signals. When the programmed bus width is 16 or 8 bits, then during read or write cycles the PBI continues driving address on any unused address/data signals. Whenever the programmed bus width is less than 32 bits, additional demultiplexed address bits are available on unused byte enable signals. These signals increment during burst accesses in similar fashion to the AD3:2 pins. Design Guide 83

84 Intel I/O Processor Memory Interface Control/Status Signal Definitions The control/status signals control data buffers and address latches or furnish information useful to external chip-select generation logic. All output control/status signals are tri-state. Bus accesses begin with the assertion of ADS# (address/data status) during a T A state. External decoding logic typically uses ADS# to qualify a valid address at the rising clock edge at the end of T A.ThePBI pulses ALE (address latch enable) active high for one half clock during T A to latch the multiplexed address on AD31:2 in external address latches. The byte enable (BE[3:0]#) signals denote which bytes on the 32-bit data bus transfers data during an access. The PBI asserts byte enables during T A and deasserts them during T R. When the data bus is configured for 16 bits, two byte enables become byte high enable and byte low enable and an additional address bit A1 is provided. When the bus is configured for 8 bits, there are no byte enables asserted, but additional address bits A1:0 are provided. Note that the PBI always drives byte enable signals to logical 1 s during the T R state, even when they are used as addresses. The WIDTH[1:0], and W/R# signals yield useful bus access information for external memory and I/O controllers. The WIDTH[1:0] signals denote programmed physical memory attributes. The write/read signal W/R#, indicates the direction of data flow relative to the. WIDTH[1:0] and W/R# change state as needed during the T A state. W/R# and DEN# signals control data transceivers. Data transceivers may be used in a system to isolate a memory subsystem or control loading on data lines. W/R# (data transmit/receive) is used to control transceiver direction. In the second half of the T A state, it transitions high for write cycles or low for read cycles. DEN# (data enable) is used to enable the transceivers. DEN# is asserted during the first T W /T D state of a bus access and deasserted during T R. W/R# and DEN# timings ensure that W/R# does not change state when DEN# is asserted Bus Arbitration The can share the bus with other bus masters, using its built-in arbitration protocol. The protocol assumes two bus masters: a default bus master (typically the 80321) that controls the bus and another that requests bus control when it performs an operation (e.g., a DMA controller). More than two bus masters may exist on the bus, but this configuration requires external arbitration logic. External bus masters do not have access to the internal peripheral bus. Therefore, an external bus master cannot access any of the internal peripherals (e.g., the Memory Controller, the Intel XScale core,etc.).two PBI signals HOLD and HOLDA comprise the bus arbitration signal group HOLD/HOLDA Arbitration Overview In most cases, the PBI controls the peripheral bus; however, an I/O peripheral (e.g., a communications controller) can request peripheral bus control. The PBI and I/O peripheral device exchange bus control with two signals, HOLD and HOLDA. HOLD is an synchronous input signal which indicates that the alternate master needs the bus. HOLD may be asserted at any time so long as the transition meets the PBI setup and hold requirements. HOLDA (hold acknowledge)is the PBI output which indicates surrender of the bus. When the bus is in hold and the needs to regain the bus to perform a transaction, the PBI does not deassert HOLDA Byte Ordering and Bus Accesses The supports only little endian data types. 84 Design Guide

85 Intel I/O Processor Memory Interface Layout Guidelines for the Peripheral Bus This section provides basic layout guidelines for using the Peripheral Bus. It is recommended that the simulation be performed with closer attention paid to signal integrity for higher frequencies of 66 MHz or 100 MHz. Figures below provide the topology for simulation of clock, control and data lines. Figure 41. Data line layout recommendations: 1. Total trace length per data bus trace line should be less than eight inches. 2. Trace length to the address demultiplexor stub should be as close to zero as possible. 3. Wait states are required when interfacing with the Flash. Refer to the Peripheral Local Bus Section of the Intel I/O Processor Datasheet. 4. To minimize overshoots due to line coupling it is recommended to increase the trace spacing to 7or12mils. 5. Timing is most critical for data returning from peripherals. A termination resistor may be used help to reduce excessive overshoots as well. As a guideline a 50 Ω resistor was used in simulation to the 1, 2 and 4 load case. Peripheral Bus Data Lines Four Load Topology Peripheral Peripheral Peripheral Intel Peripheral Device Output Buffer R term * TL0 TL2 TL3 TL4 TL5 Peripheral Device Input Receiver Buffer TL1 Address Demultiplexor * Use simulation to determine the appropriate termination resistor if needed to improve signal integrity. A Design Guide 85

86 Intel I/O Processor Memory Interface Control Signals: Figure 42. The below diagrams show a control/clock signals in with a single and dual load. 1. A termination resistor is recommended for routing control signals routed to peripheral devices to improve signal integrity. To determine the optimum value simulation is required for your own application. 2. Total trace length per control signals should be less than eight inches. Peripheral Bus Clock Buffer Single-Load Topology Intel PB-CLK Output Buffer R term * PCB trace Input Clock Buffer Peripheral Device * Use simulation to determine the appropriate termination resistor if needed to improve signal integrity. A Figure 43. Peripheral Bus Clock Buffer Dual-Load Topology Intel PB-CLK Output Buffer PCB trace PCB trace Input Clock Buffer 1st Peripheral Device Input Clock Buffer 2nd Peripheral Device A Clock Signals: When your topology is defined with peripherals that are synchronous with the clock then follow the clock layout guidelines, otherwise the clock layout is not critical. 1. The asynchronous peripheral bus connections to external peripheral bus devices such as Flash memory do not require attention to clock layout. 2. It is recommended to route clock signals to the multiple receivers with closely matched lengths +/ Total trace length per clock signals trace line should be less than eight inches. 4. There may be a need for a termination resistor on single clock lines with critical clock timing. To determine the optimum value simulation is required for your own application. 86 Design Guide

87 Intel I/O Processor Memory Interface 7.9 Flash Memory Support PBI peripheral bus interface supports 8-, 16-, or 32-bit Flash devices. Since the Flash wait state profiles for Recovery and Address-to-Data wait states are deterministic, the PBI provides programmable wait state functionality for windows configured for Flash. This saves the system designer from having to provide logic to assert RDYRCV# externally for Flash devices. Any write transactions issued to a Flash address space window must always represent a single peripheral bus data cycle (strb, strh, str).theflashchipenables,pce[5:0]#, activatethe appropriate Flash window when the address falls within one of the Flash address ranges. A Flash bank 0 is enabled as a flash bank with the maximum number of Address-to-Data and Recovery States. The width of the interface can be strapped for either 8-bit wide Flash or 16-bit Flash. The PCE0# is the Peripheral Bus chip enable to be used for booting purposes. Figure 44. Four Megabyte Flash System A[3:0] Intel I/O Processor BE[1:0]#A[1:0] A[3:2] ALE AD[20:0] OE#(W/R#) A[1:0] A[3:2] AD[20:8] AD[7:4] Latch A[7:4] DQ[7:0] Intel 28F Mbit Flash A[20:0] OE# WE# DQ[7:0] CE# WE# PCE0# PCE1# Intel 28F Mbit Flash A[20:0] OE# WE# DQ[7:0] CE# A Design Guide 87

88 Intel I/O Processor Memory Interface Programming the PBI FLASH Interface The provides six Base and Limit Registers. The Base register contains the required bits to be initialized for setting address and flash wait state programming values. Refer to Table 30 for the programmable address-to data and recovery wait states. These numbers depend on the speed of the PBI interface (100 MHz, 66 MHz, or 33 MHz). The bits 8-6 provide the recovery wait states PBI BAR and bits 2-4 provide the address to data wait states. Table 30. Flash Wait State Profile Programming Address-to-Data Wait States Recovery Wait States Flash Speed <= 55 ns <= 115 ns <= 175 ns Layout Guidelines Flash signal loading should not exceed 50 pf. All traces between the and Flash should not exceed eight inches. 88 Design Guide

89 Voltage Power Delivery 8 There are several different voltage domains needed on the These include the following: V CC_PLL1 PLL Power: is a separate V CC13 supply for the phase lock loop clock generator. It is to be connected to the board V CC13 plane. In noisy environments, add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on timing relationships. V CC_PLL2 PLL Power: is a separate V CC13 supply for the phase lock loop clock generator. It is to be connected to the board V CC13 plane. In noisy environments, add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on timing relationships. The lowpass filter, as shown in Figure 45, reduces the noise induced clock jitter and its effects on the timing relationships in system design. The 4.7 µf capacitor must be low ESR solid tantalum, the 0.01 µf capacitor must be of the type X7R and the node connecting the V CCPLL must be as short as possible. The V CCPLL balls should be connected the board ground plane. Figure 45. V CCPLL Circuit Example IN VCC1_3 10 W VCC_PLL1 OUT 4.7 µf 0.01 µf 10 W VCC_PLL2 OUT 4.7 µf 0.01 µf A V REF SDRAM Voltage Reference: is used to supply the reference voltage to the differential inputs of the memory controller pins. As shown in the diagram below the SDRAM Voltage reference is generated with a resistor divider circuit off the 2.5 V voltage to create a stable 1.25 V reference. Design Guide 89

90 Voltage Power Delivery Figure 46. V REF Circuit VDDQ KW ± 1% 0.1 µf V REF 49.9 KW ± 1% 1.0 µf A V CC V Power: connects to a 3.3 V powerboard plane. V CC V Power: connects to a 2.5 V powerboard plane. V CC V Power: connects to a 1.3 V powerboard plane. V TT DDR Termination Resistor: voltage 1.25 V V DDQ DDR Data Voltage: reference 2.5 V 90 Design Guide

91 Voltage Power Delivery 8.1 Power Delivery for the Intel I/O Processor The voltage rails V CC33, V CC25 and V CC13 do not require a specific a power up sequence. Refer to the schematic for more details on the power supply design. 8.2 Intel I/O Processor Core Supply Voltage In most system board designs, the 3.3 V system power supply is routed to board components through a dedicated board layer. With the requirements for 1.3 V and 2.5 V supplies for the 80321, it is not necessary to add completely new power supply layers to the circuit board to facilitate this. It is possible to create supply islands underneath the processor in the existing power supply plane. Other important considerations are: Τhe island must be large enough to include the required power supply decoupling capacitance, and the necessary connection to the voltage source. Τo minimize signal degradation, the gap between the supply island and the voltage plane should be kept to a minimum: typical gap size is about 0.02 inches. Minimize the number of traces routed across the power plane gap, since each crossing introduces signal degradation due to the impedance discontinuity that occurs at the gap. For traces that must cross the gap, route them on the side of the board next to the ground plane to reduce or eliminate the signal degradation caused by crossing the gap. When this is not possible, then route the trace to cross the gap at a right angle (90 degrees). Use liberal decoupling capacitance between the voltage plane and the supply islands. Decoupling the island reduces impedance discontinuity. Figure 47 demonstrate how supply islands can be created. These PCB layout sections are taken from the CRB. Figure 47shows a 1.3 V plane on the GND2 layer. Figure 48 shows the 1.3 V plane in the cavity of on the top layer. Figure 49 shows how multiple voltage islands can be used to supply voltage to as well as the DDR DIMM on the internal signal layer two. Design Guide 91

92 Voltage Power Delivery Figure 47. Voltage Island 1.3 V on GND Layer 2 GND Layer V Supply Island 92 Design Guide

93 Voltage Power Delivery Figure 48. Voltage Island 1.3 V on Top Layer V CC 1.3 V Design Guide 93

94 Voltage Power Delivery Figure 49. Multiple Voltage Islands on Internal Layer 2 V DD2.5 V TT V DDQ Design Guide