Multiple-clock Domain FPGA Designs: Challenges & Solutions
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1 Multiple-clock Domain FPGA Designs: Challenges & Solutions Reuven Dobkin, CTO
2 vsync Circuits EDA & IP Company Mission: Develop and provide our customers with Integration and Verification solutions for Multiple Clock Domain Designs 2
3 Outline Multiple-Clock Domain (MCD) Designs A few anecdotes Tips & Tricks 3 MCD Challenges A note on Vincent (on whom?) 3
4 Multiple Clock Domains? A space example Rad-Hard 64-core DSP-CPU (Ramon Chips Ltd.) DDR3 CDC Sign-off: by vsync CDC Platform Fully Functional after fabrication SpaceFibre SpaceFibre ADC / DAC ADC / DAC SpaceFibre SpaceFibre SpaceWire H NVM, GPIO 4 REF: R. Ginosar, et al., RC64: High Performance Rad-Hard Manycore, ESA DSP Day
5 REF: R. Ginosar, Fourteen Ways to Fool Your Synchronizer, ASYNC 2003 R. Dobkin and R.Ginosar, Fast Universal Synchronizers, PATMOS, Sep D. Verbitsky, R. Dobkin, S. Beer and R. Ginosar, StarSync: An Extendable Standardcell Mesochronous Synchronizer, Integration the VLSI Journal, 2014 R. Dobkin, R. Ginosar and C. Sotiriou, High Rate Data Synchronization in GALS SoCs, IEEE Trans. on VLSI, 14(10): , Oct R. Dobkin and R.Ginosar, Two phase synchronization with sub-cycle latency, INTEGRATION, the VLSI journal, Recall: How to? Make it wrong Avoiding Synchronization One Flop Synchronizer Sneaky Path Greedy Path Flakey Protocol Async Clear DFT Leak Power optimization Leak Pulse Synchronizer Slow-to-Fast Synchronizer Parallel Synchronizer Reconvergence path Conservative Synchronizer Glitching control path Make it correct Universal synchronizer Handshake event driven synchronizer FIFO gray-code based synchronizer Mesochronous synchronizer Periodic Synchronizer Predictive synchronizer Adaptive Synchronizer Local-delay latching synchronizer Asynchronous reset synchronizer Glitch-free gator Glitch-free clock switch Quasi-static synchronizer 6
6 A few notes on FIFO design (1) Eliminate glitching into Sync: Gray Encoder output must be sampled WR_PNT MEMORY RAM or FFs RD_PNT Registered output Registered output WR_PORT WR_PNT _NXT Binary2GrayEnc WR_PNT_CODED Binary2GrayEnc RD_PORT RD_PNT_CODED N-Flop Sync WR_PNT_SYNC Binary2GrayDec Binary2GrayDec RD_PNT_SYNC N-Flop Sync RD_PNT 7
7 A few notes on FIFO design (2) RAM write could be tricky : Check out the RAM specification for write latency MEMORY WR_PNT RD_PNT Registered output RAM Registered output WR_PORT WR_PNT _NXT Binary2GrayEnc WR_PNT_CODED Additional register (only for RAM-configuration) RD_PNT_CODED Binary2GrayEnc RD_PORT N-Flop Sync WR_PNT_SYNC Binary2GrayDec WR_ Binary2GrayDec RD_PNT_SYNC N-Flop Sync RD_PNT 8
8 A few notes on FIFO design (3) Register Read side data output + enable (who knows how it is used further ) MEMORY CDC! Registered output Control EN Registered output WR_PNT FFs WR_ Domain RD_PNT Registered output Not Empty Logic WR_PORT WR_PNT _NXT Binary2GrayEnc WR_PNT_CODED Additional register (only for RAM-configuration) RD_PNT_CODED Binary2GrayEnc RD_PORT N-Flop Sync WR_PNT_SYNC Binary2GrayDec WR_ Binary2GrayDec RD_PNT_SYNC N-Flop Sync RD_PNT 9
9 Asynchronous Reset CDC Reset must meet setup/hold constrains RSTI 1 RST D Q F0 RST D Q F1 Asynchronous Reset Synchronizers RSTO_N (active low) RSTI D Q F0 D Q F1 RSTO Fast clocks Reset distribution network T T T R SU T R Reset Generator / Synchronizer RSTO RST D Q F2 Large designs 10 REF: R. Dobkin, Asynchronous Reset Synchronization and Distribution, embedded.com, 2017
10 An elegant solution: The Clock-Gated Async Reset Synchronizer RSTI RSTI Reset Synchhronizer RSTO RST_ Reset FSM RST SET D Q F1 RST D Q F2 RST G CE EN ICG I O A multi-cycle path _G RST G_LEAF RST D Q F3 RSTI Reset Tree Latency Reset Sync Reset Tree Latency No violation RST_ RST G RST_=1 RST_ST RST_=0 RST G=1 CE=0 COUNTER=0 RST G_LEAF _G COUNTER < MAX COUNT_ST COUNTER = MAX RST G=0 CE=0 CE STATE RST_ST COUNT_ST FINISH_ST FINISH_ST RST G=0 CE=1 11
11 Another Good Approach: Power Up Initialization in FPGA FPGA allows programming memory default state on power up Benefits: A significant reduction of FPGA global resources utilization Elimination of the related timing issues of the asynchronous reset removal Not applicable when: Reset is functional during application run Reset value depends on an external value Technically done by replacing asynchronous resets with signal defaults: VHDL: signal my_signal : std_logic := 0 ; Verilog: reg my_flop = 1 b0; NOT applicable for ASIC! 12
12 Multiple Clock Design Challenges Setup: Clock & Reset requirements... Complexity: design and verification Integration: (Black-box) Third-party IPs 13
13 Getting Requirements Clocks setup Who is Who? Clock relationships Clock sources Async, meso, periodic, etc. Intra Black-box clock manipulations Clock switching (e.g. SpaceWire) Reset setup Who is Who? Reset sequences Power up run G.I.G.O. 14
14 Clock Scheme Impacts Synchronization solution choice CDC verification setup Static Dynamic Reliability verification (MTBF) E.g. correlated / uncorrelated clocks Constraints generation for CDC Sync types Quasi-static CDC Class Df Df Synchronizer Synchronous 0 0 None Mesochronous f c 0 Phase compensation Multi-synchronous drifts 0 Plesiochronous Varies f d <e Adaptive phase compensation Adaptive phase compensation Periodic f d >e Predictive Asynchronous Two-Flop REF: S. Beer, R. Ginosar, R. Dobkin and Y. Weizman, MTBF Estimation in Coherent Clock Domains, ASYNC 19, REF: U.S. Patent ,
15 Clock & Reset Requirements Solutions Challenges Clocks setup Who is Who? Clock relationships Clock sources Async, meso, periodic, etc. Intra Black-box clock manipulations Clock switching Reset setup Who is Who? Reset sequences Power up run Solutions (EDA) Auto Clock and Reset setup Clock & Reset trees auto recognition Vendor-IP recognition (e.g. PLLs) SDC Call for user intervention when needed Multi-modal analysis support Clock-gating / switching 16
16 Multiple Clock Design Challenges Setup: Clock & Reset requirements... Complexity: design and verification Integration: (Black-box) Third-party IPs 17
17 Complexity Key issues Large designs Long runtimes Many clocks Multiple clock relations, large results set Many CDCs A need to design multiple synchronizers Multiple Quasi-Static CDCs Many third-party IPs False alarms, undiscovered CDC issues Many operation modes Long runtimes, enormously large results set 18
18 Complexity Solutions Large designs Parallel exploration, hierarchical analysis Many clocks Automatic-clock recognition, SDC analysis Many CDCs Pre-verified synchronizers (incl. Quasi-Static) Verification support (m/s modeling + coverage) Many third-party IPs Modeling and auto-recognition of the IPs* Many operation modes Shared user data-base for the multiple modes M1 M3 M1 M2 M3 M4 M1 M3 M2 M4 M2 M4 M1 M2 M3 M4 BB Model RESET CLOCK RST0 RST D Q RST1 RST D Q Q0 Q1 19 *REF: U.S. Patent , 2014
19 Multiple Clock Design Challenges Setup: Clock & Reset requirements... Complexity: design and verification Integration: (Black-box) Third-party IPs 20
20 (Black-box) Third-party IPs Key issues Third-party IP modules Open-source Encrypted May have internal synchronization schemes May have internal synchronization bugs May cause CDC bugs, when incorrectly connected Single / Multi-instance connections 21
21 Third-party IP integration Open-code IPs: Hard to dig in someone else s code Thus, it is usually worthwhile to abstract out up to Gray/Silver BB* CDC report shall be jointly reviewed with the vendor Vendor IPs with internal synchronizers: Ask IP vendor to extract all CDCs to a separate, open code hierarchy Analyze/review this open-code with CDC verification tools Static & Dynamic Communicate with IP vendor on possible issues and waivers IP Core (encrypted) IP Synchronizers IP Core (encrypted) IP RAM Blocks (open code) IP RAM Blocks (open code) IP-TOP IP-TOP IP Synchronizers (open code) 22 *REF: U.S. Patent , 2014
22 Dealing with BOTH design and verification vsync Vincent CDC platform LINT RTL Analysis Synchronizer Generator MTBF Computation Dynamic CDC Verification CDC Static Analysis and auto-fix Automatic Constraints Generation 23 23
23 vsync Vincent Platform: A Complete Solution for CDC Thank you!
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