2. BLOCK DIAGRAM Figure 1 shows the block diagram of an Asynchronous FIFO and the signals associated with it.

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1 Volume 115 No , ISSN: (printed version); ISSN: (on-line version) url: ijpam.eu DESIGNING ASYNCHRONOUS FIFO FOR LOW POWER DFT IMPLEMENTATION 1 Avinash Yadlapati and 2 Kakarla Hari Kishore Department of ECE, K L University, Vaddeswaram, Guntur, A.P, India 1 avinash.yadlapati@infosys.com 2 kakarla.harikishore@kluniversity.in ABSTRACT: Asynchronous FIFO s are used for Data Synchronization between two different clock domains, data storage and achieving faster data rates. There have been many papers and designs for Asynchronous FIFO by different authors. This paper focuses primarily on the design of an Asynchronous FIFO for the Implementation of Low Power DFT (Design for Test). Low power is the current challenge of the VLSI Industry and we have already seen many Low Power Techniques in the various phases of the ASIC Design Flow like Architecture, RTL Coding, Synthesis, Physical Design and last but not the least, Design for Test (DFT). In the Design for Test Flow for Low Power, we mainly consider at two phases i.e., Scan Insertion and the ATPG Simulations. The idea of implementing the Low Power Technique is to first design a Asynchronous FIFO and then apply the Low Power DFT Techniques to the Design. This paper primarily focuses on the architecture and simulations of the Asynchronous FIFO. Keyword: Asynchronous FIFO, Pointers, Overrun, under run, Synchronization, Design for Test. 1. INTRODUCTION FIFO stands for first-in first-out and it is used to transfer the data by achieving synchronization [1]. In this paper an asynchronous FIFO is designed for the purpose of implementing the Low Power Design for Test technique. Primarily, there are two types of FIFO. a. Synchronous FIFO b. Asynchronous FIFO In a Synchronous FIFO, there will be a single clock under which the read and write operations take place. In Synchronous FIFO, the execution of read and write operations will be sequential which means that, only after write operation happens, read can follow. Initially, the FIFO will be empty at reset and once the write happens in the location, then read follows. In this design, we have always reset the FIFO to read operation because, the FIFO needs to be empty at reset and that is only possible after read operation. Since, the read and write happens in the same clock, the data transfer will be slow in this case of Synchronous FIFO. In Asynchronous FIFO, there will be two separate clocks for write and read operations. They may operate at different frequencies and the data transfers will be faster in this case. The synchronization between the two different clocks, viz, read and write clocks will happen by using 2-stage synchronizer which is also known as Dual-Flop Synchronizer. The applications of Asynchronous FIFO are primarily for Data Synchronization in high speed data transfers. The main concept of the design implemented in this paper is the way the pointers are handled to generate the over run (fifo_full) and under run (fifo_empty) conditions along with the synchronization of the read pointer and the write pointer. 2. BLOCK DIAGRAM Figure 1 shows the block diagram of an Asynchronous FIFO and the signals associated with it. wr_clk rd_clk wr_en rd_en rst: data_out Overrun Underrun As mentioned earlier we use two different clocks for write_operation and read_operation, i.e., wr_clk and rd_clk are the clocks that are used for write and read operation accordingly. rst signal is used for resetting the FIFO to a known state. As mentioned earlier, the read signal is used to reset the FIFO. During the rst operation, when the rst is enabled high, it will be read operation so that the FIFO is empty and is in known state or IDLE state data_in and data_out are the inout bus signals which are split into input and output buses for testing purpose. data_in is the signal which is the input to the FIFO for writing the data inside the 631

2 FIFO and data_out is the signal which is the output of the read operation i.e., output data of the FIFO during read cycle. Figure 1. Asynchronous FIFO schematic symbol 3. Design OF Asynchronous FIFO This paper details a new architecture which is different from the other designs. The complete design is being carried out using Multiplexer and Flip-Flops. All the outputs are being registered and the RMM (Reuse Methodology Manual) Coding Guidelines have been strictly followed. The entire concept of generation of fifo_full and fifo_empty signals has been generated on a signal by name last_operation. The last_operation can be either read or write operation Read and Write Pointers of Asynchronous FIFO To understand FIFO design architecture, one should understand how these pointers operate. The following is the execution of the read and write pointers along with the last_operation. 1. Initially both read and write pointers of the FIFO point to the zeroth location. 2. The FIFO is in empty or known state. 3. When the wr_en signal is asserted, the write operation starts by incrementing the write pointer. 4. When the read_en signal is asserted (Active Low), the read operation starts and the read pointer is incremented. 5. The last_operation is a single bit signal which indicates if the last operation is read or write. For a synchronous FIFO the underrun and overrun flags are generated using the pointers and the last operation. If the pointers point to the same location and the last operation was a write, the overrun flag is asserted else if the pointers point to the same location and the last operation was a read, the underrun flag is generated. In Asynchronous FIFO the concept of generation of the overrun and underrun flags will be the same as mentioned above, however, since the write and read operate at two different frequencies, it is important that the pointers Figure 2. Architecture of Asynchronous FIFO have to be synchronized Gray Code Converters Gray code converter is used for the synchronization of the read and writes pointers. The other characteristic of gray code comes when representing successive binary numbers, reflecting only one-bitv change for each increment in binary values, thus reducing the switching activity and hence power [4]. The lower switching activity also accomplishes less glitch formation, thus reducing any m e t s t a b i l i t y. 632

3 Figure 3. Gray code sequence The importance of reducing the met stable condition comes when comparing the two pointers (representing 5-bit read and write addresses). By reducing the number of transitions the possibility of interpreting a signal transitioning from 1 to 0 or 0 to 1 as 1 s and 0 s respectively by the combinational logic (xnor gate as an equivalency check) will become easier Synchronizer Overrun is critical for write operation and under run is critical for read operation. Full and empty conditions are critical for write and read inhibition respectively. Overrun and under run conditions are generated based on the read and write pointers position. Being an asynchronous design read and writes operations increment respective pointers with different clock speeds. Synchronization is implemented by reading the gray code write pointer with read clock domain and vice versa. Hence, there s a need for synchronizing the gray code write pointer with read clock and gray code read pointer with write clock. Figure 4 depicts the synchronization mechanism. In general, a 1-bit data is synchronized using two flip- flops. The write data is synchronized with the read clock and the read data will be synchronized with the write clock. By following this mechanism read and writes clock signals are synchronized. Figure 4. Synchronization mechanism 3.4. Generation of Overrun and under run Conditions from Asynchronous Pointers During the write operation, the first step to be checked is to see if the FIFO is full. If the FIFO is full, no write can happen and the write pointer cannot be incremented. This is the overrun condition. This flag is generated when both write and read pointers point to the same location and the last operation was a write. During the read operation, the first step to be checked is to see if the FIFO is empty. If the FIFO is full, no read can happen and the read pointer cannot be incremented. This is the under run condition. This flag is generated when both write and read pointers point to the same location and the last operation was a read Asynchronous FIFO Functionality The read or write operation is done according to the user request, when the user requests a write operation data is loaded into the memory and the location will be specified by the write pointer. When the user requests for a read operation the data that is loaded into the memory is read out. The read and write pointers keep on incrementing until it reaches the last location and again the pointers come to initial location. This being a FIFO the first loaded data will be read out first and so o n. The memory specified in this paper can address n locations and of m-bit wide data. When the user requests for continuous write operation and no read operation the memory will load data until all the n locations are filled and then it remains in the same state i.e. it preserves (Overrun condition), until read enable signal is asserted. If the memory is completely filled and the user requests for a read operation, the data will be read out until there remains no data in the memory. Even the user requests a read operation, the FIFO asserts under run signal and the circuit preserves the state. When there occurs read and write operations 633

4 simultaneously the data that is composed into the memory first will be read out first. The pointers will look after the addresses, to which address of the memory the data is to be sent and from which address of the memory the data is to be read. From figure 2 it s clear that the full and empty status flags are generated by previous operation logic and comparison of gray code pointers using a comparator after synchronization of the read pointer with write clock and viz. The counter used in this design is an n-bit counter and the comparison between the read and write gray code pointers is done as follows: If the pointers are equal and previous operation is write, then Overrun flag is asserted. If the pointers are equal and previous operation is read, then Overrun flag is asserted. into the memory and after write enable is requested there is a continuous write operation and no read operation requested until the FIFO depth is completely filled hence, Overrun flag is asserted. We can find that once the data is loaded into memory there is a deassertion of under run flag. After read operation is requested we can observe that there s de-assertion of Overrun flag. Simultaneous read and write operations are also depicted in Figure 5. Hence,Asynchronous FIFO functionality is verified. Figure 6 shows that under run flag is asserted when the FIFO is read out completely and there is no data. 4. SIMULATION OUTCOME Simulation is being carried out on Cadence NC Simulator, using Verilog as a hardware description language. Different test cases are used to verify the Asynchronous FIFO functionality. Figure 5 shows that Overrun flag is asserted as there s no data initially loaded Figure 6. Under run Flag generation Figure 5. Overrun Flag generation In this paper, new design architecture to implement Asynchronous FIFO using gray counter synchronization and with the help of previous operation is shown. In this design the gray counters use a comparator along with the previous operation for the generation of Overrun and under run status flags. This being an Asynchronous FIFO a lot of effort is required to design and meet the timing and frequencies of the read clock with the write clock and vice versa. This architecture also overcomes the problem of met stability and mean time between failures by using Gray code counters. Continuous writing of data into memory, continuous reading of data from memory and simultaneous reading and writing of data from memory are verified with different test cases. All these test cases are verified using Cadence NCSim. This paper though focuses on the Design of Asynchronous FIFO; the final goal is to make this asynchronous FIFO suitable for implementing the Low Power DFT Techniques. One of the techniques which will be applied in the next version of the paper will be dividing the scan clock for even and odd scan chains and thereby reducing the power consumption. REFERENCES [1] O_architecture. [2] Simulation and synthesis techniques of Async FIFO design, available at Sunburst design Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition. 634

5 [3] HoSuk Han, Kenneth S. Steven, Clocked and asynchronous FIFO characterization and comparison [4] G. Ramesh, V. Shivraj Kumar, K. Jeevan Reddy, Asynchronous FIFO Design with Gray code Pointer for High Speed AMBA AHB Compliant Memory controller, IOSR, volume: 1, issue 3, Nov- Dec 2012 [5] p_documentation/async_fifo.pdf [6] Asynchronous FIFO in virtex-ii FPGA s, available at [6] Asynchronous FIFO architectures by A.Nebhrajani available at, vlsi_book/asynch1.pdf. [7] N Bala Dastagiri, K Hari Kishore "Novel Design of Low Power Latch Comparator in 45nm for Cardiac Signal Monitoring, International Journal of Control Theory and Applications, ISSN No: , Vol No.10, Issue No.28, page: , May 2017 [8] Meka Bharadwaj, Hari Kishore "Enhanced Launch- Off-Capture Testing Using BIST Designs Journal of Engineering and Applied Sciences, ISSN No: X, Vol No.12, Issue No.3, page: , April 2017 [9] Avinash Yadlapati, Hari Kishore Kakarla "Novel Architecture for Designing Asynchronous First in First Out, International Journal of Control Theory and Applications, ISSN No: , Vol No.10, Issue No.8, page: , April 2017 [10] Mahesh Mudavath, K Hari Kishore, D Venkat Reddy "Design of CMOS RF Front-End of Low Noise Amplifier for LTE System Applications Integrating FPGAs Asian Journal of Information Technology, ISSN No: , Vol No.15, Issue No.20, page: , December 2016 [11] Mr. S.V.Manikanthan and K. Srividhya, a Comparative Analysis of Raspberry BasedMetric Using Cloud Computing Techniques, ISSN: Volume 13 Issues 2 MARCH [12] A Murali, K Hari Kishore, D Venkat Reddy "Integrating FPGAs with Trigger Circuitry Core System Insertions for Observability in Debugging Process Journal of Engineering and Applied Sciences, ISSN No: X, Vol No.11, Issue No.12, page: , December [13] S Nazeer Hussain, K Hari Kishore "Computational Optimization of Placement and Routing using Genetic Algorithm Indian Journal of Science and Technology, ISSN No: , Vol No.9, Issue No.47, page: 1-4, December [14] K Hari Kishore, K Akhil, G Viswanath, N Pavan Kumar Design and Implement of 8X8 Multiplier using 4-2 Compressor and 5-2 Compressor, International Journal of Reconfigurable and Embedded Systems, ISSN , Volume 5, Number 3, pp , November 2016 [15] P Bala Gopal, K Hari Kishore An FPGA Implementation of On Chip UART Testing with BIST Techniques, International Journal of Reconfigurable and Embedded Systems, ISSN , Volume 5, Number 3, pp , November 2016 [16] N Bala Gopal, K Hari Kishore "Analysis of Low Power Low Kickback Noise in Dynamic Comparators in Pacemakers Indian Journal of Science and Technology, ISSN No: , Vol No.9, Issue No.44, page: 1-4, November [17] N Bala Gopal, Kakarla Hari Kishore "Reduction of Kickback Noise in Latched Comparators for Cardiac IMDs Indian Journal of Science and Technology, ISSN No: , Vol No.9, Issue No.43, Page: 1-6, November [18] Nidamanuri Sai Charan, Kakarla Hari Kishore "Recognization of Delay Faults in Cluster Based FPGA Using BIST Indian Journal of Science and Technology, ISSN No: , Vol No.9, Issue No.28, Page: 1-7, July [19] Avinash Yadlapati, Hari Kishore Kakarla "Validating Advanced Extensible Interface Protocol using Randomized Verification Environment" Research Journal of Applied Sciences, Engineering and Technology, ISSN No: , Vol No.13, Issue No.1, page: 42-47, July [20] SV Manikanthan and K Srividhya, An Android based secure access control using ARM and cloud computing - Electronics and Communication. 2015, INSPEC , - ieeexplore.ieee.org. [21] Sravya Kante, Hari Kishore Kakarla, Avinash Yadlapati,"Design and Verification of AMBA AHB-Lite protocol using Verilog HDL" International Journal of Engineering and Technology, E-ISSN No: , Vol No.8, Issue No.2, Page: , April-May

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