MCMASTER UNIVERSITY EMBEDDED SYSTEMS

Transcription

1 MCMASTER UNIVERSITY EMBEDDED SYSTEMS Computer Engineering 4DS4 Lecture Revision of Digital Systems Amin Vali January 26 Course material belongs to DrNNicolici

2 Field programmable gate arrays (FPGAs) x x x x M E M M E M logic elements multipliers interconnect wires interconnect switches embedded memory blocks

3 FPGAs logic elements multipliers interconnect wires interconnect switches x x x x M E M M E M embedded memory blocks There may be other physical resources prefabricated in the FPGA, such as digital clock managers (eg, PLLs), fast I/Os, ; note, we focus on the logic blocks Hardwired multipliers available for fast digital signal processing

4 Programmable Logic Logic Elements (s) A generic combinational or sequential function 4-LUT D flipflop Mux configured by an SRAM cell not shown in the figure

5 Programmable Logic Lookup Tables (LUTs) Programmed to any function with n inputs 2 n SRAM Cells to form the truth table SRAM cells 2-LUT 2-LUT 4-LUT

6 Propagation Delay A G Clock speed? B C F ABC: F: (glitch) Clock A B C G F Clock?

7 Timing Parameters Maximum clock frequency influenced by the following timing parameters: register-to-register delay input-to-register delay register-to-output delay input-to-output delay (Mealy only) Inputs Combinational Logic Outs Next state Present state

8 Critical Path Activation Longest propagation delay occurs on the critical path however its activation deps on the processed data A3-A B3-B C C2 C3 A3 B3 A2 B2 A B A B C4 C4 + C3 + C2 + C + S S S3 S2 S S S2 S3 Distance between two clock pulses for the circuit to function properly (in addition to LUT propagation delays, the propagation delays through FFs and the setup time of FFs should be taken in account)

9 Embedded Memories Timing Diagram Single-Port RAM vs Dual-Port RAM Clock A DI value Clock Adress (A) 2 3 we DO RAM() RAM()= value A RAM(2) RAM(3) 4 Data In (DI) value DI2 value2 Write Enable (we) we2 Data Out (DO) RAM() RAM()= value RAM(2) DO2 RAM(5) RAM(6) RAM()= value2 RAM(2) Content from RAM location that was updated during the write cycle Writing on both ports at the same time is NOT permitted!

10 Verilog How to describe a MUX Using continuous assignment Procedural signal assignment module mux_2_to_ (input logic sel, input logic[7:] x, y, output logic[7:] f); assign f = sel? x : y; module module mux_2_to_ (input logic sel, input logic[7:] x, y, output logic[7:] f); always_comb if (sel) f = x; else f = y; module Or module mux_2_to_ (input logic sel, input logic[7:] x, y, output logic[7:] f); always_comb f = y; if (sel) f = x; module

11 Multiple Drivers Problem x y Short circuit between two signal paths: impossible to implement unless the targeted fabric provides some form of resolution for it (not in our case)! sel2 sel f problem module multiple_drivers (input logic sel, sel2, input logic[7:] x, y, output logic[7:] f); always_comb if (sel) f = x; else f = y; always_comb if (sel2) f = y; // bad assignment else f = x; // it will NOT compile module

12 Multiple Drivers Problem The designer MUST decide which signal path takes priority! module multiple_drivers_fixed (input logic sel, sel2, input logic[7:] x, y, output logic[7:] f); logic[7:] g; // internal signal within the module y x sel2 g sel f always_comb if (sel) f = x; else f = g; always_comb if (sel2) g = y; else g = x; module module multiple_drivers_fixed (input logic sel, sel2, input logic[7:] x, y, output logic[7:] f); assign f = sel? x : (sel2? y : x); module

13 Priority Encoders z y c3 x c2 w c f module priority_encoder (input logic c, c2, c3, input logic[7:] w, x, y, z, output logic[7:] f); always_comb if (c) f = w; else if (c2) f = x; else if (c3) f = y; else f = z; module module priority_encoder (input logic c, c2, c3, input logic[7:] w, x, y, z, output logic[7:] f); always_comb f = z; if (c3) f = y; if (c2) f = x; if (c) f = w; module

14 Sequential Logic Fundamental sequential element - edge-triggered Data (or D) flip-flop with asynchronous reset (active low) Combinational logic can be described either using continuous assignments or procedural assignments in always or always_comb blocks Sequential logic can be described using always or always_ff blocks Latches can be described using always or always_latch blocks module d_flip_flop (input logic clock, resetn, input logic d, output logic q); clock or negedge resetn) // sensitivity list if (!resetn) q <= 'b; else q <= d; // this is a non-blocking assignment

15 Registers 8-bit register with synchronous enable All the signals on the left hand side of non-blocking procedural assignments in always_ff blocks will up as state elements (flip-flops)! IMPORTANT coding conventions: in always_comb blocks use only blocking assignments in always_ff blocks use only non-blocking assignments module enabled_register (input logic clock, resetn, input logic en, input logic[7:] d, output logic[7:] q); clock or negedge resetn) if (resetn == 'b) // different way to test for active low q <= 8'b_; else if (en == 'b) q <= d; module

16 Counters 8-bit modulo 2 up counter module modulo_counter (input logic clock, resetn, input logic en, output logic[7:] count); logic load; clock or negedge resetn) if (!resetn) count <= 8'h; else if (en) if (load) count <= 8'h; else count <= count + 8'd; assign load = (count == 8'd2); module

17 Counters 8-bit modulo 2 up counter Equivalent code with present_count and next_count module modulo_counter (input logic clock, resetn, input logic en, output logic[7:] count); =2 en load next_count count clock present_count + logic[7:] present_count, next_count; assign count = present_count; clock or negedge resetn) Begin if (!resetn) present_count <= 8'h; else if (en) present_count <= next_count; // non-blocking assignment always_comb : next_state_logic // this is a label for naming a block logic load; // declare a signal only for this block load = (present_count == 8'd2); // blocking assignment if (load) next_count = 8'h; else next_count = present_count + 8'd;

18 Verilog s non-blocking <= assign Signal a driven in block Signal b receives old a value always_ff (@posedge clk ) OR always (@posedge clk ) + Wrong a <= a+ ; b <= a; a b

19 Shift Register data_in[5] data_in[4] data_in[] data_in[] serial_in load data_out[2] serial_out clock data_out[5] data_out[4] data_out[] data_out[] Signal concatenation: R<={ Sin,R[5:] } Shift operator: R <= R >> Verilog for loop: R[i] <= R[i+]

20 Shift Register `define DATA_WIDTH 6 // used outside the module to // parameterize the design ports module shift_register (input logic resetn, clock, serial_in, load, input logic[`data_width-:] data_in, output logic serial_out, output logic[`data_width-:] data_out); // right shift register clock or negedge resetn) if (!resetn) data_out <= {`DATA_WIDTH{'b}}; // signal concatenation // equivalent to: data_out <= `DATA_WIDTH'd; else if (load) data_out <= data_in; else : right_shift // label for a block of statements integer i; // integer variable used as an iterator for (i=`data_width-; i>; i=i-) data_out[i-] <= data_out[i]; data_out[`data_width-] <= serial_in; // alternative code based on signal concatenation /* data_out[`data_width-:] <= {serial_in, data_out[`data_width - : ]}; */ // alternative code based on the >> operator /* data_out <= (data_out >> ); data_out[`data_width-] <= serial_in; */ assign serial_out = data_out[]; module

21 Control/Data Path Control Path Finite state machine (FSM) Decisions and timing Synchronous enable, load shift enable, control inputs control path (finite state machine) control outputs control signals status signals data inputs data path (registers, arithmetic/ logic units, shift registers, counters, ) data outputs Data Path registers, arithmetic units (adders, multipliers), logic units, shift registers, counters, comparators, embedded memories, Comparator results, zero detect,

22 FSM Up/down 2-bit counter with zero detect module fsm (input logic clock, resetn, w, output logic z); logic[:] state; parameter S = 2'b; parameter S = 2'b; parameter S2 = 2'b; parameter S3 = 2'b; (posedge clock or negedge resetn) if (!resetn) state <= S; else case (state) S: if (w) state <= S; else state <= S3; S: if (w) state <= S2; else state <= S; S2: if (w) state <= S3; else state <= S; S3: if (w) state <= S; else state <= S2; case w S3/ z= w w w S/ z= S2/ z= w w w S/ z= w assign z = (state == S); module

23 Exercise Given the enclosed source code, draw the equivalent hardware circuit module problem (input logic resetn, clock, input logic load, serial_in, output logic parity); input logic start, stop, input logic [7:] parallel_in, logic shift_left; logic[7:] shift_register; clock or negedge resetn) if (!resetn) shift_left <= 'b; shift_register <= 8'd; else if (start) shift_left <= 'b; if (stop) shift_left <= 'b; if (shift_left) shift_register <= {shift_register[6:],serial_in}; else if (load) shift_register <= parallel_in; module always_comb parity = ^shift_register;

24 Exercise Consider an array A containing 6 bit signed numbers stored in one memory with 256 locations with 6 bits per location Element A[i] is stored in location i Design a digital circuit that computes an array B as follows: B[i]=(A[i-] 2*A[i] + 4*A[i+])/4 It is assumed that A[-] = A[] and A[256] = A[255] As soon as it is available, element B[i] will replace A[i] in memory location i Assume that the memory is a single-port RAM with one clock cycle latency The aim is to reduce the number of clock cycles required to complete the calculation Repeat the above problem by replacing the single-port RAM with a dual-port RAM