Rechnerstrukturen

Transcription

1 Rechnerstrukturen Institut für Technische Informatik Treitlstraße 3, 1040 Wien 1

2 incl. CD-ROM < 50 e-book version available

3 Further reading

4 Organisatorisches Vorlesungen An Dienstagen, 10:00 12:00, Hörsaal EI 10 An Donnerstagen, 09:00 11:00, Hörsaal EI 4 3 VO 2 x 2 VO bis Dezember Prüfungen Mündlich/schriftlich? Anmeldung über TISS 4

5 Studienplan Semester Fach 1. VU Grundlagen digitaler Systeme 3. VO Rechnerstrukturen VO+UE Betriebssysteme 4. VO Digital Design 5. LU Digital Design & Computer Architecture 5

6 Chapter 1 Computer Abstractions and Technology 6

7 The Computer Revolution Progress in computer technology Underpinned by Moore s Law Makes novel applications feasible Computers in automobiles Cell phones Human genome project World Wide Web Search Engines Computers are pervasive 1.1 Introduction 7

8 Classes of Computers Desktop computers General purpose, variety of software Subject to cost/performance tradeoff Server computers, Supercomputers Network based High capacity, performance, reliability Range from small servers to building sized Embedded computers (processors) Hidden as components of systems Stringent power/performance/cost constraints 8

9 Embedded Processor Characteristics The largest class of computers spanning the widest range of applications and performance Often have minimum performance requirements. Often have stringent limitations on cost. Often have stringent limitations on power consumption. Often have low tolerance for failure. 9

10 The Processor Market manufactured/year 2010: 3x Rechnerstrukturen 9 TV, > 5 x10 1 Computer 9 cell phones, >1x10 Abstractions and Technology 9 PCs; 7x10 9 population 10

11 What You Will Learn How programs are translated into the machine language And how the hardware executes them The hardware/software interface What determines program performance And how it can be improved How hardware designers improve performance What is parallel processing 11

12 Understanding Performance Algorithm Determines number of operations executed Programming language, compiler, architecture Determine number of machine instructions executed per operation Processor and memory system Determine how fast instructions are executed I/O system (including OS) Determines how fast I/O operations are executed 12

13 Below your Program Application software Written in high-level language System software Compiler: translates HLL code to machine code Operating System: service code Handling input/output Managing memory and storage Scheduling tasks & sharing resources Hardware Processor, memory, I/O controllers 1.2 Below Your Program 13

14 Levels of Program Code High-level language Level of abstraction closer to problem domain Provides for productivity and portability Assembly language Textual representation of instructions Hardware representation Binary digits (bits) Encoded instructions and data One-to-many One-to-one 14

15 Components of a Computer The BIG Picture Datapath + Control = Processor (CPU) Same components for all kinds of computer Desktop, server, embedded Input/output includes User-interface devices Display, keyboard, mouse Storage devices Hard disk, CD/DVD, flash Network adapters For communicating with other computers 1.3 Under the Covers 15

16 Anatomy of a Computer Output device Network cable Input device Input device 16

17 Opening the Box 17

18 Inside the Processor (CPU) Datapath: performs operations on data Control: sequences datapath, memory,... Cache memory Small fast SRAM memory for immediate access to data 18

19 Inside the Processor AMD Barcelona: 4 processor cores (Intel Nehalem µ-architecture) 1.9 GHz, 65 nm technology, L1, L2, L3, integrated Northbridge, 4 OoO cores 19

20 Abstractions The BIG Picture Abstraction helps us deal with complexity Hide lower-level detail Instruction set architecture (ISA) The hardware/software interface Application binary interface The ISA plus system software interface Implementation The details underlying and interface 20

21 Instruction Set Architecture (ISA) ISA, or simply architecture the abstract interface between the hardware and the lowest level software that encompasses all the information necessary to write a machine language program, including instructions, registers, memory access, I/O, Enables implementations of varying cost and performance to run identical software The combination of the basic instruction set (the ISA) and the operating system interface is called the application binary interface (ABI) ABI The user portion of the instruction set plus the operating system interfaces used by application programmers. Defines a standard for binary portability across computers. 21

22 A Safe Place for Data Volatile main memory Loses instructions and data when power off Non-volatile secondary memory Magnetic disk ( 1 TB) Flash memory ( 256 GB) Optical disk (CDROM, DVD, BlueRay) 22

23 Networks Communication and resource sharing Local area network (LAN): Ethernet Within a building Wide area network (WAN): the Internet Wireless network: WiFi, Bluetooth 23

24 Moore s Law In 1965, Intel s Gordon Moore predicted that the number of transistors that can be integrated on single chip would double about every two years. (DRAM x4 every 3 years) 24

25 Technology Trends Electronics technology continues to evolve (beyond CMOS) Increased capacity and performance Reduced cost Year Technology Relative performance/cost 1951 Vacuum tube Transistor Integrated circuit (IC) Very large scale IC (VLSI) 2,400, Ultra large scale IC 6,200,000,000 = 6.2x

26 Moore s Law (2) Dual Core Itanium (IA 64) with 1.7x10 9 transistors Feature Size, Die Size 26

27 DRAM capacity growth [b] 64M 256M 128M 512M 1G 1M 4M 16M 64K 16K 256K x4 every 3 years 27

28 v( CPU ) > v( DRAM ) Cache Memory 28

29 Technology Scaling Road Map (ITRS) Year Feature size (nm) Integration Capacity (10 9 Transistors) nm technology 30 million devices fit on the head of a pin > 2,000 across the width of a human hair If car prices had fallen at the same rate as the price of a single transistor has since 1968, a new car today would cost about 1 cent. 29

30 Defining Performance Which airplane has the best performance? 1.4 Performance Boeing 777 Boeing 777 Boeing 747 BAC/Sud Concorde Douglas DC-8-50 Boeing 747 BAC/Sud Concorde Douglas DC Passenger Capacity Cruising Range (miles) Boeing 777 Boeing 777 Boeing 747 BAC/Sud Concorde Douglas DC-8-50 Boeing 747 BAC/Sud Concorde Douglas DC Cruising Speed (mph) Passengers x mph 30

31 Response Time and Throughput Response time How long it takes to do a task Throughput Total work done per unit time e.g., tasks/transactions/ per hour How are response time and throughput affected by Replacing the processor with a faster version? Adding more processors? We ll focus on response time for now 31

32 Relative Performance Define Performance = 1/Execution Time X is n time faster than Y Performance X Execution time Performance = Y X Y Execution time = n Example: time taken to run a program 10s on A, 15s on B Execution Time B / Execution Time A = 15s / 10s = 1.5 So A is 1.5 times faster than B 32

33 Measuring Execution Time Elapsed time Total response time, including all aspects Processing, I/O, OS overhead, idle time Determines system performance CPU time Time spent processing a given job Discounts I/O time, other jobs shares Comprises user CPU time and system CPU time Different programs are affected differently by CPU and system performance 33

34 CPU Clocking Operation of digital hardware governed by a constant-rate clock Clock (cycles) Data transfer and computation Update state Clock period Clock period: duration of a clock cycle e.g., 250ps = 0.25ns = s Clock frequency (rate): cycles per second e.g., 4.0GHz = 4000MHz = Hz 34

35 CPU Time CPU Time = # CPU Clock Cycles Clock Cycle Time # CPU Clock Cycles = Clock Rate Performance improved by Reducing number of clock cycles Increasing clock rate Hardware designer must often trade off clock rate against cycle count 35

36 CPU Time Example Computer A: 2GHz clock, 10s CPU time Designing Computer B Aim for 6s CPU time Can do faster clock, but causes 1.2 clock cycles How fast must Computer B clock be? Clock Rate B = Clock Cycles CPU Time B B = 1.2 Clock Cycles 6s A Clock Cycles A = CPU Time A Clock Rate A = 10s 2GHz = Clock Rate B = s 9 = s 9 = 4GHz 36

37 Instruction Count and CPI Clock Cycles = Instruction Count Cycles per Instruction CPU Time = = Instruction Count CPI Clock Cycle Time Instruction Count CPI Clock Rate Instruction Count for a program Determined by program, ISA and compiler Average cycles per instruction Determined by CPU hardware If different instructions have different CPI Average CPI affected by instruction mix 37

38 CPI Example Computer A: Cycle Time = 250ps, CPI = 2.0 Computer B: Cycle Time = 500ps, CPI = 1.2 Same ISA Which is faster, and by how much? CPU Time A CPU Time B CPU Time B CPU Time A = Instruction Count CPI A = I ps = I 500ps = Instruction Count CPI B = I ps = I 600ps I 600ps = I 500ps = 1.2 Cycle Time A Cycle Time B A is faster by this much 38

39 CPI in More Detail If different instruction classes take different numbers of cycles Clock Cycles = n i= 1 (CPI Instruction Count i i) Weighted average CPI CPI = Clock Cycles Instruction Count = n i= 1 CPI i Instruction Counti Instruction Count Relative frequency 39

40 CPI Example Alternative compiled code sequences using instructions in classes A, B, C Class A B C CPI for class IC in sequence IC in sequence Sequence 1: IC = 5 Clock Cycles = = 10 Avg. CPI = 10/5 = 2.0 Sequence 2: IC = 6 Clock Cycles = = 9 Avg. CPI = 9/6 =

41 Performance Summary The BIG Picture Instructions Clock cycles CPU Time = Program Instruction Seconds Clock cycle Performance depends on Algorithm: affects IC, possibly CPI Programming language: affects IC, CPI Compiler: affects IC, CPI Instruction set architecture: affects IC, CPI, T c 41

42 Determinates of CPU Performance CPU time = Instruction_count x CPI x clock_cycle Instruction_ count CPI clock_cycle Algorithm X X Programming language X X Compiler X X ISA X X X Core organization X X Technology X 42

43 Power Trends (Limits) Power Wall 1.5 The Power Wall In CMOS IC technology 2 Power = Capacitive Load Voltage Frequency 1 Pc f CU V 1V

44 Reducing Power Suppose a new CPU has 85% of capacitive load of old CPU 15% voltage and 15% frequency reduction 2 P Cold 0.85 (Vold 0.85) Fold = = P C V F new = old The power wall old We can t reduce voltage further We can t remove more heat old How else can we improve performance? old

45 Uniprocessor Performance Constrained by power, instruction-level parallelism, memory latency 1.6 The Sea Change: The Switch to Multiprocessors 45

46 Multiprocessors Multicore microprocessors More than one processor per chip Requires explicitly parallel programming Compare with instruction level parallelism Hardware executes multiple instructions at once Hidden from the programmer Hard to do Programming for performance Load balancing Optimizing communication and synchronization 46

47 A Sea Change is at Hand The power challenge has forced a change in the design of µ-processors Since 2002 the rate of improvement in the response time of programs on desktop computers has slowed from a factor of 1.5 per year to less than a factor of 1.2 per year As of 2006 all desktop and server companies are shipping µ-processors with multiple processors (cores) per chip 47

48 A Sea Change is at Hand (2) Product AMD Barcelona Intel IA-64 Nehalem IBM Power 6 Sun Niagara 2 Cores per chip Clock rate 2.5 GHz ~2.5 GHz? 4.7 GHz 1.4 GHz Power 120 W ~100 W? ~100 W? 94 W Plan of record is to double the number of cores per chip per generation (about every two years) 48

49 Manufacturing ICs 300 mm (450 mm) 1.7 Real Stuff: The AMD Opteron X4 Yield: proportion of working dies per wafer 49

50 50

51 AMD Opteron X2 Wafer X2: 300 mm wafer, 117 chips, 90 nm technology X4: 45 nm technology 51

52 Integrated Circuit Cost Cost per die = Cost per wafer Dies per wafer Yield Dies per wafer Wafer area Die area Yield = (1+ (Defects per 1 area Die area/2)) 2 Nonlinear relation to area and defect rate Wafer cost and area are fixed Defect rate determined by manufacturing process Die area determined by architecture and circuit design 52

53 SPEC CPU Benchmark Programs used to measure performance Supposedly typical of actual workload Standard Performance Evaluation Corp (SPEC) Develops benchmarks for CPU, I/O, Web, SPEC CPU2006 Elapsed time to execute a selection of programs Negligible I/O, so focuses on CPU performance Normalize relative to reference machine Summarize as geometric mean of performance ratios CINT2006 (integer) and CFP2006 (floating-point) n n Execution time ratio i i= 1 53

54 CINT2006 for Opteron X Name Description IC 10 9 CPI Tc (ns) Exec time Ref time SPECratio perl Interpreted string processing 2, , bzip2 Block-sorting compression 2, , gcc GNU C Compiler 1, , mcf Combinatorial optimization ,345 9, go Go game (AI) 1, , hmmer Search gene sequence 2, , sjeng Chess game (AI) 2, , libquantum Quantum computer simulation 1, ,047 20, h264avc Video compression 3, , omnetpp Discrete event simulation , astar Games/path finding 1, , xalancbmk XML parsing 1, ,143 6, Geometric mean 11.7 High cache miss rates 54

55 SPEC Power Benchmark Power consumption of server at different workload levels Performance: ssj_ops/sec Power: Watts (Joules/sec) Overall ssj_ops per Watt ssj_ops i power i= 0 = i= 0 i 55

56 SPECpower_ssj2008 for X4 Target Load % Performance (ssj_ops/sec) Average Power (Watts) 100% 231, % 211, % 185, % 163, % 140, % 118, % 920, % 70, % 47, % 23, % Overall sum 1,283,590 2,605 ssj_ops/ power

57 Pitfall: Amdahl s Law Improving an aspect of a computer and expecting a proportional improvement in overall performance T improvement affected T improved = + factor unaffected Example: multiply accounts for 80s/100s How much improvement in multiply performance to get 5 overall? = + 20 Can t be done! n T 1.8 Fallacies and Pitfalls Corollary: make the common case fast 57

58 Fallacy: Low Power at Idle Look back at X4 power benchmark At 100% load: 295W At 50% load: 246W (83%) At 10% load: 180W (61%) Google data center Mostly operates at 10% 50% load At 100% load less than 1% of the time Consider designing processors to make power proportional to load 58

59 Pitfall: MIPS as a Performance Metric MIPS: Millions of Instructions Per Second Doesn t account for Differences in ISAs between computers Differences in complexity between instructions MIPS Instruction count = Execution time 10 = Instruction count Instruction count CPI 10 Clock rate 6 6 = Clock rate 6 CPI 10 CPI varies between programs on a given CPU 59

60 Concluding Remarks Cost/performance is improving Due to underlying technology development Hierarchical layers of abstraction In both hardware and software Instruction set architecture The hardware/software interface Execution time: the best performance measure Power is a limiting factor Use parallelism to improve performance 1.9 Concluding Remarks 60