Computer Organization and Design: The Hardware/Software Interface by Patterson and Hennessy

Transcription

1 Computer Organization and Design: The Hardware/Software Interface by Patterson and Hennessy Chapter 1: Computer Abstraction and Technology Gi-Ho Park Dept. of Computer Engineering Sejong University 1

2 1. Computer Abstractions and Technology 1.1 Introduction 1.2 Eight Great Ideas in 1.3 Below Your Program 1.4 Under the Covers 1.5 Technologies for Building Processors and Memory 1.6 Performance 1.7 The Power Wall 1.8 The Sea Change: The Switch from Uniprocessor to Multiprocessor 1.9 Real Stuff: Benchmarking the Intel Core i Fallacies and Pitfalls 1.11 Concluding Remarks 1.12 Historical Perspective and Further Reading 1.13 Exercises 2

3 1 장내용소개 Chap. 1: Computer Abstraction and Technology 컴퓨터의종류및구성 (5 가지 components) 본강좌를통하여무엇을배우는가? 성능 (Performance) 이란? Algorithm, PL/compiler/arch., Proc./Mem., I/O system (H/W, OS) Abstraction, Principle of Abstraction ISA (Instruction Set Architecture) 컴퓨터기반기술 (Technology) 의발전과 Power Wall, Multicore System Chap 1 학습목표 컴퓨터의기본동작원리및컴퓨터시스템설계시에기반이되는개념에대한이해 프로그램이컴퓨터에서어떤과정을거쳐서수행되는가에대한학습 성능의개념및멀티코어시스템, Power Wall 등최신시스템설계의주요동향및이슈에대한이해 3

4 1.1 Introduction The Computer Revolution Third revolution of civilization 1 st : Agricultural, 2 nd : Industrial Makes novel applications feasible (In the recent past those applications were computer science fiction.) Automatic teller machine (ATM) (in 1950 s cheapest computer: $500,000, size of a car) Computers in automobiles Laptop computers Human genome project Cell phones World Wide Web Search Engines Computers are pervasive 4

5 Classes of Computers (1) 1. Personal computers Good performance to a single user at low cost General purpose Execute third-party software Subject to cost/performance trade-off 2. Servers Modern form of mainframes, mini- and supercomputers Network based High capacity, performance, reliability Range from small servers to building sized 5

6 Classes of Computers (2) 3. Embedded computers A computer inside another device used for running one predetermined application or collection of software (Hidden as a components of system) Include microprocessor in washing machine, car, the computer in cell phone,, or PDA (Personal digital assistant), video games, airplane, cargo ship. Tight power/performance/cost constraint 6

7 The PostPC Era (1) 7

8 The PostPC Era (2) Personal Mobile Device (PMD) Battery operated Connects to the Internet Hundreds of dollars Smart phones, tablets, electronic glasses Cloud computing Warehouse Scale Computers (WSC) Software as a Service (SaaS) Portion of software run on a PMD and a portion run in the Cloud Amazon and Google 8

9 What You Can Learn By the time you complete this class, you will be able to answ er the following questions. How are programs written in a high level language such as C or Java, translated into the machine language and how the hardwa re executes them? What is the interface between the software and hardware, and h ow does software interact the hardware to perform needed func tions? What determines the performance of a program and how it can a programmer improve the performance? What techniques can be used by hardware designers to ve performance? What techniques can be used by hardware designers to improve energy efficiency? What is parallel processing? impro What great ideas did computer architects come up with that lay the foundation of modern computing? 9

10 Understanding Performance 10

11 1.2 Eight Great Ideas in Design for Moore s Law Use abstraction to simplify design Make the common case fast Performance via parallelism Performance via pipelining Performance via prediction Hierarchy of memories Dependability via redundancy 11

12 1.3 Below Your Program Application software Written in high-level language System software Compiler: translates HLL code to machine code Operating System(OS): service code Hardware Handling input/output Managing memory and storage Scheduling tasks & sharing resources Processor, memory, I/O controllers 12

13 Levels of Program Code High-level language Level of abstraction is very high (problem domain) Provides productivity and portability Assembly language Symbolic (textual) representation of instructions Machine language (Hardware representation) Binary digits (bits) Encoded instructions and data 13

14 1.4 Under the Covers The BIG Picture Five Classic Components of a Computer Input Output Memory Datapath Control You can place every piece of every computer (desktop, server, embedded), past and present, into one of these five categories. Input/output includes User-interface devices Display, keyboard, mouse Storage devices Hard disk, CD/DVD, flash Network adapters For communicating with other computer 14

15 Through the Looking Glass CRT (Cathode Ray Tube) display Refresh rate 30 to 75 times per second LCD (Liquid Crystal Display) LCD pixel is not the source of light. Rod-shaped molecules Active matrix LCD Raster refresh buffer or frame buffer 15

16 Touchscreen PostPC device Supersedes keyboard and mouse Resistive and Capacitive types Most tablets, smart phones use capacitive Capacitive allows multiple touches simultaneously 16

17 Opening the Box Capacitive multitouch LCD screen 3.8 V, 25 Watt-hour battery Computer board 17

18 Inside the Processor (CPU) Datapath: performs operations on data Control: sequences datapath, memory,... Cache memory Small fast SRAM memory for immediate access to data 18

19 Inside the Processor Apple A5 19

20 Abstractions Abstraction helps us deal with complexity A model that renders lower-level details of computer systems temporarily invisible in order to facilitate design of sophisticated systems. Instruction set architecture (ISA, =Architecture) Interface between hardware and lowest level software Separate functionality from implementation Application Binary Interface (ABI) The combination of the basic instruction set and the operating system interface provided for application programmer Implementation Hardware that obeys the architecture abstraction 20

21 Abstractions The BIG Picture Principle of abstraction Both hardware and software consist of hierarchical layers, with each lower layer hiding details from the level above. The way both hardware designers and software designers cope with the complexity of computer systems. Instruction set architecture: one key interface between the hardware and low-level software. This abstract interface enables many implementations of varying cost and performance to run identical software. 21

22 A Safe Place for Data Main memory (=primary memory) Volatile Mainly DRAMs since 1975 Magnetic disk Dominating secondary memory since 1965 Nonvolatile Removable storage technologies Optical disks (Compact disk (CD), Digital video disk (DVD), Rewritable CD/DVD) Magnetic tape FLASH-based memory cards Floppy drives and Zip drives 22

23 Communication with Other Computers Major advantages of networked computers Communication Resource sharing Non-local access Local area network (LAN): Ethernet Within a building Wide area network (WAN): the Internet Wireless network: WiFi, Bluetooth 23

24 1.5 Technologies for Building Processors and Memory Electronics technology continues to evolve Increased capacity and performance Reduced cost DRAM capacity Year Technology Relative performance/cost 1951 Vacuum tube Transistor Integrated circuit (IC) Very large scale IC (VLSI) 2,400, Ultra large scale IC 250,000,000,000 24

25 1.5 Technologies for Building Processors and Memory Source: Charles P. Tracker, ISCA 2010 Keynote Presentation, June

26 Semiconductor Technology Silicon: semiconductor Add materials to transform properties: Conductors Insulators Switch 26

27 Computer VS. Other Industry If the automobile industry advanced as rapidly as the semiconductor industry, a Rolls Royce would get ½ million miles per gallon and it would be cheaper to throw it away than to park it. Gordon Moore, Intel Corporation Source: Yan Solihin, Fundamentals of Parallel, 2008 Had the transportation industry kept pace with the computer industry, for example, today we could travel from New York to London in a second for a penny. living in Tahiti while working in San Francisco, going for Moscow for an evening at the Bolshoi Ballet and you can appreciate the implications of such a change. - in our text book 27

28 Manufacturing ICs Yield: proportion of working dies per wafer 28

29 Intel Core i7 Wafer 300mm(12-inch) wafer, 280 chips, 32nm technology Each chip is 20.7 x 10.5 mm 29

30 Integrated Circuit Cost Cost per die Cost Dies per per wafer wafer Yield Dies per wafer Wafer area Die area Yield (1 (Defects per 1 area 2 Die area/2)) Nonlinear relation to area and defect rate Wafer cost and area are fixed Defect rate determined by manufacturing process Die area determined by architecture and circuit design 30

31 1.6 Performance How to measure, report, and summarize performance An analogy Defining Performance 31

32 Defining Performance Which airplane has the best performance? Boeing 777 Boeing 777 Boeing 747 BAC/Sud Concorde Douglas DC-8-50 Boeing 747 BAC/Sud Concorde Douglas DC Passenger Capacity Cruising Range (miles) Boeing 777 Boeing 777 Boeing 747 BAC/Sud Concorde Douglas DC-8-50 Boeing 747 BAC/Sud Concorde Douglas DC Cruising Speed (mph) Passengers x mph 32

33 Response Time and Throughput Response time ( = execution time ) The time between the start and completion of a task How long it takes to do a task Throughput The total amount of a work done in a given time Eg. Tasks/transactions/.. per hour How are response time and throughput affect by Replacing the processor with a faster version Adding more processor? We will focus on response time for now.. 33

34 Relative Performance Define Performance = 1/Execution Time X is n time faster than Y Performance X Execution time Performance Y Y Execution time X n Example: time taken to run a program 10s on A, 15s on B Execution TimeB / Execution TimeA = 15s / 10s = 1.5 So A is 1.5 times faster than B 34

35 Measuring Performance: Execution Time Elapsed time Total response time, including all aspects Processing, I/O, OS overhead, idle time Determines system performance CPU time Time spent processing a given job Discounts I/O time, other jobs shares Comprises user CPU time and system CPU time Different programs are affected differently by CPU and system performance This chapter focuses on user CPU time Definitions of performance System performance: based on elapsed time CPU performance: based on user CPU time 35

36 CPU Clocking Operation of digital hardware governed by a constant-rate clock Clock (cycles) Data transfer and computation Update state Clock period Clock period: duration of a clock cycle e.g., 250ps = 0.25ns = s Clock frequency (rate): cycles per second e.g., 4.0GHz = 4000MHz = Hz 36

37 CPU Performance and Its Factors CPU Execution Time CPU Clock Cycles Clock Cycle Time CPU Clock Cycles Clock Rate Performance improved by Reducing number of clock cycles Increasing clock rate Hardware designer must often trade off clock rate against cycle count 37

38 Example: CPU Time Computer A: 2GHz clock, 10s CPU time Designing Computer B Aim for 6s CPU time Can do faster clock, but causes 1.2 clock cycles How fast must Computer B clock be? Clock Rate Clock Cycles B A Clock Cycles CPU Time CPU Time A B B 1.2 Clock Rate Clock Cycles 6s A A 10s 2GHz Clock Rate B s s 9 4GHz 38

39 Instruction Performance (Instruction Count and CPI) Clock Cycles Instruction Count(IC) Cycles per Instruction CPU Time Instruction CountI(IC) CPI Clock Cycle Time Instruction Count(IC) CPI Clock Rate Instruction Count (IC) for a program Determined by program, ISA and compiler Average cycles per instruction (CPI) Determined by CPU hardware If different instructions have different CPI Average CPI affected by instruction mix 39

40 Example: CPI Example Same instruction set architecture, same program Clock cycle time A = 250ps, CPI A = 2.0 Clock cycle time B = 500ps, CPI B = 1.2 Which is faster, and by how much? CPUTim e A CPUTim e B CPUTim e B CPUTim e A Ins truction Count CPI Cycle Time A A I ps I500ps Ins truction Count CPI CycleTime B B I ps I 600ps I 600ps 1.2 I500ps A is faster by this much 40

41 The Classic CPU Performance Equation (CPI in More Detail) If different instruction classes take different numbers of cycles Clock Cycles n i1 (CPI Instruction Count i i) Weighted average CPI Weighted average CPI CPI Clock Cycles Instruction Count n i1 CPI i Instruction Counti Instruction Count Relative frequency 41

42 Example: Comparing Code Segments Which will be faster? What is the CPI for each sequence? Class A B C CPI for class IC in sequence IC in sequence instruction count 1 = = 5 and instruction count 2 = = 6 Thus (1) executes fewer instructions. CPU clock cycles 1 = 2x1 + 1x2 + 2x3 = 10 and CPU clock cycles 2 = 4x1 + 1x2 + 1x3 = 9 Thus (2) is faster. CPI 1 = CPU clock cycles 1 / instruction count 1 = 10 / 5 =2 CPI 2 = 9 / 6 = 1.5 (2) has lower CPI. 42

43 Performance Summary The BIG Picture CPU Time Instructions Program Clock cycles Instruction Seconds Clock cycle Performance depends on Algorithm: affects IC, possibly CPI Programming language: affects IC, CPI Compiler: affects IC, CPI Instruction set architecture: affects IC, CPI, T c 43

44 1.7 The Power Wall: Power Trends In CMOS IC technology Power Capacitive load Voltage 2 Frequency 30 5V 1V

45 Reducing Power Suppose a new CPU has 85% of capacitive load of old CPU 15% voltage and 15% frequency reduction 2 Pnew Cold 0.85(Vold 0.85) Fold P C V F old The power wall old old We can t reduce voltage further We can t remove more heat How else can we improve performance old

46 1.6 The Sea Change: The Switch from Uniprocessor to Multiprocessors: Uniprocessor Performance Constrained by power, instruction-level parallelism, memory latency 46

47 Multiprocessors Multicore microprocessors More than one processor per chip Requires explicitly parallel programming Compare with instruction level parallelism Hardware executes multiple instructions at once Hidden from the programmer Hard to do Programming for performance Load balancing Optimizing communication and synchronization 47

48 Sea Change in Chip Design Intel 4004 (1971): 4-bit processor, 2312 transistors, 0.4 MHz, 10 micron PMOS, 11 mm 2 chip RISC II (1983): 32-bit, 5 stage pipeline, 40,760 transistors, 3 MHz, 3 micron NMOS, 60 mm 2 chip 125 mm 2 chip, micron CMOS = 2312 RISC II+FPU+Icache+Dcache RISC II shrinks to ~ 0.02 mm 2 at 65 nm Caches via DRAM or 1 transistor SRAM ( Proximity Communication via capacitive coupling at > 1 TB/s? (Ivan Sun / Berkeley) Processor is the new transistor? 48

49 Recent Processor Evolution Power GHz 130nm 174M Tr. 267 mm 2 2 Cores 2001 Power GHz 90nm 276M Tr. 389 mm 2 2 Cores 2005 i7 2.7 GHz 45nm 731M Tr. 263mm 2 4 Cores x 2 SMT 2008 i5 3.4 GHz 32nm 382M Tr. 81mm 2 2C x 2T 2010 Source: Kathryn McKinley Keynote Speech Presentation, HPCA

50 SPEC CPU Benchmark Programs used to measure performance Supposedly typical of actual workload Standard Performance Evaluation Corp (SPEC) Develops benchmarks for CPU, I/O, Web, SPEC CPU2006 Elapsed time to execute a selection of programs Negligible I/O, so focuses on CPU performance Normalize relative to reference machine Summarize as geometric mean of performance ratios CINT2006 (integer) and CFP2006 (floating-point) n n Execution timeratio i i1 50

51 Evaluating Performance Benchmarking The process of performance comparison for two or more systems by measurements Benchmark Programs specifically chosen to measure performance A workload that the user hopes will predict the performance of the actual workload Compiler tricks Optimizations in either the architecture or compiler 51

52 Performance Measurement & SPEC benchmark Performance best determined by running a real application Use programs typical of expected workload Or, typical of expected class of applications e.g., compilers/editors, scientific applications, graphics, etc. Small benchmarks nice for architects and designers easy to standardize can be abused SPEC (System Performance Evaluation Cooperative) companies have agreed on a set of real program and inputs valuable indicator of performance (and compiler technology) can still be abused 52

53 CINT2006 for Intel Core i

54 SPEC Power Benchmark Power consumption of server at different workload levels Performance: ssj_ops/sec Power: Watts (Joules/sec) Overall ssj_opsper Watt 10 i0 10 ssj_ops i power i0 i 54

55 SPECpower_ssj2008 for Xeon X

56 Pitfall: Amdahl s Law Improving an aspect of a computer and expecting a proportional improvement in overall performance T improved Taffected improvement factor unaffected Example: multiply accounts for 80s/100s How much improvement in multiply performance to get 5 overall? Can t be done! n Corollary: make the common case fast T 56

57 Fallacy: Low Power at Idle Look back at X4 power benchmark At 10% load: 33% of the peak power (specially configured computer with the best results in 2012) Google data center Mostly operates at 10% 50% load At 100% load less than 1% of the time Consider designing processors to make power proportional to load 57

58 Pitfall: MIPS as a Performance Metric MIPS: Millions of Instructions Per Second Doesn t account for Differences in ISAs between computers Differences in complexity between instructions MIPS Instruction count Execution time10 6 Instruction count Instruction countcpi 10 Clock rate 6 Clock rate 6 CPI10 CPI varies between programs on a given CPU 58

59 1.11 Concluding Remarks Computer designer and programmers Must understand a wider variety of issues. Cost/performance is improving Due to underlying technology development Abstraction Both H/W, S/W designers construct computer systems in hierarchical layers, with each lower layer hiding details from the level above. Instruction set architecture: most important example of abstraction, interface between hardware and low-level software Many implementations with same ISA May preclude introducing innovations that requires the interface to change. Key technologies for modern processors: compilers, silicon New ideas in the computer organization for improved price/performance: pipelining (exploiting parallelism in the processor), caches (exploiting locality of accesses to a memory hierarchy) Execution time: the best performance measure Power is a limiting factor Use parallelism to improve performance 59

60 Concluding Remarks Performance is specific to a particular program/s Total execution time is a consistent summary of performance For a given architecture performance increases come from: increases in clock rate (without adverse CPI affects) improvements in processor organization that lower CPI compiler enhancements that lower CPI and/or instruction count Algorithm/Language choices that affect instruction count Three design criteria 1. High-performance design: Supercomputer and high-end server 2. Low-cost design: Embedded system 3. Cost/performance design: Desktop computer Execution time of real program as the metrics second program instructions program clock cycle instruction seconds clock cycle 60

61 Road Map for This Book Concluding Remarks Five classic components of a computer: datapath, control, memory, input, and output. Datapath: Chapter 3, 4, 6 Control: Chapter 4, 6 Memory: Chapter 5 Input: Chapter 5, 6 Output: Chapter 5, 6 Chapter 4: Pipelining (exploit parallelism) Chapter 5: Memory hierarchy (exploit locality) Chapter 2: Instruction sets (interface between compilers and computes) Chapter 3: Arithmetic operation and data Chapter 6: Multiprocessor 61

62 1.12 Historical Perspective and Further Reading 62

63 Exercises Abstraction 의개념을우리일상생활에서사용하는기기등을예로들어 1-2 문단정도로설명하세요. ( 예 : 자동차, 항공기, 집, 경제, 도시등 ) 과제제출 1.5, 1.11 ( 각자풀어볼것 ) 63