The Future of SPARC64 TM

Transcription

1 The Future of SPARC64 TM Kevin Oltendorf VP, R&D Fujitsu Management Services of America 0

2 Raffle at the Conclusion Your benefits of Grandstand Suite Seats Free Beer, Wine and Fried snacks Early access with Fujitsu private shuttle 1

3 Today s SPARC Enterprise Server Family Server line-up fully adapted to changing business environments Supported OS : Oracle Solaris 10 and Oracle Solaris 11 M-Series SPARC64 VII/VII+ High performance High scalability High reliability applicable to mission critical server Server Consolidation Platform for Broad Range of Applications M CPU(2/4 core) 2.86 GHz M4000 M5000 M8000 M CPU(16 core) 2.66 GHz 8 CPU(32 core) 2.66 GHz 16 CPU(64 core) 3.0 GHz 64CPU(256 core) 3.0 GHz T-Series SPARC T4-1, T4-2, T4-4 High throughput Energy and space saving High Performance up to 4 sockets/32 core The Most Cost efficient Platform for Web and Application Servers T4-1 1CPU(8core) 2.85GHz 2 T4-2 2CPU(16core) 2.85GHz T4-4 4CPU(32core) 3.0GHz

4 Video: SPARC64 X Introduction Evolution from SPARC64 VIIIfx (K computer) 8 core/socket SPARC64 VIIIfx -> 16 core/socket SPARC64 X 1 thread/core -> 2 threads/core <2GHz clock speed -> 3GHz -> 24MB shared L2$ -> ~3 Billion transistors -> 28nm CMOS technology -> 288 GIPS / 102 GB/s (peak) memory throughput -> SWoC (Software on Chip) Hybrid air/water cooling Scalable building block design High Speed Interconnect 3

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6 Fujitsu Processor Development High Performance Technology High Reliability Technology Virtual Machine Architecture Software On Chip HPC-ACE System On Chip Hardware Barrier Multi-core Multi-thread L2$ on Die Non-Blocking $ O-O-O Execution Super-Scalar Single-chip CPU Store Ahead Branch History Prefetch $ ECC Register/ALU Parity Instruction Retry $ Dynamic Degradation RC/RT/History Tr=10M CMOS Al 350nm GS8600 SPARC64 SPARC64 II Tr=30M CMOS Al 250nm / 220nm GS8800B GS8800 SPARC64 GP ~ SPARC64 Processor Tr=190M0 CMOS Cu 130nm Tr=46M CMOS Cu 180nm GS8900 SPARC64 GP Tr=30M CMOS Cu 180nm / 150nm 2000~2003 Tr=400M CMOS Cu 90nm SPARC64 V GS Tr=190M CMOS Cu 130nm Tr=540M CMOS Cu 90nm SPARC64 V + Tr=760M CMOS Cu 45nm Tr=600M CMOS Cu 65nm SPARC64 VI GS Tr=500M CMOS Cu 90nm SPARC64 VII GS21 Mainframe :Technology generation 2004~2007 Tr=1B CMOS Cu 40nm SPARC64 VIIIfx SPARC64 IXfx 2008~2011 Tr=2.95B CMOS Cu 28nm SPARC64 X 2012~

7 SPARC64 X Design Concept Combine UNIX and HPC Fujitsu processor features to realize an extremely high throughput UNIX processor. SPARC64 TM VII/VII+ (UNIX processor) features High CPU frequency (up-to 3GHz) Multicore/Multithread Scalability: up to 64 sockets SPARC64 TM VIIIfx (HPC processor) features HPC-ACE: Innovative ISA extensions to SPARC-V9 High Memory B/W: peak 64GB/s, Embedded Memory Controller Added new features vital to current and future UNIX servers Virtual Machine Architecture Software On Chip Embedded IOC (PCI-GEN3 controller) Direct CPU-CPU interconnect 6

8 SPARC64 X Chip Overview L2 Cache Data DDR3 Interface MAC L2 Cache Control MAC DDR3 Interface L2 Cache Data Architecture Features 16 cores x 2 threads SWoC (Software on Chip) Shared 24 MB L2$ Embedded Memory and IO Controller 28nm CMOS 23.5mm x 25.0mm 2,950M transistors 1,500 signal pins 3GHz Performance (peak) 288GIPS/382GFlops 102GB/s memory throughput 7

9 SPARC64 TM X interconnects SPARC64 TM VII/VII+ interconnects SPARC Enterprise M8000 CPU CPU CPU CPU SC SC MAC MAC MAC MAC SPARC64 TM X interconnects CPU CPU 14.5GB/s SC SC CPU CPU 102GB/s DDR2 DIMMs DDR2 DIMMs DDR2 DIMMs DDR2 DIMMs DDR3 DIMMs DDR3 DIMMs DDR3 DIMMs DDR3 DIMMs SPARC64 TM VII/VII+ interconnects 4 CPUs require 8 additional LSIs to be connected with DIMM DIMM i/f: 4.35GB/s (STREAMtriad) SPARC64 TM X interconnects No additional LSIs to be connected with DIMM DIMM i/f: 65.6GB/s (STREAMtriad) CPU i/f: 14.5GB/s x 5ports (peak) 3 ports: glueless 4way CPU interconnect 2 ports: > 4way CPU 8

10 Reliability, Availability, Serviceability Units Cache (Tag) Cache (Data) Register ALU Cache dynamic degradation HW Instruction Retry History Error detection and correction scheme ECC / Duplicate & Parity ECC / Parity ECC (INT/FP) / Parity(Others) Parity/Residue Yes Yes Yes SPARC64 TM X RAS diagram New RAS features from SPARC64 VII/VII+ Floating-point registers are ECC protected #checkers increased to ~53,000 to identify a failure point more precisely Guarantees Data Integrity 1bit error Correctable 1bit error Detectable 1bit error harmless 9

11 SPECint _rate ,000 20,000 x2 SPARC64 X Prototype provided 15,000 10,000 5,000 11,300 22,445 (estimated) twice the performance of IBM Power 7 server, based on measured estimates. 0 IBM POWER 7 SPARC64 X (64 sockets) The IBM POWER7 result reflects a result published as of November, The SPARC64 X prototype result is a measured estimate run on pre-production hardware. SPEC and SPECint are registered trademarks of the Standard Performance Evaluation Corporation. For the latest SPEC benchmark results, visit 10

12 Software on Chip performance - Highlight NUMBER x430 Crypto x163 HASH (*) x7 Copy x12 Compare x15 (*) : HASH is one of the functions being used frequently in DBMS transactions. 11

13 NUMBER Performance SUM(8B+8B) Chip Throughput x430 x7.7 w/vector w/o Vector 45, Format conversion required between decimal on Database and binary on Processors Exclusive arithmetic unit inside of SPARC64 X offloads the conversion to hardware. Mop/s SPARC64 VII+ (3GHz) SPARC64 X (3GHz) 12

14 Crypto Performance Chip Throughput 50,000 40,000 Decrypt Encrypt 50,000 40,000 Crypto-compliance mandatory for current & future ICT transactions 30,000 20,000 10,000 MB/s 0 X SPARC64 VII+ (3GHz) 46,495 SPARC64 X (3GHz) 30,000 20,000 10,000 MB/s 0 X SPARC64 VII+ (3GHz) 46,880 SPARC64 X (3GHz) SPARC64 X s microarchitecture boosts encryption & decryption processes 13

15 STREAM Benchmark Triad 4,000 3,500 3,000 SPARC64 X prototype provides 2,500 2,000 1,500 X x5 performance of IBM Power 595, based on measured estimates 1, IBM POWER 595 SPARC64 X (64 sockets) SPARC64 X result is measured by pre-production system. Source of IBM POWER 595 data is in 14

16 SPARC64 TM X CPU Summary SPARC64 TM X is Fujitsu s10 th SPARC processor, designed to be used for Fujitsu s next generation UNIX server SPARC64 TM X integrates 16cores + 24MB L2 cache with over 100GB/s(peak) memory bandwidth SPARC64 TM X increases strong RAS features SPARC64 TM X chip is up and running in the lab SPARC64 TM X has shown 7 times throughput of SPARC64 TM VII+ w/o compiler tuning SWoC is effective to accelerate specific software functions Fujitsu will continue to develop SPARC64 TM series 15

17 Cooling 16

18 Smart Cooling Chassis Reduced Size: (No metal heat sinks) LLC Liquid Loop Cooling system Space savings & performance: CPUs & DIMMs much closer, without engineering compromises Straight Cooling Frame Backplane-less Less ventilation space & lower fan power Reduced Size: (50% smaller than prior PSUs with same rated amperage) High -Efficiency/Density PSU New Technologies 17

19 Hybrid Cooling with LLC (Liquid Loop Cooling) Air Cooling + Liquid Cooling Coolant circulates heat from CPUs to a radiator to be air-cooled. Self-contained liquid cooling for System-on-Chip CPU Anti-freeze-like liquid flows through plates, tubes, tanks & radiator. Employs new gasket technology 2 LLCs per Building Block, each cooling 2 CPUs 12x2 (redundant) inline micro-pumps per Building Block Pump rotation and liquid temperature constantly monitored Heatsink-less design allows components to be densely placed Lower latency Saves 3U of space in each 4-socket Building Block Weight savings of 55kg per Building Block Self-contained cooling for the life of the system No maintenance required No external pipes/hoses Liquid Cooling Radiator Pump Air Cooling 18

20 SPARC64 TM X Prototype Systems 4U Prototype Prototype 1U Prototype 19

21 SPARC64 TM X Prototype Power On (Years in development/thousands of staff overcoming challenges) 20

22 Scalable Building Blocks Linear Hardware Scalability Investment Protection: start small, grow very big Maximum 16 Building Blocks tested Linear Performance/Scalability with unique Fujitsu 14.5GB/s Optical Interconnects (no software stack/no device drivers to interrupt OS): Embedded System on Chip IOCs: connect up to 4BBs. For >4BBs, IOBox is used. 21

23 Solaris Operating Environment SPARC64 TM X Prototypes in testing w/solaris 10/11 internal builds sun4v architecture with Oracle VM support (same as T-series) Solaris 10 & 11 Control and Guest Domains High performance and manageability Uniform server management and same OS across all platforms Scalable up to max cores / 2048 threads Investment protection through binary compatibility Long history of Solaris binary compatibility over ten years assures customer investment protection Variety and choice in ISV solutions Many more ISV products available on Solaris TCO reduction through virtualization at no extra cost Virtualization functions such as Oracle VM and software partitioning (Solaris Containers) can be used at no extra cost 22

24 Oracle VM for SPARC Flexible virtualization at the firmware layer Virtual hardware domain has CPU thread-level granularity Multiple OS versions co-exist Redundant Virtual I/O Service Common management interface across SPARC (Same OVM for T-series) Finer granularity ensures the most efficient resource utilization No CPU or Memory virtualization overhead Choice: Hardware or Virtual partitioning + Solaris Containers! S11 Control Domain Application A Application B Application C Application D Solaris 11 Container Solaris 10 Container Oracle Solaris 11 Guest Domain Hypervisor (firmware) Solaris 10 Container Solaris 8/9 Container Oracle Solaris 10 Guest Domain 23

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27 Raffle Your benefits of Grandstand Suite Seats Free Beer, Wine and Fried snacks Early access with Fujitsu private shuttle 26