Puey Wei Tan. Danny Lee. IBM zenterprise 196

Transcription

1 Puey Wei Tan Danny Lee IBM zenterprise 196

2 IBM zenterprise System What is it? IBM s product solutions for mainframe computers. IBM s product models: 700/7000 series System/360 System/370 System/390 zseries System z9 System z10 zenterprise 196 zenterprise 114

3 What and who is it for? What exactly is a mainframe? A computer typically optimized for high reliability, security, high volume and concurrent input/output processing, and substantial storage. Target market of IBM zenterprise 196: Large enterprises and businesses who require maximum reliability, availability, and serviceability for their work.

4 Reliability, availability, serviceability (RAS) Reliability: features that help avoid and detect faults, corrects the corruption when possible or stops and reports the corruption, provides security Availability: features that allow the system to stay operational even when faults occur, disables malfunctioning parts and continues operating Serviceability: features that allow easy diagnosis of the system, early detection of faults, minimal disruption to normal operations when effecting repairs

5 zenterprise 196 Full System 4 multi chip module (MCM) nodes 96 cores ~1.5 GB of total cache 19.5 MB L1 private (SRAM) 144 MB L2 private (SRAM) 576 MB L3 shared (edram) 768 MB L4 shared (edram)

6 zenterprise 196 MCM 6 central processor (CP) chips each 2 shared cache (SC) chips each

7 zenterprise 196 SC Acts as a connectivity chip 96 MB of L4 edram per chip

8 z196 Central Processor (CP) Manufactured in Fishkill, NY Designed for max performance and efficient power consumption Implements z/architecture and backwards compatible with z legacy code

9 z196 Central Processor (CP) General features: 4 cores per chip 5.2 GHz per core clock speed 64 kb L1 instruction cache 128 kb L1 data cache 1.5 MB private L2 cache 24 MB shared L3 cache 512 mm 2 45 nm SOI process z/architecture Out of order execution Core features: Decode, crack, group, map 2 integer units 2 load store units 1 binary fixed point unit 1 decimal fixed point unit 2 co processors per chip

10 z196 CP ISA CISC instructions with cracking to RISC RISC core Instruction mapping Instruction cracking

11 z196 CP Special Features Protection: all registers, L1, L2, and L3 cache are protected CRC checks against all data Everything is checkpointed: GPR, FPR, AR Inline single error correction for L3 and L4 cache

12 z196 CP Special Features Recovery Unit Drains store queue, cuts of core from L3, EX units, registers, registers and register files are reset to checkpointed state Permanent damage: data read out to spare core and data restarted

13 z196 CP Special Features RAIM: redundant array of inexpensive memory 5 channel main memory Groups of 5 DIMMs Up to 3 TB of memory ECC Can be cascaded Supports hot swapping of memory modules Co processors: 2 per chip Hardware cryptography Hardware compression

14 z196 CP Special Features Power Efficiency Detailed power budget and simulation to validate Same power budget as predecessor, z10 50% more logic, 20% high frequency per core Process shrink: 65 nm to 45 nm SOI Power consumption limit set to allow easy upgrades and cooling constraints

15 z196 CP Special Features Careful voltage domain planning 5 supply rails Primary V DD for all logic SRAM/DRAM gets V CS Differential MCIO (DDR3 controller) gets V MEM SCIO, GXIO gets V IO Last rail for test and diagnostics Multiple clock grids High frequency grid only covers core areas 0.5 frequency grid covers most of chip 30% reduction in clock distribution power usage MCIO/GXIO have separate grids for asynchronous operations

16 z196 CP Special Features Fine grained CLK gating Cycle by cycle control Granularity: any latch group in core, nest, cache 60% of groups gated during typical workload Reduced switching power by 25% during typical workloads Pulsed clocks for clocked storage elements

17 z196 CP Special Features MOSFETs with multiple threshold voltages used Super high threshold High threshold Regular threshold Low threshold (<1% of devices on most critical paths) Low threshold MOSFETs have higher performance Reduced total chip leakage power by 30%

18 z196 CP Special Features edram Reduced leakage power by 60% For same area: Triple capacity Higher performance Reduced 4% of overall chip power

19 Recap z196 is targeted for mainframe computing Does it meet RAS? Reliability Availability Serviceability Does it meet IBM s design goal for latest generation mainframe technology?

20