+/- X EN. IGLOO 2 FPGAs LUT4 CIN NC_SR CLK RST. More Resources in Low-Density Devices. Lowest Power. Proven Security. Exceptional Reliability OVFL LO

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1 IGLOO 2 FPGAs Up to 150K LEs SP CO C CIN _BYP NC_SR CLK RST LUT4 I/O ensity UB ] XAUI A_S A[17:0 PCIe Gen2 OVFL LO A B SERES RO +/- X ] C[43:0 SL ] B[17: SHIFT >> 17 ASC SEL_C :0] SN-1[43 More Resources in Low-ensity evices Lowest Power Proven Security Exceptional Reliability SN[43:

2 s Microsemi s Offer More Resources in Low-ensity evices with the Lowest Power, Proven Security, and Exceptional Reliability s are ideal for general purpose functions such as Gigabit or dual-pci Express control planes, bridging functions, input/output (I/O) expansion and conversion, video/image processing, system management, and secure connectivity. Microsemi FPGAs are used by customers in communications, industrial, medical, defense, and aviation markets. Communications Industrial efense Automotive IGLOO2 Features More Resources in Low-ensity evices PCIe Gen2 support in 10K LE High-performance memory subsystem Highest I/O density With Clear Advantages Lowest power Reduces total power by up to 50% 70 mw per 5G SERES (PCIe Gen2) Proven security Protection from overbuilding and cloning Secure boot for FPGA and processors Exceptional reliability SEU immune zero FIT flash FPGA configuration Reliable safety-critical and mission-critical systems 2

3 Architecture s offer 5K 150K LEs with a high-performance memory subsystem, up to 512 KB embedded flash, 2 32 KB embedded static random-access memory (SRAM), two direct memory access (MA) engines, and two double data rate (R) memory controllers. Architecture highlights include: Up to 16 transceiver lanes PCIe Gen2, XAUI/XGXS+, generic epcs mode at 3.2G Up to 150K LEs, 5 Mbits SRAM, 4 Mbits envm Hard 667 Mbps R2/3 controllers Integrated SP processing blocks Power as low as 7 mw standby, typical PA-hardened, AES256, SHA256, on-demand NVM data integrity check SEU-protected/tolerant memories: esrams, R bridges IGLOO 2 FPGA Standard Cell/ SEU Immune Up to 16 Lanes Multi Protocol SERES FlashBased/ SEU Immune PMA PMA PMA PMA PCI Express x1, x2, x4 XAUI XGXS irect Attach x1, x2, x4 High Performance Memory Subsystem COMM_BLK AES256 System Controller SHA256 Math Blocks (18x18) FPGA Fabric Up to 150K Logic Elements, XGMII, irect 20 Bit Bus Micro SRAM (64x18) Large SRAM (1024x18) FIC AHB Bus Matrix envm esram_0 esram_1 PMA HPMA ECC NRBG FIC R Bridge SRAM PUF Math Blocks (18x18) Micro SRAM (64x18) Large SRAM (1024x18) 667 Mbps R Controller/PHY 667 Mbps R Controller/PHY Multi-Standard GPIO (1.2 V 3.3 V, LVS, HSTL/SSTL) AES Advanced Encryption Standard FIC Fabric Interface Controller AHB Advanced High-Performance Bus HPMS High Performance Memory Subsystem APB Advanced Peripheral Bus SHA Secure Hashing Algorithm AXI Advanced extensible Interface XAUI 10 Gbps Attachment Unit Interface R ouble ata Rate XGMII 10 Gigabit Media Independent Interface ECC Elliptical Curve Cryptography XGXS XGMII Extended Sublayer PCI Express R3 Controller Secure Flash 3

4 General Purpose Applications PCIe 1G Control Plane PCIe Gen2 in 10K LE devices with I/O expansion Gigabit PHY MCU 10/100 PHY SERES PCIe USB Security Peripherals R3 RAM R3 RAM FLASH High Performance Memory Subsystem Flash, SRAM LC I2C GPIO FPGA Fabric CPU Multi-Axis Motor Control eterministic and secure multi-axis/ high-rpm solutions Motor control IP and development kit Timing Automation Controller/ Host CPU System Control PWM Timing Inverter Bridge, IGBTs, SiC MOSFETS Host Interface envm, esram PI Control Loop Power Supply/ Conversion Power Management Transforms Sensors: Speed, Torque, Position A/ Conversion Audio Processing, Storage, and Retrieval I2S-to- bridge allows multiple audio recordings and playbacks 2 igital MEMS Microphones Timberwolf ZL38051 Audio Processor I2S Interface Conversion, Buffering & Formatter Interface Flash Host Interface 4 Audio Jack

5 General Purpose Applications Bridging and Co-Processing SERES to bridge CPRI, AC/AC CPRI CPRI FE Co-Processing Memory Subsystem AC/AC Interfacing JES204B Secure Connectivity Best-in-class security data communications and anti-tamper Ultra-low static power for portability Antenna RF Front End Receiver AC Transmitter AC C CU Baseband Processing Crypto Memory Subsystem ata Processing Board Initialization PMBus, instant-on RJ45/SFP PHY PoE P69208 Host Processor I2C PoE Managers e RJ45/SFP O O O PHY PoE P69208 Switch I2C Controller System Control e Controller PMBus Interface PMBus 5 V PoL Supply 3.3 V PoL Supply 2.5 V PoL Supply 1.5 V PoL Supply RJ45/SFP PHY PoE P69208 Clock Management Status LEs 5

6 Features High-Performance Memory Subsystem 64 KB embedded SRAM (esram) Two MA controllers to offload Up to 512 KB embedded nonvolatile data transactions memory (envm) 8-channel peripheral MA (PMA) One /COMM_BLK for data transfer between soft R bridge (2 port) with 64-bit peripherals in fabric and embedded AXI interface esrams, as well as support for Non-blocking, multi-layer AHB bus memory-to-memory transfers matrix allowing multi-master scheme esram and external R memory supporting 4 masters and 8 slaves for efficient data movement Two AHB/APB interfaces to FPGA between embedded real-time fabric (master/slave capable) memories High Performance Memory Subsystem FIC FIC AHB Bus Matrix COMM_BLK envm esram_0 esram_1 PMA HPMA R Bridge 667 Mbps R Controller/PHY 667 Mbps R Controller/PHY SERES Up to 16 lanes at up to 5 Gbps ual-based reference clocks with single-lane rate granularity Tx and Rx PLLs programmable for each lane Reference clock is shared by groups of two lanes Transmitter features Programmable pre/post-emphasis Programmable impedance Programmable amplitude Receiver features Programmable termination Programmable linear equalization Built-in system debug features PRBS gen/chk Constant patterns Loopbacks TXn RXn PMA PCS ASIC IGLOO2 SERES PCI Express Protocol x1, x2, x4 XAUI XGXS 64-bit XGMII 4x20-bit EPCS FPGA Fabric Custom Logic or Custom Protocol, SRIO, JES204x or Custom Protocol Up to 150k Logic Elements Math Block High-performance and poweroptimized multiplication operations Supports signed multiplication (natively) Supports unsigned multiplication Supports dot product: the multiplier computes (A[8:0] B[17:9] + A[17:9] B[8:0]) 29 independent third input C with data width 44-bits completely registered Supports both registered and unregistered inputs and outputs Internal cascade signals (44-bit CIN and COUT) enable cascading of the Math Blocks to support larger accumulator, adder, and subtractor without extra logic Supports loopback capability Adder support: (A B) + C or (A B) + or (A B) + C + Clock-gated input and output registers for power optimizations SUB A [17:0] B [17:0] C [43:0] CARRYIN ARSHFT17 CSEL FBKSEL IGLOO2 Math Block OTP 36 + / >>17 OVFL_CARROUT_SEL 0 CIN [43:0] OVFL_CARRYOUT COUT [43:0] P [46:0] Logic Element A fully permutable 4-input LUT Clock-gated input and output A dedicated carry chain based on the registers for power optimizations carry look-ahead technique A separate flip-flop that can be used independently from the LUT A B C CIN LUT4 IGLOO2 Logic Element SL CO LO RO 6 LUT_BYP SYNC_SR CLK RST

7 esign Resources Libero SoC esign Software Microsemi s Libero SoC design suite offers high productivity with its comprehensive, easy-to-learn, easy-to-adopt development tools that are used for designing with Microsemi s power-efficient flash-based IGLOO2 devices. The suite integrates industry-standard Synopsys Synplify Pro synthesis and Mentor Graphics ModelSim simulation with best-in-class constraints management, debug capabilities, timing analysis, power analysis, secure production programming, and push button design flow. This comprehensive suite features an intuitive design flow with GUI wizards to guide the design process. Its easy-to-adopt single-click synthesis to programming flow integrates industry-standard third-party tools, a rich IP library of irectcores and CompanionCores, and supports complete reference designs and development kits. IGLOO2 Evaluation Kit Gives designers access to s that offer leadership in I/O density, security, reliability, and lowpower for mainstream applications Supports industry-standard interfaces including Gigabit, USB 2.0 OTG,, I2C, and UART Can be powered by a 12 V power supply or the PCIe connector, and includes a FlashPro4 programmer Board features in the FGG484 package (M2GL010T-1FGG484) JTAG/ programming interface Gigabit PHY and RJ45 connector USB 2.0 OTG interface connector 1 GB LPR, 64 MB flash Headers for I2C, UART,, GPIOs 1 Gen2 PCIe edge connector Tx/Rx/Clk SMP pairs Ordering Code Supported evice Price M2GL-EVAL-KIT M2GL010T-1FGG484 $ Intellectual Property Microsemi enhances your design productivity by providing an extensive suite of proven and optimized IP cores for use with Microsemi FPGAs. Our extensive suite of IP cores covers all key markets and applications. Our cores are organized as either Microsemi-developed irectcores or third-party-developed CompanionCores. Most irectcores are available for free within our Libero tool suite and include common communications interfaces, peripherals, and processing elements. Functionality Connectivity SP Memory Controller Processor Security irectcore Examples UART,16550, 429, PCI, JES204B CIC, FFT, FIR, CORIC, RS FIFO, R, QR, SR, MemCtrl, MMC 8051, 8051s, ARM7TMI MII, RGMII, GMII, ES, 3ES, AES, SHA irectcore CompanionCore Functionality CompanionCores Examples Connectivity CAN, CANF, PCIE, VME SP FFT, JPEG, RS, VBMO Memory Controller SRAMR, Flash, S Processor 80188, 80186, LEON3, 6809 Security M5, ARC4, RNG, ZUC, AES, SHA, 802.1ae (MACSec) 7

8 Product Family IGLOO2 evices Features M2GL005 M2GL010 M2GL025 M2GL050 M2GL060 M2GL090 M2GL150 Maximum logic elements (4LUT + FF) 6,060 12,084 27,696 56,340 56,520 86, ,124 Math blocks (18x18) PLLs and CCCs Logic/SP /HPMA/PMA 1 each Fabric interface controllers (FICs) ata security AES256, SHA256, RNG AES256, SHA256, RNG, ECC, PUF envm (KBytes) LSRAM 18K Blocks Memory usram 1K Blocks esram (KBytes) 64 Total RAM (Kbits) R Controllers (count width) x36 High speed Seres lanes PCIe endpoints MSIO (3.3 V) MSIO (2.5 V) User I/O RIO (2.5 V) Total user I/Os Grades Commercial (C), Industrial (I), Military (M) C, I C, I, M * Total logic may vary based on utilization of SP and memories in your design. Please see the IGLOO2 Fabric UG for details. * Feature availablility is package dependent. I/Os per Package Package Options Package type FCS(G)325 VF(G)256 FCS(G)536 VF(G)400 FCV(G)484 TQ(G)144 FG(G)484 FG(G)676 FG(G)896 FC(G)1152 Pitch (mm) Length x width (mm) 11 x x x x x x x x x x 35 evice I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes M2GL005 (S) M2GL010 (S/T/TS) M2GL025 (T/TS) M2GL050 (T/TS) M2GL060 (T/TS) M2GL090 (T/TS) M2GL150 (T/TS) M2GL090 FCS325 is 11x13.5 pkg dim Highlighted devices can migrate vertically in the same package Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA USA Within the USA: +1 (800) Outside the USA: +1 (949) Fax: +1 (949) sales.support@microsemi.com Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world s standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; solutions; Power-over- ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California and has approximately 4,800 employees globally. Learn more at Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided as is, where is and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. IGLOO2 Rev.2-02/17